[llvm] [TableGen] Use StringTable for searchable tables (PR #206252)
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llvm-commits at lists.llvm.org
Sat Jun 27 06:50:35 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
Author: Alexis Engelke (aengelke)
<details>
<summary>Changes</summary>
LLVM has some large searchable tables containing string pointers. This
patch changes two things:
- String references in searchable tables are now always StringTable
offsets; and all code referencing these is updated accordingly. This
often avoids relocations in the data structures, permitting their
placement in .rodata instead of .data.rel.ro and avoids dynamic
relocations.
- The lookup indicies now reference the same string table instead of
storing string pointers, permitting deduplication and also avoids
dynamic relocations.
In an all-target assert build, this changes section sizes as follows:
- .data.rel.ro: -311920
- .rodata: +227712
- .rela.dyn: -308520 (-12855 entries)
Note that due to 32-bit string offsets, most structures also got
smaller. There is room for further size reductions by using 8/16 bit
integers for string offsets where applicable and by permitting
lower-case search indices when most entries are lower-case (avoids
storing all strings twice) -- both can be done in later changes.
---
Patch is 78.86 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206252.diff
19 Files Affected:
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+32-18)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp (+34-33)
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h (+21-16)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+4-1)
- (modified) llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp (+6-6)
- (modified) llvm/lib/Target/ARM/Utils/ARMBaseInfo.h (+4-3)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+6-3)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+3-2)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2-1)
- (modified) llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.cpp (+8-5)
- (modified) llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h (+2-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp (+97-82)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp (+2-2)
- (modified) llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h (+4-3)
- (modified) llvm/test/TableGen/generic-tables-return-range.td (+3-2)
- (modified) llvm/test/TableGen/generic-tables.td (+12-12)
- (modified) llvm/utils/TableGen/SearchableTableEmitter.cpp (+75-18)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6a6b73b8a4c88..a0cf7024ff89d 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1576,11 +1576,12 @@ class AArch64Operand : public MCParsedAsmOperand {
// Lookup the immediate from table of supported immediates.
auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
assert(Desc && "Unknown enum value");
+ StringRef DescRepr = AArch64ExactFPImm::getExactFPImmStr(Desc->Repr);
// Calculate its FP value.
APFloat RealVal(APFloat::IEEEdouble());
auto StatusOrErr =
- RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero);
+ RealVal.convertFromString(DescRepr, APFloat::rmTowardZero);
if (errorToBool(StatusOrErr.takeError()) || *StatusOrErr != APFloat::opOK)
llvm_unreachable("FP immediate is not exact");
@@ -3216,7 +3217,8 @@ ParseStatus AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) {
auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(MCE->getValue());
Operands.push_back(AArch64Operand::CreatePrefetch(
- prfop, RPRFM ? RPRFM->Name : "", S, getContext()));
+ prfop, RPRFM ? AArch64RPRFM::getRPRFMStr(RPRFM->Name) : "", S,
+ getContext()));
return ParseStatus::Success;
}
@@ -3251,9 +3253,10 @@ ParseStatus AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
auto LookupByEncoding = [](unsigned E) {
if (IsSVEPrefetch) {
if (auto Res = AArch64SVEPRFM::lookupSVEPRFMByEncoding(E))
- return std::optional<StringRef>(Res->Name);
+ return std::optional<StringRef>(
+ AArch64SVEPRFM::getSVEPRFMStr(Res->Name));
} else if (auto Res = AArch64PRFM::lookupPRFMByEncoding(E))
- return std::optional<StringRef>(Res->Name);
+ return std::optional<StringRef>(AArch64PRFM::getPRFMStr(Res->Name));
return std::optional<StringRef>();
};
unsigned MaxVal = IsSVEPrefetch ? 15 : 31;
@@ -4056,7 +4059,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!IC)
return TokError("invalid operand for IC instruction");
else if (!IC->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("IC " + std::string(IC->Name) + " requires: ");
+ std::string Str("IC " + std::string(AArch64IC::getICStr(IC->Name)) +
+ " requires: ");
setRequiredFeatureString(IC->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4067,7 +4071,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!DC)
return TokError("invalid operand for DC instruction");
else if (!DC->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("DC " + std::string(DC->Name) + " requires: ");
+ std::string Str("DC " + std::string(AArch64DC::getDCStr(DC->Name)) +
+ " requires: ");
setRequiredFeatureString(DC->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4077,7 +4082,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!AT)
return TokError("invalid operand for AT instruction");
else if (!AT->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("AT " + std::string(AT->Name) + " requires: ");
+ std::string Str("AT " + std::string(AArch64AT::getATStr(AT->Name)) +
+ " requires: ");
setRequiredFeatureString(AT->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4087,7 +4093,9 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!TLBI)
return TokError("invalid operand for TLBI instruction");
else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("TLBI " + std::string(TLBI->Name) + " requires: ");
+ std::string Str("TLBI " +
+ std::string(AArch64TLBI::getTLBIStr(TLBI->Name)) +
+ " requires: ");
setRequiredFeatureString(TLBI->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4100,7 +4108,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!GIC)
return TokError("invalid operand for GIC instruction");
else if (!GIC->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("GIC " + std::string(GIC->Name) + " requires: ");
+ std::string Str("GIC " + std::string(AArch64GIC::getGICStr(GIC->Name)) +
+ " requires: ");
setRequiredFeatureString(GIC->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4111,7 +4120,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!GSB)
return TokError("invalid operand for GSB instruction");
else if (!GSB->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("GSB " + std::string(GSB->Name) + " requires: ");
+ std::string Str("GSB " + std::string(AArch64GSB::getGSBStr(GSB->Name)) +
+ " requires: ");
setRequiredFeatureString(GSB->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4122,7 +4132,9 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (!PLBI)
return TokError("invalid operand for PLBI instruction");
else if (!PLBI->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("PLBI " + std::string(PLBI->Name) + " requires: ");
+ std::string Str("PLBI " +
+ std::string(AArch64PLBI::getPLBIStr(PLBI->Name)) +
+ " requires: ");
setRequiredFeatureString(PLBI->getRequiredFeatures(), Str);
return TokError(Str);
}
@@ -4217,7 +4229,9 @@ bool AArch64AsmParser::parseSyslAlias(StringRef Name, SMLoc NameLoc,
if (!GICR)
return Error(S2, "invalid operand for GICR instruction");
else if (!GICR->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("GICR " + std::string(GICR->Name) + " requires: ");
+ std::string Str("GICR " +
+ std::string(AArch64GICR::getGICRStr(GICR->Name)) +
+ " requires: ");
setRequiredFeatureString(GICR->getRequiredFeatures(), Str);
return Error(S2, Str);
}
@@ -4305,9 +4319,9 @@ ParseStatus AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
if (Value < 0 || Value > 15)
return Error(ExprLoc, "barrier operand out of range");
auto DB = AArch64DB::lookupDBByEncoding(Value);
- Operands.push_back(AArch64Operand::CreateBarrier(Value, DB ? DB->Name : "",
- ExprLoc, getContext(),
- false /*hasnXSModifier*/));
+ StringRef DBStr = DB ? AArch64DB::getDBStr(DB->Name) : "";
+ Operands.push_back(AArch64Operand::CreateBarrier(
+ Value, DBStr, ExprLoc, getContext(), false /*hasnXSModifier*/));
return ParseStatus::Success;
}
@@ -4363,9 +4377,9 @@ AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
if (Value != 16 && Value != 20 && Value != 24 && Value != 28)
return Error(ExprLoc, "barrier operand out of range");
auto DB = AArch64DBnXS::lookupDBnXSByImmValue(Value);
- Operands.push_back(AArch64Operand::CreateBarrier(DB->Encoding, DB->Name,
- ExprLoc, getContext(),
- true /*hasnXSModifier*/));
+ StringRef DBName = AArch64DBnXS::getDBnXSStr(DB->Name);
+ Operands.push_back(AArch64Operand::CreateBarrier(
+ DB->Encoding, DBName, ExprLoc, getContext(), true /*hasnXSModifier*/));
return ParseStatus::Success;
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 9134203a2da2a..2783b559c8f5c 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -879,7 +879,7 @@ bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
O << "\trprfm ";
if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
- O << RPRFM->Name << ", ";
+ O << AArch64RPRFM::getRPRFMStr(RPRFM->Name) << ", ";
else
O << "#" << formatImm(RPRFOp) << ", ";
O << getRegisterName(Rm);
@@ -962,7 +962,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
NeedsReg = IC->NeedsReg;
Ins = "ic\t";
- Name = std::string(IC->Name);
+ Name = std::string(AArch64IC::getICStr(IC->Name));
}
break;
// DC aliases
@@ -974,7 +974,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
NeedsReg = true;
Ins = "dc\t";
- Name = std::string(DC->Name);
+ Name = std::string(AArch64DC::getDCStr(DC->Name));
}
break;
// AT aliases
@@ -985,7 +985,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
NeedsReg = true;
Ins = "at\t";
- Name = std::string(AT->Name);
+ Name = std::string(AArch64AT::getATStr(AT->Name));
}
break;
// Overlaps with AT and DC
@@ -995,11 +995,11 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
if (AT && AT->haveFeatures(STI.getFeatureBits())) {
NeedsReg = true;
Ins = "at\t";
- Name = std::string(AT->Name);
+ Name = std::string(AArch64AT::getATStr(AT->Name));
} else if (DC && DC->haveFeatures(STI.getFeatureBits())) {
NeedsReg = true;
Ins = "dc\t";
- Name = std::string(DC->Name);
+ Name = std::string(AArch64DC::getDCStr(DC->Name));
} else {
return false;
}
@@ -1016,7 +1016,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
STI.hasFeature(AArch64::FeatureTLBID))
OptionalReg = TLBI->RegUse == REG_OPTIONAL;
Ins = "tlbi\t";
- Name = std::string(TLBI->Name);
+ Name = std::string(AArch64TLBI::getTLBIStr(TLBI->Name));
} else if (CnVal == 12) {
if (CmVal != 0) {
// GIC aliases
@@ -1026,7 +1026,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
NeedsReg = GIC->NeedsReg;
Ins = "gic\t";
- Name = std::string(GIC->Name);
+ Name = std::string(AArch64GIC::getGICStr(GIC->Name));
} else {
// GSB aliases
const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByEncoding(Encoding);
@@ -1035,7 +1035,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
NeedsReg = false;
Ins = "gsb\t";
- Name = std::string(GSB->Name);
+ Name = std::string(AArch64GSB::getGSBStr(GSB->Name));
}
} else if (CnVal == 10) {
// PLBI aliases
@@ -1048,7 +1048,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
STI.hasFeature(AArch64::FeatureTLBID))
OptionalReg = PLBI->RegUse == REG_OPTIONAL;
Ins = "plbi\t";
- Name = std::string(PLBI->Name);
+ Name = std::string(AArch64PLBI::getPLBIStr(PLBI->Name));
} else
return false;
@@ -1110,7 +1110,7 @@ bool AArch64InstPrinter::printSyslAlias(const MCInst *MI,
return false;
Ins = "gicr";
- Name = std::string(GICR->Name);
+ Name = std::string(AArch64GICR::getGICRStr(GICR->Name));
} else
return false;
} else
@@ -1159,7 +1159,7 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
return false;
Ins = "tlbip\t";
- Name = std::string(TLBIP->Name);
+ Name = std::string(AArch64TLBIP::getTLBIPStr(TLBIP->Name));
} else
return false;
@@ -1237,7 +1237,7 @@ void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
unsigned svcrop = MO.getImm();
const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
assert(SVCR && "Unexpected SVCR operand!");
- O << SVCR->Name;
+ O << AArch64SVCR::getSVCRStr(SVCR->Name);
}
void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -1543,7 +1543,7 @@ void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned prfop = MI->getOperand(OpNum).getImm();
if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
- O << PRFM->Name;
+ O << AArch64RPRFM::getRPRFMStr(PRFM->Name);
return;
}
@@ -1557,13 +1557,13 @@ void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
unsigned prfop = MI->getOperand(OpNum).getImm();
if (IsSVEPrefetch) {
if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
- O << PRFM->Name;
+ O << AArch64SVEPRFM::getSVEPRFMStr(PRFM->Name);
return;
}
} else {
auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
- O << PRFM->Name;
+ O << AArch64PRFM::getPRFMStr(PRFM->Name);
return;
}
}
@@ -1577,7 +1577,7 @@ void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
unsigned psbhintop = MI->getOperand(OpNum).getImm();
auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
if (PSB)
- O << PSB->Name;
+ O << AArch64PSBHint::getPSBStr(PSB->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(psbhintop);
}
@@ -1588,7 +1588,7 @@ void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
if (BTI)
- O << BTI->Name;
+ O << AArch64BTIHint::getBTIStr(BTI->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(btihintop);
}
@@ -1601,7 +1601,7 @@ void AArch64InstPrinter::printCMHPriorityHintOp(const MCInst *MI,
auto PHint =
AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(priorityhint_op);
if (PHint)
- O << PHint->Name;
+ O << AArch64CMHPriorityHint::getCMHPriorityHintStr(PHint->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(priorityhint_op);
}
@@ -1612,7 +1612,7 @@ void AArch64InstPrinter::printTIndexHintOp(const MCInst *MI, unsigned OpNum,
unsigned tindexhintop = MI->getOperand(OpNum).getImm();
auto TIndex = AArch64TIndexHint::lookupTIndexByEncoding(tindexhintop);
if (TIndex)
- O << TIndex->Name;
+ O << AArch64TIndexHint::getTIndexStr(TIndex->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(tindexhintop);
}
@@ -1965,13 +1965,13 @@ void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
StringRef Name;
if (Opcode == AArch64::ISB) {
auto ISB = AArch64ISB::lookupISBByEncoding(Val);
- Name = ISB ? ISB->Name : "";
+ Name = ISB ? AArch64ISB::getISBStr(ISB->Name) : "";
} else if (Opcode == AArch64::TSB) {
auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
- Name = TSB ? TSB->Name : "";
+ Name = TSB ? AArch64TSB::getTSBStr(TSB->Name) : "";
} else {
auto DB = AArch64DB::lookupDBByEncoding(Val);
- Name = DB ? DB->Name : "";
+ Name = DB ? AArch64DB::getDBStr(DB->Name) : "";
}
if (!Name.empty())
O << Name;
@@ -1987,7 +1987,7 @@ void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
StringRef Name;
auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
- Name = DB ? DB->Name : "";
+ Name = DB ? AArch64DBnXS::getDBnXSStr(DB->Name) : "";
if (!Name.empty())
O << Name;
@@ -2038,7 +2038,7 @@ void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
if (Reg)
- O << Reg->Name;
+ O << AArch64SysReg::getSysRegStr(Reg->Name);
else
O << AArch64SysReg::genericRegisterString(Val);
}
@@ -2065,7 +2065,7 @@ void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
if (Reg)
- O << Reg->Name;
+ O << AArch64SysReg::getSysRegStr(Reg->Name);
else
O << AArch64SysReg::genericRegisterString(Val);
}
@@ -2078,9 +2078,9 @@ void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
- O << PStateImm15->Name;
+ O << AArch64PState::getPStateImm0_15Str(PStateImm15->Name);
else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
- O << PStateImm1->Name;
+ O << AArch64PState::getPStateImm0_1Str(PStateImm1->Name);
else
O << "#" << formatImm(Val);
}
@@ -2106,7 +2106,7 @@ void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned Val = MI->getOperand(OpNum).getImm();
if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
- O << Pat->Name;
+ O << AArch64SVEPredPattern::getSVEPREDPATStr(Pat->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(Val);
}
@@ -2121,7 +2121,7 @@ void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
llvm_unreachable("Invalid vector length specifier");
if (auto Pat =
AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
- O << Pat->Name;
+ O << AArch64SVEVecLenSpecifier::getSVEVECLENSPECIFIERStr(Pat->Name);
else
llvm_unreachable("Invalid vector length specifier");
}
@@ -2234,8 +2234,9 @@ void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
unsigned Val = MI->getOperand(OpNum).getImm();
- markup(O, Markup::Immediate)
- << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
+ markup(O, Markup::Immediate) << "#"
+ << AArch64ExactFPImm::getExactFPImmStr(
+ Val ? Imm1Desc->Repr : Imm0Desc->Repr);
}
void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
@@ -2267,7 +2268,7 @@ void AArch64InstPrinter::printPHintOp(const MCInst *MI, unsigned OpNum,
unsigned Op = MI->getOperand(OpNum).getImm();
auto PH = AArch64PHint::lookupPHintByEncoding(Op);
if (PH)
- O << PH->Name;
+ O << AArch64PHint::getPHintStr(PH->Name);
else
markup(O, Markup::Immediate) << '#' << formatImm(Op);
}
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 1f18af709bd93..bd7faa42449b7 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -24,6 +24,7 @@
#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/StringTable.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TargetParser/SubtargetFeature.h"
@@ -419,12 +420,13 @@ inline static bool isValidCBCond(AArch64CC::CondCode Code) {
} // end namespace AArch64CC
struct SysAlias {
- const char *Name;
+ StringTable::Offset Name;
uint16_t Encoding;
FeatureBitset FeaturesRequired;
- constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
- constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
+ constexpr SysAlias(StringTable::Offset N, uint16_t E)
+ : Name(N), Encoding(E) {}
+ constexpr SysAlias(StringTable::Offset N, uint16_t E, FeatureBitset F)
: Name(N), Encoding(E), FeaturesRequired(F) {}
bool haveFeatures(FeatureBitset ActiveFeatures) const {
@@ -440,25 +442,27 @@ struct SysAlias {
struct SysAliasReg : SysAlias {
bool NeedsReg;
- constexpr SysAliasReg(const char *N, uint16_t E, bool R)
+ constexpr SysAliasReg(StringTable::Offset N, uint16_t E, bool R)
: SysAlias(N, E), NeedsReg(R) {}
- constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
+ constexpr SysAliasReg(StringTable::Offset N, uint16_t E, bool R,
+ FeatureBitset F)
: SysAlias(N, E, F), NeedsReg(R) {}
};
struct SysAliasOptionalReg : SysAlias {
SysAliasRegUse RegUse;
- constexpr SysAliasOptionalReg(const char *N, uint16_t E, ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206252
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