[llvm] [RISCV] Support floating point registers with -fzero-call-used-regs (PR #204929)

[Lucas Chollet via llvm-commits]

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@@ -621,6 +625,23 @@ bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
   return true;
 }
 
+bool RISCVExpandPseudo::expandPseudoClearFPR64(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+  DebugLoc DL = MBBI->getDebugLoc();
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LucasChollet wrote:

Done!

https://github.com/llvm/llvm-project/pull/204929