[llvm] [TargetLowering] Remove isCtlzFast TLI hook (NFC) (PR #206174)
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Fri Jun 26 13:48:15 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/206174
>From b840d00bceb7f4e8249572d90e4b14e0b3f9b77b Mon Sep 17 00:00:00 2001
From: AZero13 <83477269+AZero13 at users.noreply.github.com>
Date: Fri, 26 Jun 2026 16:36:54 -0400
Subject: [PATCH] [TargetLowering] Remove isCtlzFast TLI hook (NFC)
It was literally only used by one function, called by one backend.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 11 ---------
.../CodeGen/SelectionDAG/TargetLowering.cpp | 23 -------------------
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 -
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 ++++++++++--
llvm/lib/Target/PowerPC/PPCISelLowering.h | 4 ----
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 4 +++-
llvm/lib/Target/Sparc/SparcISelLowering.h | 6 +----
llvm/lib/Target/VE/VEISelLowering.h | 2 --
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +----
llvm/lib/Target/X86/X86ISelLowering.h | 2 --
10 files changed, 18 insertions(+), 56 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 7a10a693934fd..2585affae86d9 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -726,11 +726,6 @@ class LLVM_ABI TargetLoweringBase {
return false;
}
- /// Return true if ctlz instruction is fast.
- virtual bool isCtlzFast() const {
- return false;
- }
-
/// Return true if ctpop instruction is fast.
virtual bool isCtpopFast(EVT VT) const {
return isOperationLegal(ISD::CTPOP, VT);
@@ -6003,12 +5998,6 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
SDValue Addr, int JTI,
SelectionDAG &DAG) const;
- // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
- // If we're comparing for equality to zero and isCtlzFast is true, expose the
- // fact that this can be implemented as a ctlz/srl pair, so that the dag
- // combiner can fold the new nodes.
- SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
-
// Return true if `X & Y eq/ne 0` is preferable to `X & Y ne/eq Y`
virtual bool isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) const {
return true;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index cc3deaa83f63b..27a3278727e74 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -12319,29 +12319,6 @@ SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
return CallResult.first;
}
-SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
- SelectionDAG &DAG) const {
- assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
- if (!isCtlzFast())
- return SDValue();
- ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
- SDLoc dl(Op);
- if (isNullConstant(Op.getOperand(1)) && CC == ISD::SETEQ) {
- EVT VT = Op.getOperand(0).getValueType();
- SDValue Zext = Op.getOperand(0);
- if (VT.bitsLT(MVT::i32)) {
- VT = MVT::i32;
- Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
- }
- unsigned Log2b = Log2_32(VT.getSizeInBits());
- SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
- SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
- DAG.getConstant(Log2b, dl, MVT::i32));
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
- }
- return SDValue();
-}
-
SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const {
SDValue Op0 = Node->getOperand(0);
SDValue Op1 = Node->getOperand(1);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 87041e696f0f4..5f87ff18b57fb 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -58,7 +58,6 @@ class HexagonTargetLowering : public TargetLowering {
bool isCheapToSpeculateCttz(Type *) const override { return true; }
bool isCheapToSpeculateCtlz(Type *) const override { return true; }
- bool isCtlzFast() const override { return true; }
bool hasBitTest(SDValue X, SDValue Y) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 76cc06f2b4ed9..b183feafb88c9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3663,8 +3663,19 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
// If we're comparing for equality to zero, expose the fact that this is
// implemented as a ctlz/srl pair on ppc, so that the dag combiner can
// fold the new nodes.
- if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
- return V;
+ if (isNullConstant(RHS) && CC == ISD::SETEQ) {
+ EVT VT = LHS.getValueType();
+ SDValue Zext = LHS;
+ if (VT.bitsLT(MVT::i32)) {
+ VT = MVT::i32;
+ Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHS);
+ }
+ unsigned Log2b = Log2_32(VT.getSizeInBits());
+ SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
+ SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
+ DAG.getConstant(Log2b, dl, MVT::i32));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
+ }
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
// Leave comparisons against 0 and -1 alone for now, since they're usually
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 64be786df7096..428c656cd3ec2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -231,10 +231,6 @@ namespace llvm {
unsigned ElemSizeInBits,
unsigned &Index) const override;
- bool isCtlzFast() const override {
- return true;
- }
-
bool isEqualityCmpFoldedWithSignedCmp() const override {
return false;
}
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index bd1ca913a258e..59df62fbebd6b 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3705,7 +3705,9 @@ bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
return false;
}
-bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
+bool SparcTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
+ return Subtarget->isVIS3();
+}
bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
// We lack native cttz, however,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h
index 5098480e192a6..21c99aa64600d 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.h
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.h
@@ -171,11 +171,7 @@ namespace llvm {
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
- bool isCtlzFast() const override;
-
- bool isCheapToSpeculateCtlz(Type *Ty) const override {
- return isCtlzFast();
- }
+ bool isCheapToSpeculateCtlz(Type *Ty) const override;
bool isCheapToSpeculateCttz(Type *Ty) const override;
diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h
index 487804194757e..5d8a9a8df22aa 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -289,8 +289,6 @@ class VETargetLowering : public TargetLowering {
bool hasStandaloneRem(EVT) const override { return false; }
// VE LDZ instruction returns 64 if the input is zero.
bool isCheapToSpeculateCtlz(Type *) const override { return true; }
- // VE LDZ instruction is fast.
- bool isCtlzFast() const override { return true; }
// VE has NND instruction.
bool hasAndNot(SDValue Y) const override;
/// } Target Optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b95ac78f50049..cfdbbf4dc972b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3682,10 +3682,6 @@ bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
return true;
}
-bool X86TargetLowering::isCtlzFast() const {
- return Subtarget.hasFastLZCNT();
-}
-
bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
const Instruction &AndI) const {
return true;
@@ -53333,7 +53329,7 @@ static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) {
static SDValue combineOrCmpEqZeroToCtlzSrl(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
- if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast())
+ if (DCI.isBeforeLegalize() || !Subtarget.hasFastLZCNT())
return SDValue();
auto isORCandidate = [](SDValue N) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 0d05c5772a707..843a9d04151d4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -236,8 +236,6 @@ namespace llvm {
bool isCheapToSpeculateCtlz(Type *Ty) const override;
- bool isCtlzFast() const override;
-
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
// If the pair to store is a mixture of float and int values, we will
// save two bitwise instructions and one float-to-int instruction and
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