[llvm] a1ac1c5 - AMDGPU: Avoid codegening the default target in a few tests (#206160)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 12:52:24 PDT 2026
Author: Matt Arsenault
Date: 2026-06-26T19:52:19Z
New Revision: a1ac1c5f6b2516f8c0c8b0f567c8cfa236189700
URL: https://github.com/llvm/llvm-project/commit/a1ac1c5f6b2516f8c0c8b0f567c8cfa236189700
DIFF: https://github.com/llvm/llvm-project/commit/a1ac1c5f6b2516f8c0c8b0f567c8cfa236189700.diff
LOG: AMDGPU: Avoid codegening the default target in a few tests (#206160)
Added:
Modified:
llvm/test/CodeGen/AMDGPU/infinite-loop.ll
llvm/test/CodeGen/AMDGPU/ipra.ll
llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/infinite-loop.ll
index df635925b87df..f61807b365d83 100644
--- a/llvm/test/CodeGen/AMDGPU/infinite-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/infinite-loop.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
-; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
+; RUN: opt -mtriple=amdgcn-- -mcpu=gfx600 -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
define amdgpu_kernel void @infinite_loop(ptr addrspace(1) %out) {
; SI-LABEL: infinite_loop:
@@ -27,7 +27,6 @@ define amdgpu_kernel void @infinite_loop(ptr addrspace(1) %out) {
; IR-NEXT: br i1 true, label [[LOOP]], label [[DUMMYRETURNBLOCK:%.*]]
; IR: DummyReturnBlock:
; IR-NEXT: ret void
-;
entry:
br label %loop
@@ -61,7 +60,6 @@ define amdgpu_kernel void @infinite_loop_callbr(ptr addrspace(1) %out) {
; IR-NEXT: to label [[LOOP]] []
; IR: DummyReturnBlock:
; IR-NEXT: ret void
-;
entry:
callbr void asm "", ""() to label %loop []
@@ -101,7 +99,6 @@ define amdgpu_kernel void @infinite_loop_ret(ptr addrspace(1) %out) {
; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]]
; IR: UnifiedReturnBlock:
; IR-NEXT: ret void
-;
entry:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%cond = icmp eq i32 %tmp, 1
@@ -140,16 +137,15 @@ define amdgpu_kernel void @infinite_loop_ret_callbr(ptr addrspace(1) %out) {
; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
; IR-NEXT: [[COND32:%.*]] = zext i1 [[COND]] to i32
; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND32]])
-; IR-NEXT: to label [[LOOP:%.*]] [label %UnifiedReturnBlock]
+; IR-NEXT: to label [[LOOP:%.*]] [label [[UNIFIEDRETURNBLOCK:%.*]]]
; IR: loop:
; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
-; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
+; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
; IR: TransitionBlock:
; IR-NEXT: callbr void asm "", ""()
; IR-NEXT: to label [[LOOP]] []
; IR: UnifiedReturnBlock:
; IR-NEXT: ret void
-;
entry:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%cond = icmp eq i32 %tmp, 1
@@ -214,7 +210,6 @@ define amdgpu_kernel void @infinite_loops(ptr addrspace(1) %out) {
; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]]
; IR: DummyReturnBlock:
; IR-NEXT: ret void
-;
entry:
br i1 poison, label %loop1, label %loop2
@@ -253,7 +248,7 @@ define amdgpu_kernel void @infinite_loops_callbr(ptr addrspace(1) %out) {
; IR-LABEL: @infinite_loops_callbr(
; IR-NEXT: entry:
; IR-NEXT: callbr void asm "", "r,!i"(i32 poison)
-; IR-NEXT: to label [[LOOP1:%.*]] [label %loop2]
+; IR-NEXT: to label [[LOOP1:%.*]] [label [[LOOP2:%.*]]]
; IR: loop1:
; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[DUMMYRETURNBLOCK:%.*]]
@@ -265,10 +260,9 @@ define amdgpu_kernel void @infinite_loops_callbr(ptr addrspace(1) %out) {
; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK1:%.*]], label [[DUMMYRETURNBLOCK]]
; IR: TransitionBlock1:
; IR-NEXT: callbr void asm "", ""()
-; IR-NEXT: to label [[LOOP2:%.*]] []
+; IR-NEXT: to label [[LOOP2]] []
; IR: DummyReturnBlock:
; IR-NEXT: ret void
-;
entry:
callbr void asm "", "r,!i"(i32 poison) to label %loop1 [label %loop2]
@@ -310,7 +304,6 @@ define amdgpu_kernel void @infinite_loop_nest_ret(ptr addrspace(1) %out) {
; SI-NEXT: ; %bb.4: ; %loop.exit.guard
; SI-NEXT: ; in Loop: Header=BB6_2 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[2:3]
-; SI-NEXT: s_mov_b64 vcc, 0
; SI-NEXT: s_branch .LBB6_2
; SI-NEXT: .LBB6_5: ; %UnifiedReturnBlock
; SI-NEXT: s_endpgm
@@ -329,7 +322,6 @@ define amdgpu_kernel void @infinite_loop_nest_ret(ptr addrspace(1) %out) {
; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]]
; IR: UnifiedReturnBlock:
; IR-NEXT: ret void
-;
entry:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%cond1 = icmp ne i32 %tmp, 1 ; avoid following BB optimizing away through the domination
@@ -371,11 +363,12 @@ define amdgpu_kernel void @infinite_loop_nest_ret_callbr(ptr addrspace(1) %out)
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: ;;#ASMSTART
; SI-NEXT: ;;#ASMEND
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: s_mov_b64 vcc, s[0:1]
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: s_mov_b64 vcc, s[0:1]
+; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz .LBB7_2
; SI-NEXT: ; %bb.4: ; %TransitionBlock.target.outer_loop
; SI-NEXT: ; in Loop: Header=BB7_3 Depth=1
@@ -391,7 +384,7 @@ define amdgpu_kernel void @infinite_loop_nest_ret_callbr(ptr addrspace(1) %out)
; IR-NEXT: [[COND1:%.*]] = icmp ne i32 [[TMP]], 1
; IR-NEXT: [[COND1_32:%.*]] = zext i1 [[COND1]] to i32
; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND1_32]])
-; IR-NEXT: to label [[OUTER_LOOP:%.*]] [label %UnifiedReturnBlock]
+; IR-NEXT: to label [[OUTER_LOOP:%.*]] [label [[UNIFIEDRETURNBLOCK:%.*]]]
; IR: outer_loop:
; IR-NEXT: callbr void asm "", ""()
; IR-NEXT: to label [[INNER_LOOP:%.*]] []
@@ -399,13 +392,12 @@ define amdgpu_kernel void @infinite_loop_nest_ret_callbr(ptr addrspace(1) %out)
; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
; IR-NEXT: [[COND3_32:%.*]] = zext i1 [[COND3]] to i32
-; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
+; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
; IR: TransitionBlock:
; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND3_32]])
-; IR-NEXT: to label [[INNER_LOOP]] [label %outer_loop]
+; IR-NEXT: to label [[INNER_LOOP]] [label [[OUTER_LOOP]]]
; IR: UnifiedReturnBlock:
; IR-NEXT: ret void
-;
entry:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%cond1 = icmp ne i32 %tmp, 1 ; avoid following BB optimizing away through the domination
diff --git a/llvm/test/CodeGen/AMDGPU/ipra.ll b/llvm/test/CodeGen/AMDGPU/ipra.ll
index 1e3678d278695..ec533dae0afd0 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s
; Kernels are not called, so there is no call preserved mask.
; GCN-LABEL: {{^}}kernel:
@@ -40,13 +40,13 @@ define amdgpu_kernel void @kernel_call() #0 {
}
; GCN-LABEL: {{^}}func_regular_call:
-; GCN-NOT: buffer_load
-; GCN-NOT: readlane
+; GCN: v_writelane_b32 v9, s30, 0
+; GCN: v_writelane_b32 v9, s31, 1
; GCN: flat_load_dword v8
; GCN: s_swappc_b64
-; GCN-NOT: buffer_load
-; GCN-NOT: readlane
+; GCN: v_readlane_b32 s30, v9, 0
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
+; GCN: v_readlane_b32 s31, v9, 1
; GCN: ; TotalNumSgprs: 34
; GCN: ; NumVgprs: 10
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
index d6fec18e81efe..e4e1d6c99de6a 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt -S -mtriple=amdgcn--amdhsa -passes=amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=OPT %s
-; RUN: llc -mtriple=amdgcn--amdhsa < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=GCN %s
; Opt checks from utils/update_test_checks.py, llc checks from utils/update_llc_test_checks.py, both modified.
@@ -43,16 +43,16 @@ define void @f0() {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s15
; GCN-NEXT: s_ashr_i32 s5, s15, 31
+; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_getpc_b64 s[6:7]
; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table at rel32@lo+4
; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table at rel32@hi+12
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_add_u32 s4, s6, s4
; GCN-NEXT: s_addc_u32 s5, s7, s5
; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
+; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_read_b32 v1, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_f32_e32 v1, v1, v1
@@ -82,16 +82,16 @@ define void @f1() {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s15
; GCN-NEXT: s_ashr_i32 s5, s15, 31
+; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_getpc_b64 s[6:7]
; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table at rel32@lo+8
; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table at rel32@hi+16
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_add_u32 s4, s6, s4
; GCN-NEXT: s_addc_u32 s5, s7, s5
; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
+; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_read_u16 v1, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mul_lo_u32 v1, v1, 3
@@ -121,16 +121,16 @@ define void @f2() {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s15
; GCN-NEXT: s_ashr_i32 s5, s15, 31
+; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_getpc_b64 s[6:7]
; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table at rel32@lo+12
; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table at rel32@hi+20
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_add_u32 s4, s6, s4
; GCN-NEXT: s_addc_u32 s5, s7, s5
; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
+; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_read_b64 v[0:1], v2
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
@@ -160,16 +160,16 @@ define void @f3() {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s15
; GCN-NEXT: s_ashr_i32 s5, s15, 31
+; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_getpc_b64 s[6:7]
; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table at rel32@lo+16
; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table at rel32@hi+24
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4
; GCN-NEXT: s_add_u32 s4, s6, s4
; GCN-NEXT: s_addc_u32 s5, s7, s5
; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
+; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_read_u8 v1, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mul_lo_u32 v1, v1, 5
@@ -217,28 +217,28 @@ define amdgpu_kernel void @k01() {
;
; GCN-LABEL: k01:
; GCN: ; %bb.0:
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: s_add_i32 s12, s12, s17
; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT: s_add_u32 s0, s0, s17
; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mov_b32 s20, s16
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, f0 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, f0 at gotpcrel32@hi+12
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: s_mov_b32 s20, s16
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: s_mov_b32 s13, s15
+; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s15, 0
; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]
; GCN-NEXT: s_mov_b32 s14, s20
+; GCN-NEXT: s_mov_b32 s15, 0
+; GCN-NEXT: s_mov_b32 s32, 0
+; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GCN-NEXT: s_getpc_b64 s[4:5]
@@ -268,28 +268,28 @@ define amdgpu_kernel void @k23() {
;
; GCN-LABEL: k23:
; GCN: ; %bb.0:
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: s_add_i32 s12, s12, s17
; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT: s_add_u32 s0, s0, s17
; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mov_b32 s20, s16
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, f2 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, f2 at gotpcrel32@hi+12
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: s_mov_b32 s20, s16
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: s_mov_b32 s13, s15
+; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s15, 2
; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]
; GCN-NEXT: s_mov_b32 s14, s20
+; GCN-NEXT: s_mov_b32 s15, 2
+; GCN-NEXT: s_mov_b32 s32, 0
+; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GCN-NEXT: s_getpc_b64 s[4:5]
@@ -322,28 +322,28 @@ define amdgpu_kernel void @k123() {
;
; GCN-LABEL: k123:
; GCN: ; %bb.0:
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: s_add_i32 s12, s12, s17
; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT: s_add_u32 s0, s0, s17
; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mov_b32 s20, s16
-; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 s12, s14
-; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, f1 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, f1 at gotpcrel32@hi+12
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: s_mov_b32 s20, s16
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: s_mov_b32 s13, s15
+; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
-; GCN-NEXT: s_mov_b32 s15, 1
; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]
; GCN-NEXT: s_mov_b32 s14, s20
+; GCN-NEXT: s_mov_b32 s15, 1
+; GCN-NEXT: s_mov_b32 s32, 0
+; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GCN-NEXT: v_mov_b32_e32 v0, 0
@@ -353,11 +353,11 @@ define amdgpu_kernel void @k123() {
; GCN-NEXT: s_add_u32 s4, s4, f2 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, f2 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0
+; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]
+; GCN-NEXT: s_mov_b64 s[6:7], s[16:17]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GCN-NEXT: ds_write_b8 v0, v1 offset:2
-; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]
-; GCN-NEXT: s_mov_b64 s[6:7], s[16:17]
; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll b/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
index 42f9532e96332..7ca5e648714d8 100644
--- a/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=amdgcn | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck %s -check-prefixes=CHECK
declare dso_local void @main()
@@ -29,8 +29,8 @@ define dso_local void @normal() "frame-pointer"="all" {
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: s_waitcnt expcnt(0)
; CHECK-NEXT: v_writelane_b32 v40, s16, 2
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_getpc_b64 s[16:17]
; CHECK-NEXT: s_add_u32 s16, s16, main at rel32@lo+4
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