[llvm] [AMDGPU] Select `V_MOV_B64_e32` directly if a target supports it (PR #206135)
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llvm-commits at lists.llvm.org
Fri Jun 26 10:48:55 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Shilei Tian (shiltian)
<details>
<summary>Changes</summary>
---
Patch is 52.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206135.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+30)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll (+192-204)
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll (+25-26)
- (modified) llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll (+3-2)
- (added) llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll (+119)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 750cb1973e21f..4456a7772828c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2635,6 +2635,36 @@ let True16Predicate = UseRealTrue16Insts in {
/// conservative MachineCSE. If we end up with an s_mov_b64 + copy to
/// vgpr pattern, MachineCSE will not perform the CSE which occurs
/// after operand folding.
+let SubtargetPredicate = HasVMovB64Inst, AddedComplexity = 2 in {
+ def : GCNPat <
+ (VGPRImm<(i64 InlineImm64)>:$imm),
+ (V_MOV_B64_e32 InlineImm64:$imm)
+ >;
+
+ def : GCNPat <
+ (VGPRImm<(i64 i64imm_32bit)>:$imm),
+ (V_MOV_B64_e32 i64imm_32bit:$imm)
+ >;
+
+ def : GCNPat <
+ (VGPRImm<(f64 InlineImmFP64)>:$imm),
+ (V_MOV_B64_e32 (i64 (bitcast_fpimm_to_i64 $imm)))
+ >;
+}
+
+let SubtargetPredicate = HasVMovB64Inst, OtherPredicates = [Has64BitLiterals],
+ AddedComplexity = 2 in {
+ def : GCNPat <
+ (VGPRImm<(i64 imm)>:$imm),
+ (V_MOV_B64_e32 imm:$imm)
+ >;
+
+ def : GCNPat <
+ (VGPRImm<(f64 fpimm)>:$imm),
+ (V_MOV_B64_e32 (i64 (bitcast_fpimm_to_i64 $imm)))
+ >;
+}
+
let AddedComplexity = 1 in {
// V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO can be used with any 64-bit
// immediate and wil be expanded as needed, but we will only use these patterns
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
index 55c076375fac4..eae7c22dcff64 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
@@ -106,16 +106,16 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
+; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
; AGPR-NEXT: v_mov_b32_e32 v16, s16
-; AGPR-NEXT: v_mov_b32_e32 v17, s17
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15]
-; AGPR-NEXT: v_mov_b32_e32 v18, s18
-; AGPR-NEXT: v_mov_b32_e32 v19, s19
; AGPR-NEXT: v_mov_b32_e32 v8, s20
; AGPR-NEXT: v_mov_b32_e32 v9, s21
; AGPR-NEXT: v_mov_b32_e32 v10, s22
; AGPR-NEXT: v_mov_b32_e32 v11, s23
-; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
+; AGPR-NEXT: v_mov_b32_e32 v17, s17
+; AGPR-NEXT: v_mov_b32_e32 v18, s18
+; AGPR-NEXT: v_mov_b32_e32 v19, s19
; AGPR-NEXT: s_nop 4
; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
; AGPR-NEXT: s_waitcnt vmcnt(0)
@@ -164,12 +164,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPR-NEXT: v_mov_b32_e32 v48, s16
-; VGPR-NEXT: v_mov_b32_e32 v49, s17
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15]
+; VGPR-NEXT: v_mov_b32_e32 v49, s17
; VGPR-NEXT: v_mov_b32_e32 v50, s18
; VGPR-NEXT: v_mov_b32_e32 v51, s19
-; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPR-NEXT: s_nop 8
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
@@ -179,12 +179,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
+; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: v_mov_b32_e32 v0, s20
; VGPR-NEXT: v_mov_b32_e32 v1, s21
; VGPR-NEXT: v_mov_b32_e32 v2, s22
; VGPR-NEXT: v_mov_b32_e32 v3, s23
-; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: s_nop 0
@@ -303,16 +303,16 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
+; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
; AGPR-NEXT: v_mov_b32_e32 v16, s16
-; AGPR-NEXT: v_mov_b32_e32 v17, s17
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15] cbsz:2 abid:3 blgp:1
-; AGPR-NEXT: v_mov_b32_e32 v18, s18
-; AGPR-NEXT: v_mov_b32_e32 v19, s19
; AGPR-NEXT: v_mov_b32_e32 v8, s20
; AGPR-NEXT: v_mov_b32_e32 v9, s21
; AGPR-NEXT: v_mov_b32_e32 v10, s22
; AGPR-NEXT: v_mov_b32_e32 v11, s23
-; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
+; AGPR-NEXT: v_mov_b32_e32 v17, s17
+; AGPR-NEXT: v_mov_b32_e32 v18, s18
+; AGPR-NEXT: v_mov_b32_e32 v19, s19
; AGPR-NEXT: s_nop 4
; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
; AGPR-NEXT: s_waitcnt vmcnt(0)
@@ -361,12 +361,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPR-NEXT: v_mov_b32_e32 v48, s16
-; VGPR-NEXT: v_mov_b32_e32 v49, s17
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15] cbsz:2 abid:3 blgp:1
+; VGPR-NEXT: v_mov_b32_e32 v49, s17
; VGPR-NEXT: v_mov_b32_e32 v50, s18
; VGPR-NEXT: v_mov_b32_e32 v51, s19
-; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPR-NEXT: s_nop 8
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
@@ -376,12 +376,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
+; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: v_mov_b32_e32 v0, s20
; VGPR-NEXT: v_mov_b32_e32 v1, s21
; VGPR-NEXT: v_mov_b32_e32 v2, s22
; VGPR-NEXT: v_mov_b32_e32 v3, s23
-; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; VGPR-NEXT: s_waitcnt vmcnt(0)
; VGPR-NEXT: s_nop 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
index a1fe463de1c54..1dbe1a9ee86e3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
@@ -378,12 +378,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; SDAG-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; SDAG-NEXT: v_mov_b64_e32 v[38:39], 0
; SDAG-NEXT: v_mov_b32_e32 v48, s16
-; SDAG-NEXT: v_mov_b32_e32 v49, s17
; SDAG-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[40:43], v[44:47], v[0:15]
+; SDAG-NEXT: v_mov_b32_e32 v49, s17
; SDAG-NEXT: v_mov_b32_e32 v50, s18
; SDAG-NEXT: v_mov_b32_e32 v51, s19
-; SDAG-NEXT: v_mov_b64_e32 v[38:39], 0
; SDAG-NEXT: s_nop 8
; SDAG-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -393,12 +393,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: v_mov_b32_e32 v0, s20
; SDAG-NEXT: v_mov_b32_e32 v1, s21
; SDAG-NEXT: v_mov_b32_e32 v2, s22
; SDAG-NEXT: v_mov_b32_e32 v3, s23
-; SDAG-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_nop 0
@@ -496,16 +496,16 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; HEURRC-NEXT: v_accvgpr_write_b32 a13, s21
; HEURRC-NEXT: v_accvgpr_write_b32 a14, s22
; HEURRC-NEXT: v_accvgpr_write_b32 a15, s23
+; HEURRC-NEXT: v_mov_b64_e32 v[6:7], 0
; HEURRC-NEXT: v_mov_b32_e32 v16, s16
-; HEURRC-NEXT: v_mov_b32_e32 v17, s17
; HEURRC-NEXT: v_mfma_f32_32x32x16_f16 a[16:31], v[8:11], v[12:15], a[0:15]
-; HEURRC-NEXT: v_mov_b32_e32 v18, s18
-; HEURRC-NEXT: v_mov_b32_e32 v19, s19
; HEURRC-NEXT: v_mov_b32_e32 v8, s20
; HEURRC-NEXT: v_mov_b32_e32 v9, s21
; HEURRC-NEXT: v_mov_b32_e32 v10, s22
; HEURRC-NEXT: v_mov_b32_e32 v11, s23
-; HEURRC-NEXT: v_mov_b64_e32 v[6:7], 0
+; HEURRC-NEXT: v_mov_b32_e32 v17, s17
+; HEURRC-NEXT: v_mov_b32_e32 v18, s18
+; HEURRC-NEXT: v_mov_b32_e32 v19, s19
; HEURRC-NEXT: s_nop 4
; HEURRC-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
; HEURRC-NEXT: s_waitcnt vmcnt(0)
@@ -554,12 +554,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; VGPRRC-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPRRC-NEXT: v_mov_b32_e32 v48, s16
-; VGPRRC-NEXT: v_mov_b32_e32 v49, s17
; VGPRRC-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[40:43], v[44:47], v[0:15]
+; VGPRRC-NEXT: v_mov_b32_e32 v49, s17
; VGPRRC-NEXT: v_mov_b32_e32 v50, s18
; VGPRRC-NEXT: v_mov_b32_e32 v51, s19
-; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPRRC-NEXT: s_nop 8
; VGPRRC-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
@@ -569,12 +569,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
+; VGPRRC-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: v_mov_b32_e32 v0, s20
; VGPRRC-NEXT: v_mov_b32_e32 v1, s21
; VGPRRC-NEXT: v_mov_b32_e32 v2, s22
; VGPRRC-NEXT: v_mov_b32_e32 v3, s23
-; VGPRRC-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: s_nop 0
@@ -744,12 +744,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; SDAG-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; SDAG-NEXT: v_mov_b64_e32 v[38:39], 0
; SDAG-NEXT: v_mov_b32_e32 v48, s16
-; SDAG-NEXT: v_mov_b32_e32 v49, s17
; SDAG-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[40:43], v[44:47], v[0:15] cbsz:2 abid:3 blgp:1
+; SDAG-NEXT: v_mov_b32_e32 v49, s17
; SDAG-NEXT: v_mov_b32_e32 v50, s18
; SDAG-NEXT: v_mov_b32_e32 v51, s19
-; SDAG-NEXT: v_mov_b64_e32 v[38:39], 0
; SDAG-NEXT: s_nop 8
; SDAG-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -759,12 +759,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: v_mov_b32_e32 v0, s20
; SDAG-NEXT: v_mov_b32_e32 v1, s21
; SDAG-NEXT: v_mov_b32_e32 v2, s22
; SDAG-NEXT: v_mov_b32_e32 v3, s23
-; SDAG-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_nop 0
@@ -862,16 +862,16 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; HEURRC-NEXT: v_accvgpr_write_b32 a13, s21
; HEURRC-NEXT: v_accvgpr_write_b32 a14, s22
; HEURRC-NEXT: v_accvgpr_write_b32 a15, s23
+; HEURRC-NEXT: v_mov_b64_e32 v[6:7], 0
; HEURRC-NEXT: v_mov_b32_e32 v16, s16
-; HEURRC-NEXT: v_mov_b32_e32 v17, s17
; HEURRC-NEXT: v_mfma_f32_32x32x16_f16 a[16:31], v[8:11], v[12:15], a[0:15] cbsz:2 abid:3 blgp:1
-; HEURRC-NEXT: v_mov_b32_e32 v18, s18
-; HEURRC-NEXT: v_mov_b32_e32 v19, s19
; HEURRC-NEXT: v_mov_b32_e32 v8, s20
; HEURRC-NEXT: v_mov_b32_e32 v9, s21
; HEURRC-NEXT: v_mov_b32_e32 v10, s22
; HEURRC-NEXT: v_mov_b32_e32 v11, s23
-; HEURRC-NEXT: v_mov_b64_e32 v[6:7], 0
+; HEURRC-NEXT: v_mov_b32_e32 v17, s17
+; HEURRC-NEXT: v_mov_b32_e32 v18, s18
+; HEURRC-NEXT: v_mov_b32_e32 v19, s19
; HEURRC-NEXT: s_nop 4
; HEURRC-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
; HEURRC-NEXT: s_waitcnt vmcnt(0)
@@ -920,12 +920,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; VGPRRC-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPRRC-NEXT: v_mov_b32_e32 v48, s16
-; VGPRRC-NEXT: v_mov_b32_e32 v49, s17
; VGPRRC-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[40:43], v[44:47], v[0:15] cbsz:2 abid:3 blgp:1
+; VGPRRC-NEXT: v_mov_b32_e32 v49, s17
; VGPRRC-NEXT: v_mov_b32_e32 v50, s18
; VGPRRC-NEXT: v_mov_b32_e32 v51, s19
-; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], 0
; VGPRRC-NEXT: s_nop 8
; VGPRRC-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
@@ -935,12 +935,12 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
+; VGPRRC-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
+; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: v_mov_b32_e32 v0, s20
; VGPRRC-NEXT: v_mov_b32_e32 v1, s21
; VGPRRC-NEXT: v_mov_b32_e32 v2, s22
; VGPRRC-NEXT: v_mov_b32_e32 v3, s23
-; VGPRRC-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
-; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
; VGPRRC-NEXT: s_waitcnt vmcnt(0)
; VGPRRC-NEXT: s_nop 0
@@ -2858,39 +2858,36 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; SDAG-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
; SDAG-NEXT: v_mov_b64_e32 v[32:33], 48
; SDAG-NEXT: v_mov_b64_e32 v[34:35], 32
+; SDAG-NEXT: v_mov_b64_e32 v[36:37], 16
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-NEXT: v_mov_b32_e32 v36, s24
-; SDAG-NEXT: v_mov_b32_e32 v37, s25
-; SDAG-NEXT: v_mov_b32_e32 v38, s26
-; SDAG-NEXT: v_mov_b32_e32 v39, s27
-; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
-; SDAG-NEXT: v_mov_b32_e32 v40, s28
-; SDAG-NEXT: v_mov_b32_e32 v41, s29
-; SDAG-NEXT: v_mov_b32_e32 v42, s30
-; SDAG-NEXT: v_mov_b32_e32 v43, s31
-; SDAG-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
-; SDAG-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
-; SDAG-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
-; SDAG-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
-; SDAG-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
-; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
-; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
-; SDAG-NEXT: s_nop 1
-; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[0:15], v[36:39], v[40:43], v[16:31]
+; SDAG-NEXT: v_mov_b32_e32 v40, s24
+; SDAG-NEXT: v_mov_b32_e32 v41, s25
+; SDAG-NEXT: v_mov_b32_e32 v42, s26
+; SDAG-NEXT: v_mov_b32_e32 v43, s27
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; SDAG-NEXT: v_mov_b32_e32 v44, s28
+; SDAG-NEXT: v_mov_b32_e32 v45, s29
+; SDAG-NEXT: v_mov_b32_e32 v46, s30
+; SDAG-NEXT: v_mov_b32_e32 v47, s31
+; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
+; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
+; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
+; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
+; SDAG-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; SDAG-NEXT: v_mov_b64_e32 v[38:39], 0
+; SDAG-NEXT: s_nop 0
+; SDAG-NEXT: v_mfma_i32_32x32x32_i8 v[16:31], v[40:43], v[44:47], v[0:15]
; SDAG-NEXT: s_nop 11
-; SDAG-NEXT: global_store_dwordx4 v[32:33], v[12:15], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
-; SDAG-NEXT: global_store_dwordx4 v[34:35], v[8:11], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[34:35], v[24:27], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
-; SDAG-NEXT: s_nop 0
-; SDAG-NEXT: v_mov_b64_e32 v[8:9], 16
-; SDAG-NEXT: global_store_dwordx4 v[8:9], v[4:7], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[36:37], v[20:23], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
-; SDAG-NEXT: s_nop 0
-; SDAG-NEXT: v_mov_b64_e32 v[4:5], 0
-; SDAG-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
-; SDAG-NEXT: s_nop 0
; SDAG-NEXT: v_mov_b32_e32 v0, s16
; SDAG-NEXT: v_mov_b32_e32 v1, s17
; SDAG-NEXT: v_mov_b32_e32 v2, s18
@@ -2909,14 +2906,14 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; SDAG-NEXT: v_mov_b32_e32 v1, s9
; SDAG-NEXT: v_mov_b32_e32 v2, s10
; SDAG-NEXT: v_mov_b32_e32 v3, s11
-; SDAG-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[38:39], v[0:3], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_nop 0
; SDAG-NEXT: v_mov_b32_e32 v0, s12
; SDAG-NEXT: v_mov_b32_e32 v1, s13
; SDAG-NEXT: v_mov_b32_e32 v2, s14
; SDAG-NEXT: v_mov_b32_e32 v3, s15
-; SDAG-NEXT: global_store_dwordx4 v[8:9], v[0:3], off sc0 sc1
+; SDAG-NEXT: global_store_dwordx4 v[36:37], v[0:3], off sc0 sc1
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: s_endpgm
;
@@ -2977,47 +2974,47 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; HEURRC-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
; HEURRC-NEXT: v_mov_b64_e32 v[0:1], 48
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], 32
-; HEURRC-NEXT: s_waitcnt lgkmcnt(0)
-; HEURRC-NEXT: v_mov_b32_e32 v4, s24
-; HEURRC-NEXT: v_mov_b32_e32 v5, s25
-; HEURRC-NEXT: v_mov_b32_e32 v6, s26
-; HEURRC-NEXT: v_mov_b32_e32 v7, s27
-; HEURRC-NEXT: v_accvgpr_write_b32 a31, s23
-; HEURRC-NEXT: v_mov_b32_e32 v8, s28
-; HEURRC-NEXT: v_mov_b32_e32 v9, s29
-; HEURRC-NEXT: v_mov_b32_e32 v10, s30
-; HEURRC-NEXT: v_mov_b32_e32 v11, s31
-; HEURRC-NEXT: v_accvgpr_write_b32 a30, s22
-; HEURRC-NEXT: v_accvgpr_write_b32 a29, s21
-; HEURRC-NEXT: v_accvgpr_write_b32 a28, s20
-; HEURRC-NEXT: v_accvgpr_write_b32 a27, s19
-; HEURRC-NEXT: v_accvgpr_write_b32 a26, s18
-; HEURRC-NEXT: v_accvgpr_write_b32 a25, s17
-; HEURRC-NEXT: v_accvgpr_write_b32 a24, s16
-; HEURRC-NEXT: v_accvgpr_write_b32 a23, s15
-; HEURRC-NEXT: v_accvgpr_write_b32 a22, s14
-; HEURRC-NEXT: v_accvgpr_write_b32 a21, s13
-; HEURRC-NEXT: v_accvgpr_write_b32 a20, s12
-; HEURRC-NEXT: v_accvgpr_write_b32 a19, s11
-; HEURRC-NEXT: v_accvgpr_write_b32 a18, s10
-; HEURRC-NEXT: v_accvgpr_write_b32 a17, s9
-; HEURRC-NEXT: v_accvgpr_write_b32 a16, s8
-; HEURRC-NEXT: s_nop 1
-; HEURRC-NEXT: v_mfma_i32_32x32x32_i8 a[0:15], v[4:7], v[8:11], a[16:31]
; HEURRC-NEXT: v_mov_b64_e32 v[4:5], 16
+; HEURRC-NEXT: s_waitcnt lgkmcnt(0)
+; HEURRC-NEXT: v_mov_b32_e32 v8, s24
+; HEURRC-NEXT: v_mov_b32_e...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206135
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