[llvm] [AMDGPU][True16] Lower the threshold of number of joins allowed for large live interval in true16 mode (PR #205256)
Guo Chen via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 09:23:38 PDT 2026
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/205256
>From f540089c6d35278cc38d4922402da831dc6b9a02 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 23 Jun 2026 00:59:14 -0400
Subject: [PATCH 1/2] amdgpu reduce compile-time heristic for true16
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 6 ++++
llvm/lib/CodeGen/RegisterCoalescer.cpp | 32 ++-------------------
llvm/lib/CodeGen/TargetInstrInfo.cpp | 26 +++++++++++++++++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 14 +++++++++
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 +++
5 files changed, 52 insertions(+), 30 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 03f3bf26d0608..1385d2b8983b1 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -43,6 +43,7 @@ namespace llvm {
class DFAPacketizer;
class InstrItineraryData;
+class LiveInterval;
class LiveIntervals;
class LiveVariables;
class MachineCycleInfo;
@@ -208,6 +209,11 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
return false;
}
+ /// Given a LiveInterval, return true if the LI is considered
+ /// high cost for compile time
+ virtual bool isHighCostLiveInterval(
+ LiveInterval &LI, DenseMap<Register, unsigned long> &LIVistCounter) const;
+
protected:
/// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
/// set, this hook lets the target specify whether the instruction is actually
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 4b4ba2144f964..1b890cf4bfdba 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -108,19 +108,6 @@ static cl::opt<unsigned> LateRematUpdateThreshold(
"repeated work. "),
cl::init(100));
-static cl::opt<unsigned> LargeIntervalSizeThreshold(
- "large-interval-size-threshold", cl::Hidden,
- cl::desc("If the valnos size of an interval is larger than the threshold, "
- "it is regarded as a large interval. "),
- cl::init(100));
-
-static cl::opt<unsigned> LargeIntervalFreqThreshold(
- "large-interval-freq-threshold", cl::Hidden,
- cl::desc("For a large interval, if it is coalesced with other live "
- "intervals many times more than the threshold, stop its "
- "coalescing to control the compile time. "),
- cl::init(256));
-
namespace {
class JoinVals;
@@ -248,11 +235,6 @@ class RegisterCoalescer : private LiveRangeEdit::Delegate {
/// Attempt joining two virtual registers. Return true on success.
bool joinVirtRegs(CoalescerPair &CP);
- /// If a live interval has many valnos and is coalesced with other
- /// live intervals many times, we regard such live interval as having
- /// high compile time cost.
- bool isHighCostLiveInterval(LiveInterval &LI);
-
/// Attempt joining with a reserved physreg.
bool joinReservedPhysReg(CoalescerPair &CP);
@@ -3681,17 +3663,6 @@ void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
*LIS->getSlotIndexes(), *TRI, ComposeSubRegIdx);
}
-bool RegisterCoalescer::isHighCostLiveInterval(LiveInterval &LI) {
- if (LI.valnos.size() < LargeIntervalSizeThreshold)
- return false;
- auto &Counter = LargeLIVisitCounter[LI.reg()];
- if (Counter < LargeIntervalFreqThreshold) {
- Counter++;
- return false;
- }
- return true;
-}
-
bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
SmallVector<VNInfo *, 16> NewVNInfo;
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
@@ -3704,7 +3675,8 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n');
- if (isHighCostLiveInterval(LHS) || isHighCostLiveInterval(RHS))
+ if (TII->isHighCostLiveInterval(LHS, LargeLIVisitCounter) ||
+ TII->isHighCostLiveInterval(RHS, LargeLIVisitCounter))
return false;
// First compute NewVNInfo and the simple value mappings.
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index f3666b05464b7..afbe0ecd47730 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -14,6 +14,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -57,6 +58,19 @@ static cl::opt<unsigned int> MaxAccumulatorWidth(
"acc-max-width", cl::Hidden, cl::init(3),
cl::desc("Maximum number of branches in the accumulator tree"));
+static cl::opt<unsigned> LargeIntervalSizeThreshold(
+ "large-interval-size-threshold", cl::Hidden,
+ cl::desc("If the valnos size of an interval is larger than the threshold, "
+ "it is regarded as a large interval. "),
+ cl::init(100));
+
+static cl::opt<unsigned> LargeIntervalFreqThreshold(
+ "large-interval-freq-threshold", cl::Hidden,
+ cl::desc("For a large interval, if it is coalesced with other live "
+ "intervals many times more than the threshold, stop its "
+ "coalescing to control the compile time. "),
+ cl::init(256));
+
TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *TargetInstrInfo::getRegClass(const MCInstrDesc &MCID,
@@ -2232,3 +2246,15 @@ bool TargetInstrInfo::isGlobalMemoryObject(const MachineInstr *MI) const {
return MI->isCall() || MI->hasUnmodeledSideEffects() ||
(MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad());
}
+
+bool TargetInstrInfo::isHighCostLiveInterval(
+ LiveInterval &LI, DenseMap<Register, unsigned long> &LIVistCounter) const {
+ if (LI.valnos.size() < LargeIntervalSizeThreshold)
+ return false;
+ auto &Counter = LIVistCounter[LI.reg()];
+ if (Counter < LargeIntervalFreqThreshold) {
+ Counter++;
+ return false;
+ }
+ return true;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 48953cee43956..bdf2fe0e0b855 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -63,6 +63,12 @@ static cl::opt<bool> Fix16BitCopies(
cl::init(true),
cl::ReallyHidden);
+static cl::opt<unsigned> True16LargeIntervalSizeThreshold(
+ "true16-large-interval-size-threshold", cl::Hidden,
+ cl::desc("If the valnos size of an interval is larger than the threshold, "
+ "it is regarded as a large interval. "),
+ cl::init(100));
+
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
: AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
AMDGPU::ADJCALLSTACKDOWN),
@@ -11538,3 +11544,11 @@ bool SIInstrInfo::isXDL(const MachineInstr &MI) const {
return AMDGPU::getMAIIsGFX940XDL(Opcode);
}
+
+bool SIInstrInfo::isHighCostLiveInterval(
+ LiveInterval &LI, DenseMap<Register, unsigned long> &LIVisitCounter) const {
+ if (ST.useRealTrue16Insts())
+ return LI.valnos.size() >= True16LargeIntervalSizeThreshold;
+
+ return TargetInstrInfo::isHighCostLiveInterval(LI, LIVisitCounter);
+}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1d67c8664ff44..0d7b385dd2837 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -219,6 +219,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineInstr *convertToThreeAddressImpl(MachineInstr &MI,
ThreeAddressUpdates &Updates) const;
+ bool isHighCostLiveInterval(
+ LiveInterval &LI,
+ DenseMap<Register, unsigned long> &LIVistCounter) const override;
+
protected:
/// If the specific machine instruction is a instruction that moves/copies
/// value from one register to another register return destination and source
>From da60aa77e92b759cffd5e0ff3369bc5ffa4ed879 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Fri, 26 Jun 2026 11:00:49 -0400
Subject: [PATCH 2/2] apply new heristic in codegen level
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 6 -
llvm/lib/CodeGen/RegisterCoalescer.cpp | 32 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 26 -
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 14 -
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 -
.../sve-fixed-length-masked-expandloads.ll | 1672 +--
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 12176 ++++++++--------
7 files changed, 6954 insertions(+), 6976 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 1385d2b8983b1..03f3bf26d0608 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -43,7 +43,6 @@ namespace llvm {
class DFAPacketizer;
class InstrItineraryData;
-class LiveInterval;
class LiveIntervals;
class LiveVariables;
class MachineCycleInfo;
@@ -209,11 +208,6 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
return false;
}
- /// Given a LiveInterval, return true if the LI is considered
- /// high cost for compile time
- virtual bool isHighCostLiveInterval(
- LiveInterval &LI, DenseMap<Register, unsigned long> &LIVistCounter) const;
-
protected:
/// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
/// set, this hook lets the target specify whether the instruction is actually
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 1b890cf4bfdba..4cd8201fbca9e 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -108,6 +108,19 @@ static cl::opt<unsigned> LateRematUpdateThreshold(
"repeated work. "),
cl::init(100));
+static cl::opt<unsigned> LargeIntervalSizeThreshold(
+ "large-interval-size-threshold", cl::Hidden,
+ cl::desc("If the valnos size of an interval is larger than the threshold, "
+ "it is regarded as a large interval. "),
+ cl::init(100));
+
+static cl::opt<unsigned> LargeIntervalFreqThreshold(
+ "large-interval-freq-threshold", cl::Hidden,
+ cl::desc("For a large interval, if it is coalesced with other live "
+ "intervals many times more than the threshold, stop its "
+ "coalescing to control the compile time. "),
+ cl::init(16));
+
namespace {
class JoinVals;
@@ -235,6 +248,11 @@ class RegisterCoalescer : private LiveRangeEdit::Delegate {
/// Attempt joining two virtual registers. Return true on success.
bool joinVirtRegs(CoalescerPair &CP);
+ /// If a live interval has many valnos and is coalesced with other
+ /// live intervals many times, we regard such live interval as having
+ /// high compile time cost.
+ bool isHighCostLiveInterval(LiveInterval &LI);
+
/// Attempt joining with a reserved physreg.
bool joinReservedPhysReg(CoalescerPair &CP);
@@ -3663,6 +3681,17 @@ void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
*LIS->getSlotIndexes(), *TRI, ComposeSubRegIdx);
}
+bool RegisterCoalescer::isHighCostLiveInterval(LiveInterval &LI) {
+ if (LI.valnos.size() < LargeIntervalSizeThreshold)
+ return false;
+ auto &Counter = LargeLIVisitCounter[LI.reg()];
+ if (Counter < LargeIntervalFreqThreshold) {
+ Counter++;
+ return false;
+ }
+ return true;
+}
+
bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
SmallVector<VNInfo *, 16> NewVNInfo;
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
@@ -3675,8 +3704,7 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n');
- if (TII->isHighCostLiveInterval(LHS, LargeLIVisitCounter) ||
- TII->isHighCostLiveInterval(RHS, LargeLIVisitCounter))
+ if (isHighCostLiveInterval(LHS) || isHighCostLiveInterval(RHS))
return false;
// First compute NewVNInfo and the simple value mappings.
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index afbe0ecd47730..f3666b05464b7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -14,7 +14,6 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/BinaryFormat/Dwarf.h"
-#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -58,19 +57,6 @@ static cl::opt<unsigned int> MaxAccumulatorWidth(
"acc-max-width", cl::Hidden, cl::init(3),
cl::desc("Maximum number of branches in the accumulator tree"));
-static cl::opt<unsigned> LargeIntervalSizeThreshold(
- "large-interval-size-threshold", cl::Hidden,
- cl::desc("If the valnos size of an interval is larger than the threshold, "
- "it is regarded as a large interval. "),
- cl::init(100));
-
-static cl::opt<unsigned> LargeIntervalFreqThreshold(
- "large-interval-freq-threshold", cl::Hidden,
- cl::desc("For a large interval, if it is coalesced with other live "
- "intervals many times more than the threshold, stop its "
- "coalescing to control the compile time. "),
- cl::init(256));
-
TargetInstrInfo::~TargetInstrInfo() = default;
const TargetRegisterClass *TargetInstrInfo::getRegClass(const MCInstrDesc &MCID,
@@ -2246,15 +2232,3 @@ bool TargetInstrInfo::isGlobalMemoryObject(const MachineInstr *MI) const {
return MI->isCall() || MI->hasUnmodeledSideEffects() ||
(MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad());
}
-
-bool TargetInstrInfo::isHighCostLiveInterval(
- LiveInterval &LI, DenseMap<Register, unsigned long> &LIVistCounter) const {
- if (LI.valnos.size() < LargeIntervalSizeThreshold)
- return false;
- auto &Counter = LIVistCounter[LI.reg()];
- if (Counter < LargeIntervalFreqThreshold) {
- Counter++;
- return false;
- }
- return true;
-}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bdf2fe0e0b855..48953cee43956 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -63,12 +63,6 @@ static cl::opt<bool> Fix16BitCopies(
cl::init(true),
cl::ReallyHidden);
-static cl::opt<unsigned> True16LargeIntervalSizeThreshold(
- "true16-large-interval-size-threshold", cl::Hidden,
- cl::desc("If the valnos size of an interval is larger than the threshold, "
- "it is regarded as a large interval. "),
- cl::init(100));
-
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
: AMDGPUGenInstrInfo(ST, RI, AMDGPU::ADJCALLSTACKUP,
AMDGPU::ADJCALLSTACKDOWN),
@@ -11544,11 +11538,3 @@ bool SIInstrInfo::isXDL(const MachineInstr &MI) const {
return AMDGPU::getMAIIsGFX940XDL(Opcode);
}
-
-bool SIInstrInfo::isHighCostLiveInterval(
- LiveInterval &LI, DenseMap<Register, unsigned long> &LIVisitCounter) const {
- if (ST.useRealTrue16Insts())
- return LI.valnos.size() >= True16LargeIntervalSizeThreshold;
-
- return TargetInstrInfo::isHighCostLiveInterval(LI, LIVisitCounter);
-}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 0d7b385dd2837..1d67c8664ff44 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -219,10 +219,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineInstr *convertToThreeAddressImpl(MachineInstr &MI,
ThreeAddressUpdates &Updates) const;
- bool isHighCostLiveInterval(
- LiveInterval &LI,
- DenseMap<Register, unsigned long> &LIVistCounter) const override;
-
protected:
/// If the specific machine instruction is a instruction that moves/copies
/// value from one register to another register return destination and source
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
index f2ddac3e9fac7..729c9b3db8e69 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
@@ -15809,34 +15809,34 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: ptrue p1.b, vl128
; CHECK-NEXT: ld1b { z0.b }, p1/z, [x1]
; CHECK-NEXT: cmpeq p0.b, p1/z, z0.b, #0
-; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: umov w9, v1.b[1]
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov z0.b, z1.b[18]
-; CHECK-NEXT: umov w10, v1.b[7]
-; CHECK-NEXT: umov w11, v1.b[8]
-; CHECK-NEXT: mov z2.b, z1.b[19]
-; CHECK-NEXT: umov w12, v1.b[2]
-; CHECK-NEXT: umov w14, v1.b[9]
-; CHECK-NEXT: umov w13, v1.b[3]
+; CHECK-NEXT: umov w9, v0.b[1]
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov z1.b, z0.b[18]
+; CHECK-NEXT: umov w10, v0.b[7]
+; CHECK-NEXT: umov w11, v0.b[8]
+; CHECK-NEXT: mov z2.b, z0.b[19]
+; CHECK-NEXT: umov w12, v0.b[2]
+; CHECK-NEXT: umov w14, v0.b[9]
+; CHECK-NEXT: umov w13, v0.b[3]
; CHECK-NEXT: and x8, x8, #0x1
-; CHECK-NEXT: fmov w16, s0
-; CHECK-NEXT: mov z0.b, z1.b[20]
+; CHECK-NEXT: fmov w16, s1
+; CHECK-NEXT: mov z1.b, z0.b[20]
; CHECK-NEXT: bfi x8, x9, #1, #1
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: umov w15, v1.b[10]
+; CHECK-NEXT: umov w15, v0.b[10]
; CHECK-NEXT: ubfiz x10, x10, #7, #1
; CHECK-NEXT: ubfiz x11, x11, #8, #1
-; CHECK-NEXT: mov z2.b, z1.b[21]
+; CHECK-NEXT: mov z2.b, z0.b[21]
; CHECK-NEXT: bfi x8, x12, #2, #1
-; CHECK-NEXT: fmov w12, s0
+; CHECK-NEXT: fmov w12, s1
; CHECK-NEXT: ubfiz x16, x16, #18, #1
; CHECK-NEXT: ubfiz x9, x9, #19, #1
; CHECK-NEXT: ubfiz x14, x14, #9, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: umov w11, v1.b[11]
-; CHECK-NEXT: mov z0.b, z1.b[22]
+; CHECK-NEXT: umov w11, v0.b[11]
+; CHECK-NEXT: mov z1.b, z0.b[22]
; CHECK-NEXT: ubfiz x15, x15, #10, #1
; CHECK-NEXT: ubfiz x12, x12, #20, #1
; CHECK-NEXT: orr x9, x16, x9
@@ -15845,195 +15845,195 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: bfi x8, x13, #3, #1
; CHECK-NEXT: orr x10, x10, x15
; CHECK-NEXT: orr x9, x9, x12
-; CHECK-NEXT: umov w12, v1.b[12]
-; CHECK-NEXT: fmov w13, s0
+; CHECK-NEXT: umov w12, v0.b[12]
+; CHECK-NEXT: fmov w13, s1
; CHECK-NEXT: ubfiz x11, x11, #11, #1
-; CHECK-NEXT: umov w15, v1.b[13]
-; CHECK-NEXT: mov z0.b, z1.b[16]
+; CHECK-NEXT: umov w15, v0.b[13]
+; CHECK-NEXT: mov z1.b, z0.b[16]
; CHECK-NEXT: ubfiz x14, x14, #21, #1
-; CHECK-NEXT: mov z2.b, z1.b[17]
-; CHECK-NEXT: umov w16, v1.b[4]
+; CHECK-NEXT: mov z2.b, z0.b[17]
+; CHECK-NEXT: umov w16, v0.b[4]
; CHECK-NEXT: ubfiz x13, x13, #22, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: umov w11, v1.b[14]
+; CHECK-NEXT: umov w11, v0.b[14]
; CHECK-NEXT: orr x9, x9, x14
; CHECK-NEXT: ubfiz x12, x12, #12, #1
-; CHECK-NEXT: umov w14, v1.b[5]
+; CHECK-NEXT: umov w14, v0.b[5]
; CHECK-NEXT: orr x9, x9, x13
-; CHECK-NEXT: umov w13, v1.b[15]
+; CHECK-NEXT: umov w13, v0.b[15]
; CHECK-NEXT: ubfiz x15, x15, #13, #1
; CHECK-NEXT: orr x10, x10, x12
-; CHECK-NEXT: fmov w12, s0
-; CHECK-NEXT: mov z0.b, z1.b[23]
+; CHECK-NEXT: fmov w12, s1
+; CHECK-NEXT: mov z1.b, z0.b[23]
; CHECK-NEXT: ubfiz x11, x11, #14, #1
; CHECK-NEXT: orr x10, x10, x15
; CHECK-NEXT: fmov w15, s2
-; CHECK-NEXT: mov z2.b, z1.b[24]
+; CHECK-NEXT: mov z2.b, z0.b[24]
; CHECK-NEXT: bfi x8, x16, #4, #1
-; CHECK-NEXT: umov w16, v1.b[6]
+; CHECK-NEXT: umov w16, v0.b[6]
; CHECK-NEXT: ubfiz x13, x13, #15, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: fmov w11, s0
-; CHECK-NEXT: mov z0.b, z1.b[25]
+; CHECK-NEXT: fmov w11, s1
+; CHECK-NEXT: mov z1.b, z0.b[25]
; CHECK-NEXT: ubfiz x12, x12, #16, #1
; CHECK-NEXT: bfi x8, x14, #5, #1
; CHECK-NEXT: orr x10, x10, x13
; CHECK-NEXT: fmov w13, s2
-; CHECK-NEXT: mov z2.b, z1.b[26]
+; CHECK-NEXT: mov z2.b, z0.b[26]
; CHECK-NEXT: ubfiz x11, x11, #23, #1
; CHECK-NEXT: orr x10, x10, x12
; CHECK-NEXT: ubfiz x14, x15, #17, #1
-; CHECK-NEXT: fmov w12, s0
-; CHECK-NEXT: mov z0.b, z1.b[27]
+; CHECK-NEXT: fmov w12, s1
+; CHECK-NEXT: mov z1.b, z0.b[27]
; CHECK-NEXT: bfi x8, x16, #6, #1
; CHECK-NEXT: ubfiz x13, x13, #24, #1
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: fmov w11, s2
-; CHECK-NEXT: mov z2.b, z1.b[28]
+; CHECK-NEXT: mov z2.b, z0.b[28]
; CHECK-NEXT: orr x10, x10, x14
; CHECK-NEXT: orr x9, x9, x13
; CHECK-NEXT: ubfiz x12, x12, #25, #1
-; CHECK-NEXT: fmov w13, s0
-; CHECK-NEXT: mov z0.b, z1.b[29]
+; CHECK-NEXT: fmov w13, s1
+; CHECK-NEXT: mov z1.b, z0.b[29]
; CHECK-NEXT: ubfiz x11, x11, #26, #1
; CHECK-NEXT: orr x8, x8, x10
; CHECK-NEXT: orr x9, x9, x12
; CHECK-NEXT: fmov w12, s2
-; CHECK-NEXT: mov z2.b, z1.b[30]
+; CHECK-NEXT: mov z2.b, z0.b[30]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x11, x13, #27, #1
-; CHECK-NEXT: fmov w13, s0
-; CHECK-NEXT: mov z0.b, z1.b[31]
+; CHECK-NEXT: fmov w13, s1
+; CHECK-NEXT: mov z1.b, z0.b[31]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x12, x12, #28, #1
; CHECK-NEXT: ubfiz x11, x13, #29, #1
; CHECK-NEXT: fmov w13, s2
; CHECK-NEXT: orr x9, x9, x12
-; CHECK-NEXT: mov z2.b, z1.b[32]
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov z0.b, z1.b[33]
+; CHECK-NEXT: mov z2.b, z0.b[32]
+; CHECK-NEXT: fmov w10, s1
+; CHECK-NEXT: mov z1.b, z0.b[33]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x12, x13, #30, #1
; CHECK-NEXT: lsl w10, w10, #31
; CHECK-NEXT: orr x9, x9, x12
; CHECK-NEXT: orr x8, x8, x9
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[34]
+; CHECK-NEXT: mov z2.b, z0.b[34]
; CHECK-NEXT: orr x8, x8, x10
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #32
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[35]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[35]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #33
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[36]
+; CHECK-NEXT: mov z2.b, z0.b[36]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #34
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[37]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[37]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #35
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[38]
+; CHECK-NEXT: mov z2.b, z0.b[38]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #36
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[39]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[39]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #37
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[40]
+; CHECK-NEXT: mov z2.b, z0.b[40]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #38
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[41]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[41]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #39
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[42]
+; CHECK-NEXT: mov z2.b, z0.b[42]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #40
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[43]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[43]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #41
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[44]
+; CHECK-NEXT: mov z2.b, z0.b[44]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #42
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[45]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[45]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #43
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[46]
+; CHECK-NEXT: mov z2.b, z0.b[46]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #44
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[47]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[47]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #45
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[48]
+; CHECK-NEXT: mov z2.b, z0.b[48]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #46
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[49]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[49]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #47
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[50]
+; CHECK-NEXT: mov z2.b, z0.b[50]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #48
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[51]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[51]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #49
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[52]
+; CHECK-NEXT: mov z2.b, z0.b[52]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #50
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[53]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[53]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #51
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[54]
+; CHECK-NEXT: mov z2.b, z0.b[54]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #52
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[55]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[55]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #53
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[56]
+; CHECK-NEXT: mov z2.b, z0.b[56]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #54
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[57]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[57]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #55
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[58]
+; CHECK-NEXT: mov z2.b, z0.b[58]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #56
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[59]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[59]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #57
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[60]
+; CHECK-NEXT: mov z2.b, z0.b[60]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #58
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[61]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[61]
; CHECK-NEXT: and w9, w9, #0x1
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov z0.b, z1.b[63]
+; CHECK-NEXT: fmov w10, s1
+; CHECK-NEXT: mov z1.b, z0.b[63]
; CHECK-NEXT: orr x8, x8, x9, lsl #59
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[62]
+; CHECK-NEXT: mov z2.b, z0.b[62]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #60
; CHECK-NEXT: and w9, w10, #0x1
@@ -16041,18 +16041,18 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #62
-; CHECK-NEXT: fmov w9, s0
+; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: orr x8, x8, x9, lsl #63
; CHECK-NEXT: tbz w8, #0, .LBB37_2
; CHECK-NEXT: // %bb.1: // %cond.load
-; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1rb { z1.b }, p0/z, [x0]
; CHECK-NEXT: add x0, x0, #1
; CHECK-NEXT: tbnz w8, #1, .LBB37_3
; CHECK-NEXT: b .LBB37_4
; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: adrp x9, .LCPI37_0
; CHECK-NEXT: add x9, x9, :lo12:.LCPI37_0
-; CHECK-NEXT: ld1b { z0.b }, p1/z, [x9]
+; CHECK-NEXT: ld1b { z1.b }, p1/z, [x9]
; CHECK-NEXT: tbz w8, #1, .LBB37_4
; CHECK-NEXT: .LBB37_3: // %cond.load1
; CHECK-NEXT: mov w9, #1 // =0x1
@@ -16060,7 +16060,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: .LBB37_4: // %else2
; CHECK-NEXT: tbnz w8, #2, .LBB37_181
; CHECK-NEXT: // %bb.5: // %else6
@@ -16089,7 +16089,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: .LBB37_16: // %else46
; CHECK-NEXT: mov w12, #71 // =0x47
; CHECK-NEXT: mov w14, #72 // =0x48
@@ -16102,7 +16102,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w11
+; CHECK-NEXT: mov z1.b, p1/m, w11
; CHECK-NEXT: .LBB37_18: // %else50
; CHECK-NEXT: mov w11, #73 // =0x49
; CHECK-NEXT: mov w13, #85 // =0x55
@@ -16113,7 +16113,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w15
; CHECK-NEXT: ldrb w15, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w15
+; CHECK-NEXT: mov z1.b, p1/m, w15
; CHECK-NEXT: .LBB37_20: // %else54
; CHECK-NEXT: whilels p3.b, xzr, x12
; CHECK-NEXT: whilels p4.b, xzr, x14
@@ -16128,14 +16128,14 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p5.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p5/m, w10
+; CHECK-NEXT: mov z1.b, p5/m, w10
; CHECK-NEXT: .LBB37_22: // %else58
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: mov w1, #75 // =0x4b
; CHECK-NEXT: mov w17, #87 // =0x57
-; CHECK-NEXT: lastb w12, p4, z1.b
-; CHECK-NEXT: lastb w15, p1, z1.b
-; CHECK-NEXT: lastb w16, p2, z1.b
+; CHECK-NEXT: lastb w12, p4, z0.b
+; CHECK-NEXT: lastb w15, p1, z0.b
+; CHECK-NEXT: lastb w16, p2, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x11
; CHECK-NEXT: whilels p1.b, xzr, x13
; CHECK-NEXT: tbz w8, #16, .LBB37_24
@@ -16145,12 +16145,12 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w11
+; CHECK-NEXT: mov z1.b, p3/m, w11
; CHECK-NEXT: .LBB37_24: // %else62
-; CHECK-NEXT: lastb w11, p2, z1.b
+; CHECK-NEXT: lastb w11, p2, z0.b
; CHECK-NEXT: mov w3, #76 // =0x4c
; CHECK-NEXT: mov w18, #88 // =0x58
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x9
; CHECK-NEXT: whilels p1.b, xzr, x14
; CHECK-NEXT: tbz w8, #17, .LBB37_26
@@ -16160,15 +16160,15 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w9
+; CHECK-NEXT: mov z1.b, p3/m, w9
; CHECK-NEXT: .LBB37_26: // %else66
-; CHECK-NEXT: lastb w9, p2, z1.b
+; CHECK-NEXT: lastb w9, p2, z0.b
; CHECK-NEXT: ubfiz x5, x10, #7, #1
; CHECK-NEXT: ubfiz x7, x12, #8, #1
; CHECK-NEXT: ubfiz x4, x15, #19, #1
; CHECK-NEXT: ubfiz x6, x16, #20, #1
; CHECK-NEXT: mov w15, #89 // =0x59
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x1
; CHECK-NEXT: mov w1, #77 // =0x4d
; CHECK-NEXT: whilels p1.b, xzr, x17
@@ -16180,7 +16180,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w10
+; CHECK-NEXT: mov z1.b, p3/m, w10
; CHECK-NEXT: .LBB37_28: // %else70
; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp x24, x23, [sp, #16] // 16-byte Folded Spill
@@ -16193,13 +16193,13 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w23, -40
; CHECK-NEXT: .cfi_offset w24, -48
-; CHECK-NEXT: lastb w10, p2, z1.b
+; CHECK-NEXT: lastb w10, p2, z0.b
; CHECK-NEXT: orr x7, x5, x7
; CHECK-NEXT: ubfiz x5, x13, #21, #1
; CHECK-NEXT: mov w16, #65 // =0x41
; CHECK-NEXT: orr x19, x4, x6
; CHECK-NEXT: mov w4, #90 // =0x5a
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x3
; CHECK-NEXT: ubfiz x3, x11, #9, #1
; CHECK-NEXT: whilels p1.b, xzr, x18
@@ -16211,15 +16211,15 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w11
+; CHECK-NEXT: mov z1.b, p3/m, w11
; CHECK-NEXT: .LBB37_30: // %else74
-; CHECK-NEXT: lastb w11, p2, z1.b
+; CHECK-NEXT: lastb w11, p2, z0.b
; CHECK-NEXT: ubfiz x21, x9, #10, #1
; CHECK-NEXT: ubfiz x6, x14, #22, #1
; CHECK-NEXT: orr x7, x7, x3
; CHECK-NEXT: mov w3, #79 // =0x4f
; CHECK-NEXT: orr x20, x19, x5
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: mov w5, #91 // =0x5b
; CHECK-NEXT: whilels p3.b, xzr, x17
; CHECK-NEXT: mov w17, #66 // =0x42
@@ -16232,17 +16232,17 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w9
+; CHECK-NEXT: mov z1.b, p4/m, w9
; CHECK-NEXT: .LBB37_32: // %else78
-; CHECK-NEXT: lastb w9, p3, z1.b
+; CHECK-NEXT: lastb w9, p3, z0.b
; CHECK-NEXT: orr x19, x7, x21
; CHECK-NEXT: ubfiz x21, x10, #11, #1
; CHECK-NEXT: ubfiz x7, x12, #23, #1
; CHECK-NEXT: mov w1, #67 // =0x43
; CHECK-NEXT: orr x22, x20, x6
-; CHECK-NEXT: lastb w14, p2, z1.b
+; CHECK-NEXT: lastb w14, p2, z0.b
; CHECK-NEXT: mov w6, #92 // =0x5c
-; CHECK-NEXT: lastb w15, p1, z1.b
+; CHECK-NEXT: lastb w15, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x16
; CHECK-NEXT: whilels p2.b, xzr, x18
; CHECK-NEXT: whilels p1.b, xzr, x4
@@ -16254,17 +16254,17 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w10
+; CHECK-NEXT: mov z1.b, p4/m, w10
; CHECK-NEXT: .LBB37_34: // %else82
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: orr x20, x19, x21
; CHECK-NEXT: ubfiz x21, x11, #12, #1
; CHECK-NEXT: ubfiz x19, x13, #24, #1
; CHECK-NEXT: mov w18, #68 // =0x44
; CHECK-NEXT: orr x23, x22, x7
-; CHECK-NEXT: lastb w12, p2, z1.b
+; CHECK-NEXT: lastb w12, p2, z0.b
; CHECK-NEXT: mov w7, #93 // =0x5d
-; CHECK-NEXT: lastb w16, p1, z1.b
+; CHECK-NEXT: lastb w16, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x17
; CHECK-NEXT: whilels p2.b, xzr, x3
; CHECK-NEXT: whilels p1.b, xzr, x5
@@ -16276,18 +16276,18 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w11
+; CHECK-NEXT: mov z1.b, p4/m, w11
; CHECK-NEXT: .LBB37_36: // %else86
-; CHECK-NEXT: lastb w11, p3, z1.b
+; CHECK-NEXT: lastb w11, p3, z0.b
; CHECK-NEXT: orr x20, x20, x21
; CHECK-NEXT: ubfiz x21, x14, #13, #1
; CHECK-NEXT: ubfiz x22, x15, #25, #1
; CHECK-NEXT: and x9, x9, #0x1
; CHECK-NEXT: mov w3, #69 // =0x45
-; CHECK-NEXT: lastb w13, p2, z1.b
+; CHECK-NEXT: lastb w13, p2, z0.b
; CHECK-NEXT: orr x24, x23, x19
; CHECK-NEXT: mov w19, #94 // =0x5e
-; CHECK-NEXT: lastb w17, p1, z1.b
+; CHECK-NEXT: lastb w17, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x1
; CHECK-NEXT: whilels p2.b, xzr, x4
; CHECK-NEXT: mov w4, #82 // =0x52
@@ -16300,13 +16300,13 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w14
+; CHECK-NEXT: mov z1.b, p4/m, w14
; CHECK-NEXT: .LBB37_38: // %else90
-; CHECK-NEXT: lastb w14, p3, z1.b
+; CHECK-NEXT: lastb w14, p3, z0.b
; CHECK-NEXT: bfi x9, x10, #1, #1
; CHECK-NEXT: ubfiz x23, x16, #26, #1
-; CHECK-NEXT: lastb w15, p2, z1.b
-; CHECK-NEXT: lastb w1, p1, z1.b
+; CHECK-NEXT: lastb w15, p2, z0.b
+; CHECK-NEXT: lastb w1, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x18
; CHECK-NEXT: whilels p2.b, xzr, x5
; CHECK-NEXT: ubfiz x5, x12, #14, #1
@@ -16321,13 +16321,13 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w10
+; CHECK-NEXT: mov z1.b, p4/m, w10
; CHECK-NEXT: .LBB37_40: // %else94
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: bfi x9, x11, #2, #1
; CHECK-NEXT: orr x5, x7, x5
-; CHECK-NEXT: lastb w16, p2, z1.b
-; CHECK-NEXT: lastb w18, p1, z1.b
+; CHECK-NEXT: lastb w16, p2, z0.b
+; CHECK-NEXT: lastb w18, p1, z0.b
; CHECK-NEXT: whilels p4.b, xzr, x3
; CHECK-NEXT: ubfiz x3, x13, #15, #1
; CHECK-NEXT: whilels p2.b, xzr, x4
@@ -16342,18 +16342,18 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p5.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p5/m, w11
+; CHECK-NEXT: mov z1.b, p5/m, w11
; CHECK-NEXT: .LBB37_42: // %else98
-; CHECK-NEXT: lastb w11, p4, z1.b
+; CHECK-NEXT: lastb w11, p4, z0.b
; CHECK-NEXT: bfi x9, x14, #3, #1
; CHECK-NEXT: ubfiz x15, x15, #16, #1
; CHECK-NEXT: ubfiz x1, x1, #28, #1
; CHECK-NEXT: orr x3, x5, x3
; CHECK-NEXT: orr x4, x6, x4
-; CHECK-NEXT: lastb w13, p2, z1.b
+; CHECK-NEXT: lastb w13, p2, z0.b
; CHECK-NEXT: mov w14, #96 // =0x60
-; CHECK-NEXT: lastb w17, p1, z1.b
-; CHECK-NEXT: lastb w7, p3, z1.b
+; CHECK-NEXT: lastb w17, p1, z0.b
+; CHECK-NEXT: lastb w7, p3, z0.b
; CHECK-NEXT: whilels p1.b, xzr, x12
; CHECK-NEXT: tbz w8, #26, .LBB37_44
; CHECK-NEXT: // %bb.43: // %cond.load101
@@ -16362,9 +16362,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w12
+; CHECK-NEXT: mov z1.b, p2/m, w12
; CHECK-NEXT: .LBB37_44: // %else102
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: bfi x9, x10, #4, #1
; CHECK-NEXT: ubfiz x16, x16, #17, #1
; CHECK-NEXT: ubfiz x18, x18, #29, #1
@@ -16379,7 +16379,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w4
; CHECK-NEXT: ldrb w4, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w4
+; CHECK-NEXT: mov z1.b, p1/m, w4
; CHECK-NEXT: .LBB37_46: // %else106
; CHECK-NEXT: bfi x9, x11, #5, #1
; CHECK-NEXT: ubfiz x13, x13, #18, #1
@@ -16395,9 +16395,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_48: // %else110
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: bfi x9, x12, #6, #1
; CHECK-NEXT: mov w12, #99 // =0x63
; CHECK-NEXT: whilels p1.b, xzr, x15
@@ -16410,9 +16410,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_50: // %else114
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x9, x15
; CHECK-NEXT: orr x10, x16, x10
; CHECK-NEXT: and w9, w14, #0x1
@@ -16425,9 +16425,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_52: // %else118
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16439,9 +16439,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_54: // %else122
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #32
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16453,9 +16453,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_56: // %else126
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #33
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16467,9 +16467,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_58: // %else130
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #34
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16481,9 +16481,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_60: // %else134
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #35
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16495,9 +16495,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_62: // %else138
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #36
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16509,9 +16509,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_64: // %else142
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #37
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16523,9 +16523,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_66: // %else146
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #38
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16537,9 +16537,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_68: // %else150
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #39
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16551,9 +16551,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_70: // %else154
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #40
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16565,9 +16565,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_72: // %else158
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #41
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16579,9 +16579,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_74: // %else162
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #42
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16593,9 +16593,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_76: // %else166
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #43
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16607,9 +16607,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_78: // %else170
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #44
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16621,9 +16621,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_80: // %else174
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #45
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16635,9 +16635,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_82: // %else178
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #46
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16649,9 +16649,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_84: // %else182
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #47
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16663,9 +16663,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_86: // %else186
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #48
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16677,9 +16677,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_88: // %else190
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #49
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16691,9 +16691,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_90: // %else194
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #50
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16705,9 +16705,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_92: // %else198
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #51
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16719,9 +16719,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_94: // %else202
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #52
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16733,9 +16733,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_96: // %else206
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #53
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16747,9 +16747,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_98: // %else210
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #54
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16761,9 +16761,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_100: // %else214
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #55
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16775,9 +16775,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB37_102: // %else218
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #56
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16789,9 +16789,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_104: // %else222
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #57
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -16802,9 +16802,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w12
+; CHECK-NEXT: mov z1.b, p2/m, w12
; CHECK-NEXT: .LBB37_106: // %else226
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: orr x13, x15, x9, lsl #58
; CHECK-NEXT: mov w9, #127 // =0x7f
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -16816,9 +16816,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB37_108: // %else230
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x13, x13, x10, lsl #59
; CHECK-NEXT: and w10, w12, #0x1
; CHECK-NEXT: tbz x8, #59, .LBB37_110
@@ -16828,7 +16828,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w12
+; CHECK-NEXT: mov z1.b, p1/m, w12
; CHECK-NEXT: .LBB37_110: // %else234
; CHECK-NEXT: orr x12, x13, x11, lsl #60
; CHECK-NEXT: whilels p1.b, xzr, x9
@@ -16840,9 +16840,9 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w11
+; CHECK-NEXT: mov z1.b, p2/m, w11
; CHECK-NEXT: .LBB37_112: // %else238
-; CHECK-NEXT: lastb w11, p1, z1.b
+; CHECK-NEXT: lastb w11, p1, z0.b
; CHECK-NEXT: orr x10, x12, x10, lsl #61
; CHECK-NEXT: tbnz x8, #61, .LBB37_191
; CHECK-NEXT: // %bb.113: // %else242
@@ -16981,13 +16981,13 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: tbz x9, #63, .LBB37_180
; CHECK-NEXT: .LBB37_179: // %cond.load505
; CHECK-NEXT: mov w8, #127 // =0x7f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: .LBB37_180: // %else506
-; CHECK-NEXT: sunpklo z0.h, z0.b
+; CHECK-NEXT: sunpklo z0.h, z1.b
; CHECK-NEXT: ptrue p0.h, vl128
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #32] // 16-byte Folded Reload
@@ -17001,7 +17001,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #3, .LBB37_6
; CHECK-NEXT: .LBB37_182: // %cond.load9
; CHECK-NEXT: mov w9, #3 // =0x3
@@ -17009,7 +17009,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #4, .LBB37_7
; CHECK-NEXT: .LBB37_183: // %cond.load13
; CHECK-NEXT: mov w9, #4 // =0x4
@@ -17017,7 +17017,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #5, .LBB37_8
; CHECK-NEXT: .LBB37_184: // %cond.load17
; CHECK-NEXT: mov w9, #5 // =0x5
@@ -17025,7 +17025,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #6, .LBB37_9
; CHECK-NEXT: .LBB37_185: // %cond.load21
; CHECK-NEXT: mov w9, #6 // =0x6
@@ -17033,7 +17033,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #7, .LBB37_10
; CHECK-NEXT: .LBB37_186: // %cond.load25
; CHECK-NEXT: mov w9, #7 // =0x7
@@ -17041,7 +17041,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #8, .LBB37_11
; CHECK-NEXT: .LBB37_187: // %cond.load29
; CHECK-NEXT: mov w9, #8 // =0x8
@@ -17049,7 +17049,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #9, .LBB37_12
; CHECK-NEXT: .LBB37_188: // %cond.load33
; CHECK-NEXT: mov w9, #9 // =0x9
@@ -17057,7 +17057,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #10, .LBB37_13
; CHECK-NEXT: .LBB37_189: // %cond.load37
; CHECK-NEXT: mov w9, #10 // =0xa
@@ -17065,7 +17065,7 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #11, .LBB37_14
; CHECK-NEXT: .LBB37_190: // %cond.load41
; CHECK-NEXT: mov w9, #11 // =0xb
@@ -17073,538 +17073,538 @@ define void @masked_load_sext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbnz w8, #12, .LBB37_15
; CHECK-NEXT: b .LBB37_16
; CHECK-NEXT: .LBB37_191: // %cond.load241
; CHECK-NEXT: mov w12, #61 // =0x3d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w12
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w12
; CHECK-NEXT: orr x9, x10, x9, lsl #62
; CHECK-NEXT: tbz x8, #62, .LBB37_114
; CHECK-NEXT: .LBB37_192: // %cond.load245
; CHECK-NEXT: mov w10, #62 // =0x3e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w10
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w10
; CHECK-NEXT: orr x9, x9, x11, lsl #63
; CHECK-NEXT: tbz x8, #63, .LBB37_115
; CHECK-NEXT: .LBB37_193: // %cond.load249
; CHECK-NEXT: mov w8, #63 // =0x3f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #0, .LBB37_116
; CHECK-NEXT: .LBB37_194: // %cond.load253
; CHECK-NEXT: mov w8, #64 // =0x40
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #1, .LBB37_117
; CHECK-NEXT: .LBB37_195: // %cond.load257
; CHECK-NEXT: mov w8, #65 // =0x41
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #2, .LBB37_118
; CHECK-NEXT: .LBB37_196: // %cond.load261
; CHECK-NEXT: mov w8, #66 // =0x42
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #3, .LBB37_119
; CHECK-NEXT: .LBB37_197: // %cond.load265
; CHECK-NEXT: mov w8, #67 // =0x43
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #4, .LBB37_120
; CHECK-NEXT: .LBB37_198: // %cond.load269
; CHECK-NEXT: mov w8, #68 // =0x44
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #5, .LBB37_121
; CHECK-NEXT: .LBB37_199: // %cond.load273
; CHECK-NEXT: mov w8, #69 // =0x45
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #6, .LBB37_122
; CHECK-NEXT: .LBB37_200: // %cond.load277
; CHECK-NEXT: mov w8, #70 // =0x46
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #7, .LBB37_123
; CHECK-NEXT: .LBB37_201: // %cond.load281
; CHECK-NEXT: mov w8, #71 // =0x47
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #8, .LBB37_124
; CHECK-NEXT: .LBB37_202: // %cond.load285
; CHECK-NEXT: mov w8, #72 // =0x48
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #9, .LBB37_125
; CHECK-NEXT: .LBB37_203: // %cond.load289
; CHECK-NEXT: mov w8, #73 // =0x49
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #10, .LBB37_126
; CHECK-NEXT: .LBB37_204: // %cond.load293
; CHECK-NEXT: mov w8, #74 // =0x4a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #11, .LBB37_127
; CHECK-NEXT: .LBB37_205: // %cond.load297
; CHECK-NEXT: mov w8, #75 // =0x4b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #12, .LBB37_128
; CHECK-NEXT: .LBB37_206: // %cond.load301
; CHECK-NEXT: mov w8, #76 // =0x4c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #13, .LBB37_129
; CHECK-NEXT: .LBB37_207: // %cond.load305
; CHECK-NEXT: mov w8, #77 // =0x4d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #14, .LBB37_130
; CHECK-NEXT: .LBB37_208: // %cond.load309
; CHECK-NEXT: mov w8, #78 // =0x4e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #15, .LBB37_131
; CHECK-NEXT: .LBB37_209: // %cond.load313
; CHECK-NEXT: mov w8, #79 // =0x4f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #16, .LBB37_132
; CHECK-NEXT: .LBB37_210: // %cond.load317
; CHECK-NEXT: mov w8, #80 // =0x50
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #17, .LBB37_133
; CHECK-NEXT: .LBB37_211: // %cond.load321
; CHECK-NEXT: mov w8, #81 // =0x51
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #18, .LBB37_134
; CHECK-NEXT: .LBB37_212: // %cond.load325
; CHECK-NEXT: mov w8, #82 // =0x52
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #19, .LBB37_135
; CHECK-NEXT: .LBB37_213: // %cond.load329
; CHECK-NEXT: mov w8, #83 // =0x53
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #20, .LBB37_136
; CHECK-NEXT: .LBB37_214: // %cond.load333
; CHECK-NEXT: mov w8, #84 // =0x54
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #21, .LBB37_137
; CHECK-NEXT: .LBB37_215: // %cond.load337
; CHECK-NEXT: mov w8, #85 // =0x55
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #22, .LBB37_138
; CHECK-NEXT: .LBB37_216: // %cond.load341
; CHECK-NEXT: mov w8, #86 // =0x56
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #23, .LBB37_139
; CHECK-NEXT: .LBB37_217: // %cond.load345
; CHECK-NEXT: mov w8, #87 // =0x57
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #24, .LBB37_140
; CHECK-NEXT: .LBB37_218: // %cond.load349
; CHECK-NEXT: mov w8, #88 // =0x58
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #25, .LBB37_141
; CHECK-NEXT: .LBB37_219: // %cond.load353
; CHECK-NEXT: mov w8, #89 // =0x59
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #26, .LBB37_142
; CHECK-NEXT: .LBB37_220: // %cond.load357
; CHECK-NEXT: mov w8, #90 // =0x5a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #27, .LBB37_143
; CHECK-NEXT: .LBB37_221: // %cond.load361
; CHECK-NEXT: mov w8, #91 // =0x5b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #28, .LBB37_144
; CHECK-NEXT: .LBB37_222: // %cond.load365
; CHECK-NEXT: mov w8, #92 // =0x5c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #29, .LBB37_145
; CHECK-NEXT: .LBB37_223: // %cond.load369
; CHECK-NEXT: mov w8, #93 // =0x5d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #30, .LBB37_146
; CHECK-NEXT: .LBB37_224: // %cond.load373
; CHECK-NEXT: mov w8, #94 // =0x5e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #31, .LBB37_147
; CHECK-NEXT: .LBB37_225: // %cond.load377
; CHECK-NEXT: mov w8, #95 // =0x5f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #32, .LBB37_148
; CHECK-NEXT: .LBB37_226: // %cond.load381
; CHECK-NEXT: mov w8, #96 // =0x60
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #33, .LBB37_149
; CHECK-NEXT: .LBB37_227: // %cond.load385
; CHECK-NEXT: mov w8, #97 // =0x61
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #34, .LBB37_150
; CHECK-NEXT: .LBB37_228: // %cond.load389
; CHECK-NEXT: mov w8, #98 // =0x62
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #35, .LBB37_151
; CHECK-NEXT: .LBB37_229: // %cond.load393
; CHECK-NEXT: mov w8, #99 // =0x63
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #36, .LBB37_152
; CHECK-NEXT: .LBB37_230: // %cond.load397
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #37, .LBB37_153
; CHECK-NEXT: .LBB37_231: // %cond.load401
; CHECK-NEXT: mov w8, #101 // =0x65
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #38, .LBB37_154
; CHECK-NEXT: .LBB37_232: // %cond.load405
; CHECK-NEXT: mov w8, #102 // =0x66
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #39, .LBB37_155
; CHECK-NEXT: .LBB37_233: // %cond.load409
; CHECK-NEXT: mov w8, #103 // =0x67
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #40, .LBB37_156
; CHECK-NEXT: .LBB37_234: // %cond.load413
; CHECK-NEXT: mov w8, #104 // =0x68
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #41, .LBB37_157
; CHECK-NEXT: .LBB37_235: // %cond.load417
; CHECK-NEXT: mov w8, #105 // =0x69
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #42, .LBB37_158
; CHECK-NEXT: .LBB37_236: // %cond.load421
; CHECK-NEXT: mov w8, #106 // =0x6a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #43, .LBB37_159
; CHECK-NEXT: .LBB37_237: // %cond.load425
; CHECK-NEXT: mov w8, #107 // =0x6b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #44, .LBB37_160
; CHECK-NEXT: .LBB37_238: // %cond.load429
; CHECK-NEXT: mov w8, #108 // =0x6c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #45, .LBB37_161
; CHECK-NEXT: .LBB37_239: // %cond.load433
; CHECK-NEXT: mov w8, #109 // =0x6d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #46, .LBB37_162
; CHECK-NEXT: .LBB37_240: // %cond.load437
; CHECK-NEXT: mov w8, #110 // =0x6e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #47, .LBB37_163
; CHECK-NEXT: .LBB37_241: // %cond.load441
; CHECK-NEXT: mov w8, #111 // =0x6f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #48, .LBB37_164
; CHECK-NEXT: .LBB37_242: // %cond.load445
; CHECK-NEXT: mov w8, #112 // =0x70
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #49, .LBB37_165
; CHECK-NEXT: .LBB37_243: // %cond.load449
; CHECK-NEXT: mov w8, #113 // =0x71
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #50, .LBB37_166
; CHECK-NEXT: .LBB37_244: // %cond.load453
; CHECK-NEXT: mov w8, #114 // =0x72
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #51, .LBB37_167
; CHECK-NEXT: .LBB37_245: // %cond.load457
; CHECK-NEXT: mov w8, #115 // =0x73
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #52, .LBB37_168
; CHECK-NEXT: .LBB37_246: // %cond.load461
; CHECK-NEXT: mov w8, #116 // =0x74
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #53, .LBB37_169
; CHECK-NEXT: .LBB37_247: // %cond.load465
; CHECK-NEXT: mov w8, #117 // =0x75
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #54, .LBB37_170
; CHECK-NEXT: .LBB37_248: // %cond.load469
; CHECK-NEXT: mov w8, #118 // =0x76
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #55, .LBB37_171
; CHECK-NEXT: .LBB37_249: // %cond.load473
; CHECK-NEXT: mov w8, #119 // =0x77
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #56, .LBB37_172
; CHECK-NEXT: .LBB37_250: // %cond.load477
; CHECK-NEXT: mov w8, #120 // =0x78
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #57, .LBB37_173
; CHECK-NEXT: .LBB37_251: // %cond.load481
; CHECK-NEXT: mov w8, #121 // =0x79
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #58, .LBB37_174
; CHECK-NEXT: .LBB37_252: // %cond.load485
; CHECK-NEXT: mov w8, #122 // =0x7a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #59, .LBB37_175
; CHECK-NEXT: .LBB37_253: // %cond.load489
; CHECK-NEXT: mov w8, #123 // =0x7b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #60, .LBB37_176
; CHECK-NEXT: .LBB37_254: // %cond.load493
; CHECK-NEXT: mov w8, #124 // =0x7c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #61, .LBB37_177
; CHECK-NEXT: .LBB37_255: // %cond.load497
; CHECK-NEXT: mov w8, #125 // =0x7d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #62, .LBB37_178
; CHECK-NEXT: .LBB37_256: // %cond.load501
; CHECK-NEXT: mov w8, #126 // =0x7e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbnz x9, #63, .LBB37_179
; CHECK-NEXT: b .LBB37_180
;
@@ -20951,34 +20951,34 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: ptrue p1.b, vl128
; CHECK-NEXT: ld1b { z0.b }, p1/z, [x1]
; CHECK-NEXT: cmpeq p0.b, p1/z, z0.b, #0
-; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: umov w9, v1.b[1]
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov z0.b, z1.b[18]
-; CHECK-NEXT: umov w10, v1.b[7]
-; CHECK-NEXT: umov w11, v1.b[8]
-; CHECK-NEXT: mov z2.b, z1.b[19]
-; CHECK-NEXT: umov w12, v1.b[2]
-; CHECK-NEXT: umov w14, v1.b[9]
-; CHECK-NEXT: umov w13, v1.b[3]
+; CHECK-NEXT: umov w9, v0.b[1]
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov z1.b, z0.b[18]
+; CHECK-NEXT: umov w10, v0.b[7]
+; CHECK-NEXT: umov w11, v0.b[8]
+; CHECK-NEXT: mov z2.b, z0.b[19]
+; CHECK-NEXT: umov w12, v0.b[2]
+; CHECK-NEXT: umov w14, v0.b[9]
+; CHECK-NEXT: umov w13, v0.b[3]
; CHECK-NEXT: and x8, x8, #0x1
-; CHECK-NEXT: fmov w16, s0
-; CHECK-NEXT: mov z0.b, z1.b[20]
+; CHECK-NEXT: fmov w16, s1
+; CHECK-NEXT: mov z1.b, z0.b[20]
; CHECK-NEXT: bfi x8, x9, #1, #1
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: umov w15, v1.b[10]
+; CHECK-NEXT: umov w15, v0.b[10]
; CHECK-NEXT: ubfiz x10, x10, #7, #1
; CHECK-NEXT: ubfiz x11, x11, #8, #1
-; CHECK-NEXT: mov z2.b, z1.b[21]
+; CHECK-NEXT: mov z2.b, z0.b[21]
; CHECK-NEXT: bfi x8, x12, #2, #1
-; CHECK-NEXT: fmov w12, s0
+; CHECK-NEXT: fmov w12, s1
; CHECK-NEXT: ubfiz x16, x16, #18, #1
; CHECK-NEXT: ubfiz x9, x9, #19, #1
; CHECK-NEXT: ubfiz x14, x14, #9, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: umov w11, v1.b[11]
-; CHECK-NEXT: mov z0.b, z1.b[22]
+; CHECK-NEXT: umov w11, v0.b[11]
+; CHECK-NEXT: mov z1.b, z0.b[22]
; CHECK-NEXT: ubfiz x15, x15, #10, #1
; CHECK-NEXT: ubfiz x12, x12, #20, #1
; CHECK-NEXT: orr x9, x16, x9
@@ -20987,195 +20987,195 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: bfi x8, x13, #3, #1
; CHECK-NEXT: orr x10, x10, x15
; CHECK-NEXT: orr x9, x9, x12
-; CHECK-NEXT: umov w12, v1.b[12]
-; CHECK-NEXT: fmov w13, s0
+; CHECK-NEXT: umov w12, v0.b[12]
+; CHECK-NEXT: fmov w13, s1
; CHECK-NEXT: ubfiz x11, x11, #11, #1
-; CHECK-NEXT: umov w15, v1.b[13]
-; CHECK-NEXT: mov z0.b, z1.b[16]
+; CHECK-NEXT: umov w15, v0.b[13]
+; CHECK-NEXT: mov z1.b, z0.b[16]
; CHECK-NEXT: ubfiz x14, x14, #21, #1
-; CHECK-NEXT: mov z2.b, z1.b[17]
-; CHECK-NEXT: umov w16, v1.b[4]
+; CHECK-NEXT: mov z2.b, z0.b[17]
+; CHECK-NEXT: umov w16, v0.b[4]
; CHECK-NEXT: ubfiz x13, x13, #22, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: umov w11, v1.b[14]
+; CHECK-NEXT: umov w11, v0.b[14]
; CHECK-NEXT: orr x9, x9, x14
; CHECK-NEXT: ubfiz x12, x12, #12, #1
-; CHECK-NEXT: umov w14, v1.b[5]
+; CHECK-NEXT: umov w14, v0.b[5]
; CHECK-NEXT: orr x9, x9, x13
-; CHECK-NEXT: umov w13, v1.b[15]
+; CHECK-NEXT: umov w13, v0.b[15]
; CHECK-NEXT: ubfiz x15, x15, #13, #1
; CHECK-NEXT: orr x10, x10, x12
-; CHECK-NEXT: fmov w12, s0
-; CHECK-NEXT: mov z0.b, z1.b[23]
+; CHECK-NEXT: fmov w12, s1
+; CHECK-NEXT: mov z1.b, z0.b[23]
; CHECK-NEXT: ubfiz x11, x11, #14, #1
; CHECK-NEXT: orr x10, x10, x15
; CHECK-NEXT: fmov w15, s2
-; CHECK-NEXT: mov z2.b, z1.b[24]
+; CHECK-NEXT: mov z2.b, z0.b[24]
; CHECK-NEXT: bfi x8, x16, #4, #1
-; CHECK-NEXT: umov w16, v1.b[6]
+; CHECK-NEXT: umov w16, v0.b[6]
; CHECK-NEXT: ubfiz x13, x13, #15, #1
; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: fmov w11, s0
-; CHECK-NEXT: mov z0.b, z1.b[25]
+; CHECK-NEXT: fmov w11, s1
+; CHECK-NEXT: mov z1.b, z0.b[25]
; CHECK-NEXT: ubfiz x12, x12, #16, #1
; CHECK-NEXT: bfi x8, x14, #5, #1
; CHECK-NEXT: orr x10, x10, x13
; CHECK-NEXT: fmov w13, s2
-; CHECK-NEXT: mov z2.b, z1.b[26]
+; CHECK-NEXT: mov z2.b, z0.b[26]
; CHECK-NEXT: ubfiz x11, x11, #23, #1
; CHECK-NEXT: orr x10, x10, x12
; CHECK-NEXT: ubfiz x14, x15, #17, #1
-; CHECK-NEXT: fmov w12, s0
-; CHECK-NEXT: mov z0.b, z1.b[27]
+; CHECK-NEXT: fmov w12, s1
+; CHECK-NEXT: mov z1.b, z0.b[27]
; CHECK-NEXT: bfi x8, x16, #6, #1
; CHECK-NEXT: ubfiz x13, x13, #24, #1
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: fmov w11, s2
-; CHECK-NEXT: mov z2.b, z1.b[28]
+; CHECK-NEXT: mov z2.b, z0.b[28]
; CHECK-NEXT: orr x10, x10, x14
; CHECK-NEXT: orr x9, x9, x13
; CHECK-NEXT: ubfiz x12, x12, #25, #1
-; CHECK-NEXT: fmov w13, s0
-; CHECK-NEXT: mov z0.b, z1.b[29]
+; CHECK-NEXT: fmov w13, s1
+; CHECK-NEXT: mov z1.b, z0.b[29]
; CHECK-NEXT: ubfiz x11, x11, #26, #1
; CHECK-NEXT: orr x8, x8, x10
; CHECK-NEXT: orr x9, x9, x12
; CHECK-NEXT: fmov w12, s2
-; CHECK-NEXT: mov z2.b, z1.b[30]
+; CHECK-NEXT: mov z2.b, z0.b[30]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x11, x13, #27, #1
-; CHECK-NEXT: fmov w13, s0
-; CHECK-NEXT: mov z0.b, z1.b[31]
+; CHECK-NEXT: fmov w13, s1
+; CHECK-NEXT: mov z1.b, z0.b[31]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x12, x12, #28, #1
; CHECK-NEXT: ubfiz x11, x13, #29, #1
; CHECK-NEXT: fmov w13, s2
; CHECK-NEXT: orr x9, x9, x12
-; CHECK-NEXT: mov z2.b, z1.b[32]
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov z0.b, z1.b[33]
+; CHECK-NEXT: mov z2.b, z0.b[32]
+; CHECK-NEXT: fmov w10, s1
+; CHECK-NEXT: mov z1.b, z0.b[33]
; CHECK-NEXT: orr x9, x9, x11
; CHECK-NEXT: ubfiz x12, x13, #30, #1
; CHECK-NEXT: lsl w10, w10, #31
; CHECK-NEXT: orr x9, x9, x12
; CHECK-NEXT: orr x8, x8, x9
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[34]
+; CHECK-NEXT: mov z2.b, z0.b[34]
; CHECK-NEXT: orr x8, x8, x10
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #32
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[35]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[35]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #33
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[36]
+; CHECK-NEXT: mov z2.b, z0.b[36]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #34
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[37]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[37]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #35
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[38]
+; CHECK-NEXT: mov z2.b, z0.b[38]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #36
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[39]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[39]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #37
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[40]
+; CHECK-NEXT: mov z2.b, z0.b[40]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #38
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[41]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[41]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #39
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[42]
+; CHECK-NEXT: mov z2.b, z0.b[42]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #40
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[43]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[43]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #41
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[44]
+; CHECK-NEXT: mov z2.b, z0.b[44]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #42
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[45]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[45]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #43
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[46]
+; CHECK-NEXT: mov z2.b, z0.b[46]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #44
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[47]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[47]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #45
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[48]
+; CHECK-NEXT: mov z2.b, z0.b[48]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #46
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[49]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[49]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #47
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[50]
+; CHECK-NEXT: mov z2.b, z0.b[50]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #48
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[51]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[51]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #49
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[52]
+; CHECK-NEXT: mov z2.b, z0.b[52]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #50
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[53]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[53]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #51
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[54]
+; CHECK-NEXT: mov z2.b, z0.b[54]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #52
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[55]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[55]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #53
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[56]
+; CHECK-NEXT: mov z2.b, z0.b[56]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #54
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[57]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[57]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #55
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[58]
+; CHECK-NEXT: mov z2.b, z0.b[58]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #56
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[59]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[59]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #57
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[60]
+; CHECK-NEXT: mov z2.b, z0.b[60]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #58
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: mov z0.b, z1.b[61]
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: mov z1.b, z0.b[61]
; CHECK-NEXT: and w9, w9, #0x1
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov z0.b, z1.b[63]
+; CHECK-NEXT: fmov w10, s1
+; CHECK-NEXT: mov z1.b, z0.b[63]
; CHECK-NEXT: orr x8, x8, x9, lsl #59
; CHECK-NEXT: fmov w9, s2
-; CHECK-NEXT: mov z2.b, z1.b[62]
+; CHECK-NEXT: mov z2.b, z0.b[62]
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #60
; CHECK-NEXT: and w9, w10, #0x1
@@ -21183,18 +21183,18 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: orr x8, x8, x9, lsl #62
-; CHECK-NEXT: fmov w9, s0
+; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: orr x8, x8, x9, lsl #63
; CHECK-NEXT: tbz w8, #0, .LBB43_2
; CHECK-NEXT: // %bb.1: // %cond.load
-; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1rb { z1.b }, p0/z, [x0]
; CHECK-NEXT: add x0, x0, #1
; CHECK-NEXT: tbnz w8, #1, .LBB43_3
; CHECK-NEXT: b .LBB43_4
; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: adrp x9, .LCPI43_0
; CHECK-NEXT: add x9, x9, :lo12:.LCPI43_0
-; CHECK-NEXT: ld1b { z0.b }, p1/z, [x9]
+; CHECK-NEXT: ld1b { z1.b }, p1/z, [x9]
; CHECK-NEXT: tbz w8, #1, .LBB43_4
; CHECK-NEXT: .LBB43_3: // %cond.load1
; CHECK-NEXT: mov w9, #1 // =0x1
@@ -21202,7 +21202,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: .LBB43_4: // %else2
; CHECK-NEXT: tbnz w8, #2, .LBB43_181
; CHECK-NEXT: // %bb.5: // %else6
@@ -21231,7 +21231,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: .LBB43_16: // %else46
; CHECK-NEXT: mov w12, #71 // =0x47
; CHECK-NEXT: mov w14, #72 // =0x48
@@ -21244,7 +21244,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w11
+; CHECK-NEXT: mov z1.b, p1/m, w11
; CHECK-NEXT: .LBB43_18: // %else50
; CHECK-NEXT: mov w11, #73 // =0x49
; CHECK-NEXT: mov w13, #85 // =0x55
@@ -21255,7 +21255,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w15
; CHECK-NEXT: ldrb w15, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w15
+; CHECK-NEXT: mov z1.b, p1/m, w15
; CHECK-NEXT: .LBB43_20: // %else54
; CHECK-NEXT: whilels p3.b, xzr, x12
; CHECK-NEXT: whilels p4.b, xzr, x14
@@ -21270,14 +21270,14 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p5.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p5/m, w10
+; CHECK-NEXT: mov z1.b, p5/m, w10
; CHECK-NEXT: .LBB43_22: // %else58
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: mov w1, #75 // =0x4b
; CHECK-NEXT: mov w17, #87 // =0x57
-; CHECK-NEXT: lastb w12, p4, z1.b
-; CHECK-NEXT: lastb w15, p1, z1.b
-; CHECK-NEXT: lastb w16, p2, z1.b
+; CHECK-NEXT: lastb w12, p4, z0.b
+; CHECK-NEXT: lastb w15, p1, z0.b
+; CHECK-NEXT: lastb w16, p2, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x11
; CHECK-NEXT: whilels p1.b, xzr, x13
; CHECK-NEXT: tbz w8, #16, .LBB43_24
@@ -21287,12 +21287,12 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w11
+; CHECK-NEXT: mov z1.b, p3/m, w11
; CHECK-NEXT: .LBB43_24: // %else62
-; CHECK-NEXT: lastb w11, p2, z1.b
+; CHECK-NEXT: lastb w11, p2, z0.b
; CHECK-NEXT: mov w3, #76 // =0x4c
; CHECK-NEXT: mov w18, #88 // =0x58
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x9
; CHECK-NEXT: whilels p1.b, xzr, x14
; CHECK-NEXT: tbz w8, #17, .LBB43_26
@@ -21302,15 +21302,15 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w9
+; CHECK-NEXT: mov z1.b, p3/m, w9
; CHECK-NEXT: .LBB43_26: // %else66
-; CHECK-NEXT: lastb w9, p2, z1.b
+; CHECK-NEXT: lastb w9, p2, z0.b
; CHECK-NEXT: ubfiz x5, x10, #7, #1
; CHECK-NEXT: ubfiz x7, x12, #8, #1
; CHECK-NEXT: ubfiz x4, x15, #19, #1
; CHECK-NEXT: ubfiz x6, x16, #20, #1
; CHECK-NEXT: mov w15, #89 // =0x59
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x1
; CHECK-NEXT: mov w1, #77 // =0x4d
; CHECK-NEXT: whilels p1.b, xzr, x17
@@ -21322,7 +21322,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w10
+; CHECK-NEXT: mov z1.b, p3/m, w10
; CHECK-NEXT: .LBB43_28: // %else70
; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp x24, x23, [sp, #16] // 16-byte Folded Spill
@@ -21335,13 +21335,13 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w23, -40
; CHECK-NEXT: .cfi_offset w24, -48
-; CHECK-NEXT: lastb w10, p2, z1.b
+; CHECK-NEXT: lastb w10, p2, z0.b
; CHECK-NEXT: orr x7, x5, x7
; CHECK-NEXT: ubfiz x5, x13, #21, #1
; CHECK-NEXT: mov w16, #65 // =0x41
; CHECK-NEXT: orr x19, x4, x6
; CHECK-NEXT: mov w4, #90 // =0x5a
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: whilels p2.b, xzr, x3
; CHECK-NEXT: ubfiz x3, x11, #9, #1
; CHECK-NEXT: whilels p1.b, xzr, x18
@@ -21353,15 +21353,15 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p3.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p3/m, w11
+; CHECK-NEXT: mov z1.b, p3/m, w11
; CHECK-NEXT: .LBB43_30: // %else74
-; CHECK-NEXT: lastb w11, p2, z1.b
+; CHECK-NEXT: lastb w11, p2, z0.b
; CHECK-NEXT: ubfiz x21, x9, #10, #1
; CHECK-NEXT: ubfiz x6, x14, #22, #1
; CHECK-NEXT: orr x7, x7, x3
; CHECK-NEXT: mov w3, #79 // =0x4f
; CHECK-NEXT: orr x20, x19, x5
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: mov w5, #91 // =0x5b
; CHECK-NEXT: whilels p3.b, xzr, x17
; CHECK-NEXT: mov w17, #66 // =0x42
@@ -21374,17 +21374,17 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w9
+; CHECK-NEXT: mov z1.b, p4/m, w9
; CHECK-NEXT: .LBB43_32: // %else78
-; CHECK-NEXT: lastb w9, p3, z1.b
+; CHECK-NEXT: lastb w9, p3, z0.b
; CHECK-NEXT: orr x19, x7, x21
; CHECK-NEXT: ubfiz x21, x10, #11, #1
; CHECK-NEXT: ubfiz x7, x12, #23, #1
; CHECK-NEXT: mov w1, #67 // =0x43
; CHECK-NEXT: orr x22, x20, x6
-; CHECK-NEXT: lastb w14, p2, z1.b
+; CHECK-NEXT: lastb w14, p2, z0.b
; CHECK-NEXT: mov w6, #92 // =0x5c
-; CHECK-NEXT: lastb w15, p1, z1.b
+; CHECK-NEXT: lastb w15, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x16
; CHECK-NEXT: whilels p2.b, xzr, x18
; CHECK-NEXT: whilels p1.b, xzr, x4
@@ -21396,17 +21396,17 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w10
+; CHECK-NEXT: mov z1.b, p4/m, w10
; CHECK-NEXT: .LBB43_34: // %else82
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: orr x20, x19, x21
; CHECK-NEXT: ubfiz x21, x11, #12, #1
; CHECK-NEXT: ubfiz x19, x13, #24, #1
; CHECK-NEXT: mov w18, #68 // =0x44
; CHECK-NEXT: orr x23, x22, x7
-; CHECK-NEXT: lastb w12, p2, z1.b
+; CHECK-NEXT: lastb w12, p2, z0.b
; CHECK-NEXT: mov w7, #93 // =0x5d
-; CHECK-NEXT: lastb w16, p1, z1.b
+; CHECK-NEXT: lastb w16, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x17
; CHECK-NEXT: whilels p2.b, xzr, x3
; CHECK-NEXT: whilels p1.b, xzr, x5
@@ -21418,18 +21418,18 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w11
+; CHECK-NEXT: mov z1.b, p4/m, w11
; CHECK-NEXT: .LBB43_36: // %else86
-; CHECK-NEXT: lastb w11, p3, z1.b
+; CHECK-NEXT: lastb w11, p3, z0.b
; CHECK-NEXT: orr x20, x20, x21
; CHECK-NEXT: ubfiz x21, x14, #13, #1
; CHECK-NEXT: ubfiz x22, x15, #25, #1
; CHECK-NEXT: and x9, x9, #0x1
; CHECK-NEXT: mov w3, #69 // =0x45
-; CHECK-NEXT: lastb w13, p2, z1.b
+; CHECK-NEXT: lastb w13, p2, z0.b
; CHECK-NEXT: orr x24, x23, x19
; CHECK-NEXT: mov w19, #94 // =0x5e
-; CHECK-NEXT: lastb w17, p1, z1.b
+; CHECK-NEXT: lastb w17, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x1
; CHECK-NEXT: whilels p2.b, xzr, x4
; CHECK-NEXT: mov w4, #82 // =0x52
@@ -21442,13 +21442,13 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w14
+; CHECK-NEXT: mov z1.b, p4/m, w14
; CHECK-NEXT: .LBB43_38: // %else90
-; CHECK-NEXT: lastb w14, p3, z1.b
+; CHECK-NEXT: lastb w14, p3, z0.b
; CHECK-NEXT: bfi x9, x10, #1, #1
; CHECK-NEXT: ubfiz x23, x16, #26, #1
-; CHECK-NEXT: lastb w15, p2, z1.b
-; CHECK-NEXT: lastb w1, p1, z1.b
+; CHECK-NEXT: lastb w15, p2, z0.b
+; CHECK-NEXT: lastb w1, p1, z0.b
; CHECK-NEXT: whilels p3.b, xzr, x18
; CHECK-NEXT: whilels p2.b, xzr, x5
; CHECK-NEXT: ubfiz x5, x12, #14, #1
@@ -21463,13 +21463,13 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
; CHECK-NEXT: cmpeq p4.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p4/m, w10
+; CHECK-NEXT: mov z1.b, p4/m, w10
; CHECK-NEXT: .LBB43_40: // %else94
-; CHECK-NEXT: lastb w10, p3, z1.b
+; CHECK-NEXT: lastb w10, p3, z0.b
; CHECK-NEXT: bfi x9, x11, #2, #1
; CHECK-NEXT: orr x5, x7, x5
-; CHECK-NEXT: lastb w16, p2, z1.b
-; CHECK-NEXT: lastb w18, p1, z1.b
+; CHECK-NEXT: lastb w16, p2, z0.b
+; CHECK-NEXT: lastb w18, p1, z0.b
; CHECK-NEXT: whilels p4.b, xzr, x3
; CHECK-NEXT: ubfiz x3, x13, #15, #1
; CHECK-NEXT: whilels p2.b, xzr, x4
@@ -21484,18 +21484,18 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p5.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p5/m, w11
+; CHECK-NEXT: mov z1.b, p5/m, w11
; CHECK-NEXT: .LBB43_42: // %else98
-; CHECK-NEXT: lastb w11, p4, z1.b
+; CHECK-NEXT: lastb w11, p4, z0.b
; CHECK-NEXT: bfi x9, x14, #3, #1
; CHECK-NEXT: ubfiz x15, x15, #16, #1
; CHECK-NEXT: ubfiz x1, x1, #28, #1
; CHECK-NEXT: orr x3, x5, x3
; CHECK-NEXT: orr x4, x6, x4
-; CHECK-NEXT: lastb w13, p2, z1.b
+; CHECK-NEXT: lastb w13, p2, z0.b
; CHECK-NEXT: mov w14, #96 // =0x60
-; CHECK-NEXT: lastb w17, p1, z1.b
-; CHECK-NEXT: lastb w7, p3, z1.b
+; CHECK-NEXT: lastb w17, p1, z0.b
+; CHECK-NEXT: lastb w7, p3, z0.b
; CHECK-NEXT: whilels p1.b, xzr, x12
; CHECK-NEXT: tbz w8, #26, .LBB43_44
; CHECK-NEXT: // %bb.43: // %cond.load101
@@ -21504,9 +21504,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w12
+; CHECK-NEXT: mov z1.b, p2/m, w12
; CHECK-NEXT: .LBB43_44: // %else102
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: bfi x9, x10, #4, #1
; CHECK-NEXT: ubfiz x16, x16, #17, #1
; CHECK-NEXT: ubfiz x18, x18, #29, #1
@@ -21521,7 +21521,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w4
; CHECK-NEXT: ldrb w4, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w4
+; CHECK-NEXT: mov z1.b, p1/m, w4
; CHECK-NEXT: .LBB43_46: // %else106
; CHECK-NEXT: bfi x9, x11, #5, #1
; CHECK-NEXT: ubfiz x13, x13, #18, #1
@@ -21537,9 +21537,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_48: // %else110
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: bfi x9, x12, #6, #1
; CHECK-NEXT: mov w12, #99 // =0x63
; CHECK-NEXT: whilels p1.b, xzr, x15
@@ -21552,9 +21552,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_50: // %else114
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x9, x15
; CHECK-NEXT: orr x10, x16, x10
; CHECK-NEXT: and w9, w14, #0x1
@@ -21567,9 +21567,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_52: // %else118
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21581,9 +21581,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_54: // %else122
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #32
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21595,9 +21595,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_56: // %else126
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #33
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21609,9 +21609,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_58: // %else130
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #34
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21623,9 +21623,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_60: // %else134
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #35
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21637,9 +21637,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_62: // %else138
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #36
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21651,9 +21651,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_64: // %else142
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #37
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21665,9 +21665,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_66: // %else146
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #38
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21679,9 +21679,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_68: // %else150
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #39
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21693,9 +21693,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_70: // %else154
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #40
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21707,9 +21707,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_72: // %else158
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #41
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21721,9 +21721,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_74: // %else162
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #42
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21735,9 +21735,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_76: // %else166
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #43
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21749,9 +21749,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_78: // %else170
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #44
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21763,9 +21763,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_80: // %else174
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #45
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21777,9 +21777,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_82: // %else178
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #46
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21791,9 +21791,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_84: // %else182
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #47
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21805,9 +21805,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_86: // %else186
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #48
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21819,9 +21819,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_88: // %else190
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #49
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21833,9 +21833,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_90: // %else194
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #50
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21847,9 +21847,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_92: // %else198
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #51
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21861,9 +21861,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_94: // %else202
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #52
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21875,9 +21875,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_96: // %else206
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #53
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21889,9 +21889,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_98: // %else210
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #54
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21903,9 +21903,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_100: // %else214
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #55
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21917,9 +21917,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w13
; CHECK-NEXT: ldrb w13, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w13
+; CHECK-NEXT: mov z1.b, p2/m, w13
; CHECK-NEXT: .LBB43_102: // %else218
-; CHECK-NEXT: lastb w13, p1, z1.b
+; CHECK-NEXT: lastb w13, p1, z0.b
; CHECK-NEXT: orr x15, x15, x9, lsl #56
; CHECK-NEXT: and w9, w14, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21931,9 +21931,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_104: // %else222
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x15, x15, x10, lsl #57
; CHECK-NEXT: and w10, w13, #0x1
; CHECK-NEXT: whilels p1.b, xzr, x12
@@ -21944,9 +21944,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w12
+; CHECK-NEXT: mov z1.b, p2/m, w12
; CHECK-NEXT: .LBB43_106: // %else226
-; CHECK-NEXT: lastb w12, p1, z1.b
+; CHECK-NEXT: lastb w12, p1, z0.b
; CHECK-NEXT: orr x13, x15, x9, lsl #58
; CHECK-NEXT: mov w9, #127 // =0x7f
; CHECK-NEXT: whilels p1.b, xzr, x11
@@ -21958,9 +21958,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w14
; CHECK-NEXT: ldrb w14, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w14
+; CHECK-NEXT: mov z1.b, p2/m, w14
; CHECK-NEXT: .LBB43_108: // %else230
-; CHECK-NEXT: lastb w14, p1, z1.b
+; CHECK-NEXT: lastb w14, p1, z0.b
; CHECK-NEXT: orr x13, x13, x10, lsl #59
; CHECK-NEXT: and w10, w12, #0x1
; CHECK-NEXT: tbz x8, #59, .LBB43_110
@@ -21970,7 +21970,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w12
+; CHECK-NEXT: mov z1.b, p1/m, w12
; CHECK-NEXT: .LBB43_110: // %else234
; CHECK-NEXT: orr x12, x13, x11, lsl #60
; CHECK-NEXT: whilels p1.b, xzr, x9
@@ -21982,9 +21982,9 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w11
; CHECK-NEXT: ldrb w11, [x0], #1
; CHECK-NEXT: cmpeq p2.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p2/m, w11
+; CHECK-NEXT: mov z1.b, p2/m, w11
; CHECK-NEXT: .LBB43_112: // %else238
-; CHECK-NEXT: lastb w11, p1, z1.b
+; CHECK-NEXT: lastb w11, p1, z0.b
; CHECK-NEXT: orr x10, x12, x10, lsl #61
; CHECK-NEXT: tbnz x8, #61, .LBB43_191
; CHECK-NEXT: // %bb.113: // %else242
@@ -22123,13 +22123,13 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: tbz x9, #63, .LBB43_180
; CHECK-NEXT: .LBB43_179: // %cond.load505
; CHECK-NEXT: mov w8, #127 // =0x7f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: .LBB43_180: // %else506
-; CHECK-NEXT: uunpklo z0.h, z0.b
+; CHECK-NEXT: uunpklo z0.h, z1.b
; CHECK-NEXT: ptrue p0.h, vl128
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #32] // 16-byte Folded Reload
@@ -22143,7 +22143,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #3, .LBB43_6
; CHECK-NEXT: .LBB43_182: // %cond.load9
; CHECK-NEXT: mov w9, #3 // =0x3
@@ -22151,7 +22151,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #4, .LBB43_7
; CHECK-NEXT: .LBB43_183: // %cond.load13
; CHECK-NEXT: mov w9, #4 // =0x4
@@ -22159,7 +22159,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #5, .LBB43_8
; CHECK-NEXT: .LBB43_184: // %cond.load17
; CHECK-NEXT: mov w9, #5 // =0x5
@@ -22167,7 +22167,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #6, .LBB43_9
; CHECK-NEXT: .LBB43_185: // %cond.load21
; CHECK-NEXT: mov w9, #6 // =0x6
@@ -22175,7 +22175,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #7, .LBB43_10
; CHECK-NEXT: .LBB43_186: // %cond.load25
; CHECK-NEXT: mov w9, #7 // =0x7
@@ -22183,7 +22183,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #8, .LBB43_11
; CHECK-NEXT: .LBB43_187: // %cond.load29
; CHECK-NEXT: mov w9, #8 // =0x8
@@ -22191,7 +22191,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #9, .LBB43_12
; CHECK-NEXT: .LBB43_188: // %cond.load33
; CHECK-NEXT: mov w9, #9 // =0x9
@@ -22199,7 +22199,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #10, .LBB43_13
; CHECK-NEXT: .LBB43_189: // %cond.load37
; CHECK-NEXT: mov w9, #10 // =0xa
@@ -22207,7 +22207,7 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbz w8, #11, .LBB43_14
; CHECK-NEXT: .LBB43_190: // %cond.load41
; CHECK-NEXT: mov w9, #11 // =0xb
@@ -22215,538 +22215,538 @@ define void @masked_load_zext_v128i8i16(ptr %ap, ptr %bp, ptr %c) vscale_range(1
; CHECK-NEXT: mov z3.b, w9
; CHECK-NEXT: ldrb w9, [x0], #1
; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z3.b
-; CHECK-NEXT: mov z0.b, p1/m, w9
+; CHECK-NEXT: mov z1.b, p1/m, w9
; CHECK-NEXT: tbnz w8, #12, .LBB43_15
; CHECK-NEXT: b .LBB43_16
; CHECK-NEXT: .LBB43_191: // %cond.load241
; CHECK-NEXT: mov w12, #61 // =0x3d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w12
; CHECK-NEXT: ldrb w12, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w12
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w12
; CHECK-NEXT: orr x9, x10, x9, lsl #62
; CHECK-NEXT: tbz x8, #62, .LBB43_114
; CHECK-NEXT: .LBB43_192: // %cond.load245
; CHECK-NEXT: mov w10, #62 // =0x3e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w10
; CHECK-NEXT: ldrb w10, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w10
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w10
; CHECK-NEXT: orr x9, x9, x11, lsl #63
; CHECK-NEXT: tbz x8, #63, .LBB43_115
; CHECK-NEXT: .LBB43_193: // %cond.load249
; CHECK-NEXT: mov w8, #63 // =0x3f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #0, .LBB43_116
; CHECK-NEXT: .LBB43_194: // %cond.load253
; CHECK-NEXT: mov w8, #64 // =0x40
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #1, .LBB43_117
; CHECK-NEXT: .LBB43_195: // %cond.load257
; CHECK-NEXT: mov w8, #65 // =0x41
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #2, .LBB43_118
; CHECK-NEXT: .LBB43_196: // %cond.load261
; CHECK-NEXT: mov w8, #66 // =0x42
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #3, .LBB43_119
; CHECK-NEXT: .LBB43_197: // %cond.load265
; CHECK-NEXT: mov w8, #67 // =0x43
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #4, .LBB43_120
; CHECK-NEXT: .LBB43_198: // %cond.load269
; CHECK-NEXT: mov w8, #68 // =0x44
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #5, .LBB43_121
; CHECK-NEXT: .LBB43_199: // %cond.load273
; CHECK-NEXT: mov w8, #69 // =0x45
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #6, .LBB43_122
; CHECK-NEXT: .LBB43_200: // %cond.load277
; CHECK-NEXT: mov w8, #70 // =0x46
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #7, .LBB43_123
; CHECK-NEXT: .LBB43_201: // %cond.load281
; CHECK-NEXT: mov w8, #71 // =0x47
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #8, .LBB43_124
; CHECK-NEXT: .LBB43_202: // %cond.load285
; CHECK-NEXT: mov w8, #72 // =0x48
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #9, .LBB43_125
; CHECK-NEXT: .LBB43_203: // %cond.load289
; CHECK-NEXT: mov w8, #73 // =0x49
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #10, .LBB43_126
; CHECK-NEXT: .LBB43_204: // %cond.load293
; CHECK-NEXT: mov w8, #74 // =0x4a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #11, .LBB43_127
; CHECK-NEXT: .LBB43_205: // %cond.load297
; CHECK-NEXT: mov w8, #75 // =0x4b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #12, .LBB43_128
; CHECK-NEXT: .LBB43_206: // %cond.load301
; CHECK-NEXT: mov w8, #76 // =0x4c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #13, .LBB43_129
; CHECK-NEXT: .LBB43_207: // %cond.load305
; CHECK-NEXT: mov w8, #77 // =0x4d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #14, .LBB43_130
; CHECK-NEXT: .LBB43_208: // %cond.load309
; CHECK-NEXT: mov w8, #78 // =0x4e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #15, .LBB43_131
; CHECK-NEXT: .LBB43_209: // %cond.load313
; CHECK-NEXT: mov w8, #79 // =0x4f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #16, .LBB43_132
; CHECK-NEXT: .LBB43_210: // %cond.load317
; CHECK-NEXT: mov w8, #80 // =0x50
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #17, .LBB43_133
; CHECK-NEXT: .LBB43_211: // %cond.load321
; CHECK-NEXT: mov w8, #81 // =0x51
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #18, .LBB43_134
; CHECK-NEXT: .LBB43_212: // %cond.load325
; CHECK-NEXT: mov w8, #82 // =0x52
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #19, .LBB43_135
; CHECK-NEXT: .LBB43_213: // %cond.load329
; CHECK-NEXT: mov w8, #83 // =0x53
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #20, .LBB43_136
; CHECK-NEXT: .LBB43_214: // %cond.load333
; CHECK-NEXT: mov w8, #84 // =0x54
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #21, .LBB43_137
; CHECK-NEXT: .LBB43_215: // %cond.load337
; CHECK-NEXT: mov w8, #85 // =0x55
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #22, .LBB43_138
; CHECK-NEXT: .LBB43_216: // %cond.load341
; CHECK-NEXT: mov w8, #86 // =0x56
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #23, .LBB43_139
; CHECK-NEXT: .LBB43_217: // %cond.load345
; CHECK-NEXT: mov w8, #87 // =0x57
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #24, .LBB43_140
; CHECK-NEXT: .LBB43_218: // %cond.load349
; CHECK-NEXT: mov w8, #88 // =0x58
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #25, .LBB43_141
; CHECK-NEXT: .LBB43_219: // %cond.load353
; CHECK-NEXT: mov w8, #89 // =0x59
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #26, .LBB43_142
; CHECK-NEXT: .LBB43_220: // %cond.load357
; CHECK-NEXT: mov w8, #90 // =0x5a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #27, .LBB43_143
; CHECK-NEXT: .LBB43_221: // %cond.load361
; CHECK-NEXT: mov w8, #91 // =0x5b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #28, .LBB43_144
; CHECK-NEXT: .LBB43_222: // %cond.load365
; CHECK-NEXT: mov w8, #92 // =0x5c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #29, .LBB43_145
; CHECK-NEXT: .LBB43_223: // %cond.load369
; CHECK-NEXT: mov w8, #93 // =0x5d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #30, .LBB43_146
; CHECK-NEXT: .LBB43_224: // %cond.load373
; CHECK-NEXT: mov w8, #94 // =0x5e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz w9, #31, .LBB43_147
; CHECK-NEXT: .LBB43_225: // %cond.load377
; CHECK-NEXT: mov w8, #95 // =0x5f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #32, .LBB43_148
; CHECK-NEXT: .LBB43_226: // %cond.load381
; CHECK-NEXT: mov w8, #96 // =0x60
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #33, .LBB43_149
; CHECK-NEXT: .LBB43_227: // %cond.load385
; CHECK-NEXT: mov w8, #97 // =0x61
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #34, .LBB43_150
; CHECK-NEXT: .LBB43_228: // %cond.load389
; CHECK-NEXT: mov w8, #98 // =0x62
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #35, .LBB43_151
; CHECK-NEXT: .LBB43_229: // %cond.load393
; CHECK-NEXT: mov w8, #99 // =0x63
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #36, .LBB43_152
; CHECK-NEXT: .LBB43_230: // %cond.load397
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #37, .LBB43_153
; CHECK-NEXT: .LBB43_231: // %cond.load401
; CHECK-NEXT: mov w8, #101 // =0x65
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #38, .LBB43_154
; CHECK-NEXT: .LBB43_232: // %cond.load405
; CHECK-NEXT: mov w8, #102 // =0x66
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #39, .LBB43_155
; CHECK-NEXT: .LBB43_233: // %cond.load409
; CHECK-NEXT: mov w8, #103 // =0x67
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #40, .LBB43_156
; CHECK-NEXT: .LBB43_234: // %cond.load413
; CHECK-NEXT: mov w8, #104 // =0x68
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #41, .LBB43_157
; CHECK-NEXT: .LBB43_235: // %cond.load417
; CHECK-NEXT: mov w8, #105 // =0x69
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #42, .LBB43_158
; CHECK-NEXT: .LBB43_236: // %cond.load421
; CHECK-NEXT: mov w8, #106 // =0x6a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #43, .LBB43_159
; CHECK-NEXT: .LBB43_237: // %cond.load425
; CHECK-NEXT: mov w8, #107 // =0x6b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #44, .LBB43_160
; CHECK-NEXT: .LBB43_238: // %cond.load429
; CHECK-NEXT: mov w8, #108 // =0x6c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #45, .LBB43_161
; CHECK-NEXT: .LBB43_239: // %cond.load433
; CHECK-NEXT: mov w8, #109 // =0x6d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #46, .LBB43_162
; CHECK-NEXT: .LBB43_240: // %cond.load437
; CHECK-NEXT: mov w8, #110 // =0x6e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #47, .LBB43_163
; CHECK-NEXT: .LBB43_241: // %cond.load441
; CHECK-NEXT: mov w8, #111 // =0x6f
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #48, .LBB43_164
; CHECK-NEXT: .LBB43_242: // %cond.load445
; CHECK-NEXT: mov w8, #112 // =0x70
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #49, .LBB43_165
; CHECK-NEXT: .LBB43_243: // %cond.load449
; CHECK-NEXT: mov w8, #113 // =0x71
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #50, .LBB43_166
; CHECK-NEXT: .LBB43_244: // %cond.load453
; CHECK-NEXT: mov w8, #114 // =0x72
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #51, .LBB43_167
; CHECK-NEXT: .LBB43_245: // %cond.load457
; CHECK-NEXT: mov w8, #115 // =0x73
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #52, .LBB43_168
; CHECK-NEXT: .LBB43_246: // %cond.load461
; CHECK-NEXT: mov w8, #116 // =0x74
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #53, .LBB43_169
; CHECK-NEXT: .LBB43_247: // %cond.load465
; CHECK-NEXT: mov w8, #117 // =0x75
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #54, .LBB43_170
; CHECK-NEXT: .LBB43_248: // %cond.load469
; CHECK-NEXT: mov w8, #118 // =0x76
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #55, .LBB43_171
; CHECK-NEXT: .LBB43_249: // %cond.load473
; CHECK-NEXT: mov w8, #119 // =0x77
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #56, .LBB43_172
; CHECK-NEXT: .LBB43_250: // %cond.load477
; CHECK-NEXT: mov w8, #120 // =0x78
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #57, .LBB43_173
; CHECK-NEXT: .LBB43_251: // %cond.load481
; CHECK-NEXT: mov w8, #121 // =0x79
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #58, .LBB43_174
; CHECK-NEXT: .LBB43_252: // %cond.load485
; CHECK-NEXT: mov w8, #122 // =0x7a
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #59, .LBB43_175
; CHECK-NEXT: .LBB43_253: // %cond.load489
; CHECK-NEXT: mov w8, #123 // =0x7b
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #60, .LBB43_176
; CHECK-NEXT: .LBB43_254: // %cond.load493
; CHECK-NEXT: mov w8, #124 // =0x7c
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #61, .LBB43_177
; CHECK-NEXT: .LBB43_255: // %cond.load497
; CHECK-NEXT: mov w8, #125 // =0x7d
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbz x9, #62, .LBB43_178
; CHECK-NEXT: .LBB43_256: // %cond.load501
; CHECK-NEXT: mov w8, #126 // =0x7e
-; CHECK-NEXT: index z1.b, #0, #1
+; CHECK-NEXT: index z0.b, #0, #1
; CHECK-NEXT: mov z2.b, w8
; CHECK-NEXT: ldrb w8, [x0], #1
-; CHECK-NEXT: cmpeq p1.b, p0/z, z1.b, z2.b
-; CHECK-NEXT: mov z0.b, p1/m, w8
+; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT: mov z1.b, p1/m, w8
; CHECK-NEXT: tbnz x9, #63, .LBB43_179
; CHECK-NEXT: b .LBB43_180
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index be50ef3e17a71..913a45e1691e2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -2521,1172 +2521,1172 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_238: # %else886
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a4, v16
+; CHECK-RV32-NEXT: vmv.x.s a2, v16
; CHECK-RV32-NEXT: bgez a3, .LBB61_239
; CHECK-RV32-NEXT: j .LBB61_752
; CHECK-RV32-NEXT: .LBB61_239: # %else890
-; CHECK-RV32-NEXT: andi a2, a4, 1
-; CHECK-RV32-NEXT: beqz a2, .LBB61_240
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: beqz a3, .LBB61_240
; CHECK-RV32-NEXT: j .LBB61_753
; CHECK-RV32-NEXT: .LBB61_240: # %else894
-; CHECK-RV32-NEXT: andi a2, a4, 2
-; CHECK-RV32-NEXT: beqz a2, .LBB61_241
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: beqz a3, .LBB61_241
; CHECK-RV32-NEXT: j .LBB61_754
; CHECK-RV32-NEXT: .LBB61_241: # %else898
-; CHECK-RV32-NEXT: andi a2, a4, 4
-; CHECK-RV32-NEXT: beqz a2, .LBB61_242
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: beqz a3, .LBB61_242
; CHECK-RV32-NEXT: j .LBB61_755
; CHECK-RV32-NEXT: .LBB61_242: # %else902
-; CHECK-RV32-NEXT: andi a2, a4, 8
-; CHECK-RV32-NEXT: beqz a2, .LBB61_243
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: beqz a3, .LBB61_243
; CHECK-RV32-NEXT: j .LBB61_756
; CHECK-RV32-NEXT: .LBB61_243: # %else906
-; CHECK-RV32-NEXT: andi a2, a4, 16
-; CHECK-RV32-NEXT: beqz a2, .LBB61_244
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: beqz a3, .LBB61_244
; CHECK-RV32-NEXT: j .LBB61_757
; CHECK-RV32-NEXT: .LBB61_244: # %else910
-; CHECK-RV32-NEXT: andi a2, a4, 32
-; CHECK-RV32-NEXT: beqz a2, .LBB61_245
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: beqz a3, .LBB61_245
; CHECK-RV32-NEXT: j .LBB61_758
; CHECK-RV32-NEXT: .LBB61_245: # %else914
-; CHECK-RV32-NEXT: andi a2, a4, 64
-; CHECK-RV32-NEXT: beqz a2, .LBB61_246
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: beqz a3, .LBB61_246
; CHECK-RV32-NEXT: j .LBB61_759
; CHECK-RV32-NEXT: .LBB61_246: # %else918
-; CHECK-RV32-NEXT: andi a2, a4, 128
-; CHECK-RV32-NEXT: beqz a2, .LBB61_247
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: beqz a3, .LBB61_247
; CHECK-RV32-NEXT: j .LBB61_760
; CHECK-RV32-NEXT: .LBB61_247: # %else922
-; CHECK-RV32-NEXT: andi a2, a4, 256
-; CHECK-RV32-NEXT: beqz a2, .LBB61_248
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: beqz a3, .LBB61_248
; CHECK-RV32-NEXT: j .LBB61_761
; CHECK-RV32-NEXT: .LBB61_248: # %else926
-; CHECK-RV32-NEXT: andi a2, a4, 512
-; CHECK-RV32-NEXT: beqz a2, .LBB61_249
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: beqz a3, .LBB61_249
; CHECK-RV32-NEXT: j .LBB61_762
; CHECK-RV32-NEXT: .LBB61_249: # %else930
-; CHECK-RV32-NEXT: andi a2, a4, 1024
-; CHECK-RV32-NEXT: beqz a2, .LBB61_250
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: beqz a3, .LBB61_250
; CHECK-RV32-NEXT: j .LBB61_763
; CHECK-RV32-NEXT: .LBB61_250: # %else934
-; CHECK-RV32-NEXT: slli a2, a4, 20
-; CHECK-RV32-NEXT: bgez a2, .LBB61_251
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bgez a3, .LBB61_251
; CHECK-RV32-NEXT: j .LBB61_764
; CHECK-RV32-NEXT: .LBB61_251: # %else938
-; CHECK-RV32-NEXT: slli a2, a4, 19
-; CHECK-RV32-NEXT: bgez a2, .LBB61_252
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bgez a3, .LBB61_252
; CHECK-RV32-NEXT: j .LBB61_765
; CHECK-RV32-NEXT: .LBB61_252: # %else942
-; CHECK-RV32-NEXT: slli a2, a4, 18
-; CHECK-RV32-NEXT: bgez a2, .LBB61_253
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bgez a3, .LBB61_253
; CHECK-RV32-NEXT: j .LBB61_766
; CHECK-RV32-NEXT: .LBB61_253: # %else946
-; CHECK-RV32-NEXT: slli a2, a4, 17
-; CHECK-RV32-NEXT: bgez a2, .LBB61_254
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bgez a3, .LBB61_254
; CHECK-RV32-NEXT: j .LBB61_767
; CHECK-RV32-NEXT: .LBB61_254: # %else950
-; CHECK-RV32-NEXT: slli a2, a4, 16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_255
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_255
; CHECK-RV32-NEXT: j .LBB61_768
; CHECK-RV32-NEXT: .LBB61_255: # %else954
-; CHECK-RV32-NEXT: slli a2, a4, 15
-; CHECK-RV32-NEXT: bgez a2, .LBB61_256
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bgez a3, .LBB61_256
; CHECK-RV32-NEXT: j .LBB61_769
; CHECK-RV32-NEXT: .LBB61_256: # %else958
-; CHECK-RV32-NEXT: slli a2, a4, 14
-; CHECK-RV32-NEXT: bgez a2, .LBB61_257
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bgez a3, .LBB61_257
; CHECK-RV32-NEXT: j .LBB61_770
; CHECK-RV32-NEXT: .LBB61_257: # %else962
-; CHECK-RV32-NEXT: slli a2, a4, 13
-; CHECK-RV32-NEXT: bgez a2, .LBB61_258
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bgez a3, .LBB61_258
; CHECK-RV32-NEXT: j .LBB61_771
; CHECK-RV32-NEXT: .LBB61_258: # %else966
-; CHECK-RV32-NEXT: slli a2, a4, 12
-; CHECK-RV32-NEXT: bgez a2, .LBB61_259
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bgez a3, .LBB61_259
; CHECK-RV32-NEXT: j .LBB61_772
; CHECK-RV32-NEXT: .LBB61_259: # %else970
-; CHECK-RV32-NEXT: slli a2, a4, 11
-; CHECK-RV32-NEXT: bgez a2, .LBB61_260
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bgez a3, .LBB61_260
; CHECK-RV32-NEXT: j .LBB61_773
; CHECK-RV32-NEXT: .LBB61_260: # %else974
-; CHECK-RV32-NEXT: slli a2, a4, 10
-; CHECK-RV32-NEXT: bgez a2, .LBB61_261
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bgez a3, .LBB61_261
; CHECK-RV32-NEXT: j .LBB61_774
; CHECK-RV32-NEXT: .LBB61_261: # %else978
-; CHECK-RV32-NEXT: slli a2, a4, 9
-; CHECK-RV32-NEXT: bgez a2, .LBB61_262
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bgez a3, .LBB61_262
; CHECK-RV32-NEXT: j .LBB61_775
; CHECK-RV32-NEXT: .LBB61_262: # %else982
-; CHECK-RV32-NEXT: slli a2, a4, 8
-; CHECK-RV32-NEXT: bgez a2, .LBB61_263
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bgez a3, .LBB61_263
; CHECK-RV32-NEXT: j .LBB61_776
; CHECK-RV32-NEXT: .LBB61_263: # %else986
-; CHECK-RV32-NEXT: slli a2, a4, 7
-; CHECK-RV32-NEXT: bgez a2, .LBB61_264
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bgez a3, .LBB61_264
; CHECK-RV32-NEXT: j .LBB61_777
; CHECK-RV32-NEXT: .LBB61_264: # %else990
-; CHECK-RV32-NEXT: slli a2, a4, 6
-; CHECK-RV32-NEXT: bgez a2, .LBB61_265
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bgez a3, .LBB61_265
; CHECK-RV32-NEXT: j .LBB61_778
; CHECK-RV32-NEXT: .LBB61_265: # %else994
-; CHECK-RV32-NEXT: slli a2, a4, 5
-; CHECK-RV32-NEXT: bgez a2, .LBB61_266
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bgez a3, .LBB61_266
; CHECK-RV32-NEXT: j .LBB61_779
; CHECK-RV32-NEXT: .LBB61_266: # %else998
-; CHECK-RV32-NEXT: slli a2, a4, 4
-; CHECK-RV32-NEXT: bgez a2, .LBB61_267
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bgez a3, .LBB61_267
; CHECK-RV32-NEXT: j .LBB61_780
; CHECK-RV32-NEXT: .LBB61_267: # %else1002
-; CHECK-RV32-NEXT: slli a2, a4, 3
-; CHECK-RV32-NEXT: bgez a2, .LBB61_268
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bgez a3, .LBB61_268
; CHECK-RV32-NEXT: j .LBB61_781
; CHECK-RV32-NEXT: .LBB61_268: # %else1006
-; CHECK-RV32-NEXT: slli a2, a4, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_270
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_270
; CHECK-RV32-NEXT: .LBB61_269: # %cond.load1009
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 254
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 254
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 253
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 253
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_270: # %else1010
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v16, v0, 4
-; CHECK-RV32-NEXT: slli a2, a4, 1
-; CHECK-RV32-NEXT: bgez a2, .LBB61_272
+; CHECK-RV32-NEXT: slli a3, a2, 1
+; CHECK-RV32-NEXT: bgez a3, .LBB61_272
; CHECK-RV32-NEXT: # %bb.271: # %cond.load1013
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
-; CHECK-RV32-NEXT: li a2, 255
-; CHECK-RV32-NEXT: li a3, 254
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a3
+; CHECK-RV32-NEXT: li a3, 255
+; CHECK-RV32-NEXT: li a4, 254
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
; CHECK-RV32-NEXT: vmv4r.v v8, v20
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_272: # %else1014
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a2, v16
-; CHECK-RV32-NEXT: bgez a4, .LBB61_273
+; CHECK-RV32-NEXT: vmv.x.s a3, v16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_273
; CHECK-RV32-NEXT: j .LBB61_782
; CHECK-RV32-NEXT: .LBB61_273: # %else1018
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: beqz a3, .LBB61_274
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: beqz a2, .LBB61_274
; CHECK-RV32-NEXT: j .LBB61_783
; CHECK-RV32-NEXT: .LBB61_274: # %else1022
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: beqz a3, .LBB61_275
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: beqz a2, .LBB61_275
; CHECK-RV32-NEXT: j .LBB61_784
; CHECK-RV32-NEXT: .LBB61_275: # %else1026
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: beqz a3, .LBB61_276
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: beqz a2, .LBB61_276
; CHECK-RV32-NEXT: j .LBB61_785
; CHECK-RV32-NEXT: .LBB61_276: # %else1030
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: beqz a3, .LBB61_277
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: beqz a2, .LBB61_277
; CHECK-RV32-NEXT: j .LBB61_786
; CHECK-RV32-NEXT: .LBB61_277: # %else1034
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: beqz a3, .LBB61_278
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: beqz a2, .LBB61_278
; CHECK-RV32-NEXT: j .LBB61_787
; CHECK-RV32-NEXT: .LBB61_278: # %else1038
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: beqz a3, .LBB61_279
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: beqz a2, .LBB61_279
; CHECK-RV32-NEXT: j .LBB61_788
; CHECK-RV32-NEXT: .LBB61_279: # %else1042
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: beqz a3, .LBB61_280
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: beqz a2, .LBB61_280
; CHECK-RV32-NEXT: j .LBB61_789
; CHECK-RV32-NEXT: .LBB61_280: # %else1046
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: beqz a3, .LBB61_281
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: beqz a2, .LBB61_281
; CHECK-RV32-NEXT: j .LBB61_790
; CHECK-RV32-NEXT: .LBB61_281: # %else1050
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: beqz a3, .LBB61_282
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: beqz a2, .LBB61_282
; CHECK-RV32-NEXT: j .LBB61_791
; CHECK-RV32-NEXT: .LBB61_282: # %else1054
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: beqz a3, .LBB61_283
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: beqz a2, .LBB61_283
; CHECK-RV32-NEXT: j .LBB61_792
; CHECK-RV32-NEXT: .LBB61_283: # %else1058
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: beqz a3, .LBB61_284
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: beqz a2, .LBB61_284
; CHECK-RV32-NEXT: j .LBB61_793
; CHECK-RV32-NEXT: .LBB61_284: # %else1062
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bgez a3, .LBB61_285
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bgez a2, .LBB61_285
; CHECK-RV32-NEXT: j .LBB61_794
; CHECK-RV32-NEXT: .LBB61_285: # %else1066
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bgez a3, .LBB61_286
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bgez a2, .LBB61_286
; CHECK-RV32-NEXT: j .LBB61_795
; CHECK-RV32-NEXT: .LBB61_286: # %else1070
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bgez a3, .LBB61_287
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bgez a2, .LBB61_287
; CHECK-RV32-NEXT: j .LBB61_796
; CHECK-RV32-NEXT: .LBB61_287: # %else1074
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bgez a3, .LBB61_288
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bgez a2, .LBB61_288
; CHECK-RV32-NEXT: j .LBB61_797
; CHECK-RV32-NEXT: .LBB61_288: # %else1078
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_289
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_289
; CHECK-RV32-NEXT: j .LBB61_798
; CHECK-RV32-NEXT: .LBB61_289: # %else1082
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bgez a3, .LBB61_290
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bgez a2, .LBB61_290
; CHECK-RV32-NEXT: j .LBB61_799
; CHECK-RV32-NEXT: .LBB61_290: # %else1086
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bgez a3, .LBB61_291
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bgez a2, .LBB61_291
; CHECK-RV32-NEXT: j .LBB61_800
; CHECK-RV32-NEXT: .LBB61_291: # %else1090
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bgez a3, .LBB61_292
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bgez a2, .LBB61_292
; CHECK-RV32-NEXT: j .LBB61_801
; CHECK-RV32-NEXT: .LBB61_292: # %else1094
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bgez a3, .LBB61_293
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bgez a2, .LBB61_293
; CHECK-RV32-NEXT: j .LBB61_802
; CHECK-RV32-NEXT: .LBB61_293: # %else1098
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bgez a3, .LBB61_294
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bgez a2, .LBB61_294
; CHECK-RV32-NEXT: j .LBB61_803
; CHECK-RV32-NEXT: .LBB61_294: # %else1102
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bgez a3, .LBB61_295
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bgez a2, .LBB61_295
; CHECK-RV32-NEXT: j .LBB61_804
; CHECK-RV32-NEXT: .LBB61_295: # %else1106
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bgez a3, .LBB61_296
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bgez a2, .LBB61_296
; CHECK-RV32-NEXT: j .LBB61_805
; CHECK-RV32-NEXT: .LBB61_296: # %else1110
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bgez a3, .LBB61_297
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bgez a2, .LBB61_297
; CHECK-RV32-NEXT: j .LBB61_806
; CHECK-RV32-NEXT: .LBB61_297: # %else1114
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bgez a3, .LBB61_298
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bgez a2, .LBB61_298
; CHECK-RV32-NEXT: j .LBB61_807
; CHECK-RV32-NEXT: .LBB61_298: # %else1118
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bgez a3, .LBB61_299
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bgez a2, .LBB61_299
; CHECK-RV32-NEXT: j .LBB61_808
; CHECK-RV32-NEXT: .LBB61_299: # %else1122
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bgez a3, .LBB61_300
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bgez a2, .LBB61_300
; CHECK-RV32-NEXT: j .LBB61_809
; CHECK-RV32-NEXT: .LBB61_300: # %else1126
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bgez a3, .LBB61_301
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bgez a2, .LBB61_301
; CHECK-RV32-NEXT: j .LBB61_810
; CHECK-RV32-NEXT: .LBB61_301: # %else1130
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bgez a3, .LBB61_302
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bgez a2, .LBB61_302
; CHECK-RV32-NEXT: j .LBB61_811
; CHECK-RV32-NEXT: .LBB61_302: # %else1134
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_304
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_304
; CHECK-RV32-NEXT: .LBB61_303: # %cond.load1137
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 286
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 285
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 285
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_304: # %else1138
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsrl.vx v16, v16, a1
-; CHECK-RV32-NEXT: slli a3, a2, 1
-; CHECK-RV32-NEXT: bgez a3, .LBB61_306
+; CHECK-RV32-NEXT: slli a2, a3, 1
+; CHECK-RV32-NEXT: bgez a2, .LBB61_306
; CHECK-RV32-NEXT: # %bb.305: # %cond.load1141
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 287
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 287
; CHECK-RV32-NEXT: li a4, 286
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_306: # %else1142
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a3, v16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_307
+; CHECK-RV32-NEXT: vmv.x.s a2, v16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_307
; CHECK-RV32-NEXT: j .LBB61_812
; CHECK-RV32-NEXT: .LBB61_307: # %else1146
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: beqz a2, .LBB61_308
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: beqz a3, .LBB61_308
; CHECK-RV32-NEXT: j .LBB61_813
; CHECK-RV32-NEXT: .LBB61_308: # %else1150
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: beqz a2, .LBB61_309
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: beqz a3, .LBB61_309
; CHECK-RV32-NEXT: j .LBB61_814
; CHECK-RV32-NEXT: .LBB61_309: # %else1154
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: beqz a2, .LBB61_310
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: beqz a3, .LBB61_310
; CHECK-RV32-NEXT: j .LBB61_815
; CHECK-RV32-NEXT: .LBB61_310: # %else1158
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: beqz a2, .LBB61_311
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: beqz a3, .LBB61_311
; CHECK-RV32-NEXT: j .LBB61_816
; CHECK-RV32-NEXT: .LBB61_311: # %else1162
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: beqz a2, .LBB61_312
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: beqz a3, .LBB61_312
; CHECK-RV32-NEXT: j .LBB61_817
; CHECK-RV32-NEXT: .LBB61_312: # %else1166
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: beqz a2, .LBB61_313
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: beqz a3, .LBB61_313
; CHECK-RV32-NEXT: j .LBB61_818
; CHECK-RV32-NEXT: .LBB61_313: # %else1170
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: beqz a2, .LBB61_314
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: beqz a3, .LBB61_314
; CHECK-RV32-NEXT: j .LBB61_819
; CHECK-RV32-NEXT: .LBB61_314: # %else1174
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: beqz a2, .LBB61_315
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: beqz a3, .LBB61_315
; CHECK-RV32-NEXT: j .LBB61_820
; CHECK-RV32-NEXT: .LBB61_315: # %else1178
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: beqz a2, .LBB61_316
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: beqz a3, .LBB61_316
; CHECK-RV32-NEXT: j .LBB61_821
; CHECK-RV32-NEXT: .LBB61_316: # %else1182
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: beqz a2, .LBB61_317
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: beqz a3, .LBB61_317
; CHECK-RV32-NEXT: j .LBB61_822
; CHECK-RV32-NEXT: .LBB61_317: # %else1186
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: beqz a2, .LBB61_318
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: beqz a3, .LBB61_318
; CHECK-RV32-NEXT: j .LBB61_823
; CHECK-RV32-NEXT: .LBB61_318: # %else1190
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bgez a2, .LBB61_319
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bgez a3, .LBB61_319
; CHECK-RV32-NEXT: j .LBB61_824
; CHECK-RV32-NEXT: .LBB61_319: # %else1194
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bgez a2, .LBB61_320
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bgez a3, .LBB61_320
; CHECK-RV32-NEXT: j .LBB61_825
; CHECK-RV32-NEXT: .LBB61_320: # %else1198
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bgez a2, .LBB61_321
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bgez a3, .LBB61_321
; CHECK-RV32-NEXT: j .LBB61_826
; CHECK-RV32-NEXT: .LBB61_321: # %else1202
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bgez a2, .LBB61_322
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bgez a3, .LBB61_322
; CHECK-RV32-NEXT: j .LBB61_827
; CHECK-RV32-NEXT: .LBB61_322: # %else1206
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_323
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_323
; CHECK-RV32-NEXT: j .LBB61_828
; CHECK-RV32-NEXT: .LBB61_323: # %else1210
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bgez a2, .LBB61_324
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bgez a3, .LBB61_324
; CHECK-RV32-NEXT: j .LBB61_829
; CHECK-RV32-NEXT: .LBB61_324: # %else1214
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bgez a2, .LBB61_325
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bgez a3, .LBB61_325
; CHECK-RV32-NEXT: j .LBB61_830
; CHECK-RV32-NEXT: .LBB61_325: # %else1218
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bgez a2, .LBB61_326
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bgez a3, .LBB61_326
; CHECK-RV32-NEXT: j .LBB61_831
; CHECK-RV32-NEXT: .LBB61_326: # %else1222
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bgez a2, .LBB61_327
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bgez a3, .LBB61_327
; CHECK-RV32-NEXT: j .LBB61_832
; CHECK-RV32-NEXT: .LBB61_327: # %else1226
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bgez a2, .LBB61_328
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bgez a3, .LBB61_328
; CHECK-RV32-NEXT: j .LBB61_833
; CHECK-RV32-NEXT: .LBB61_328: # %else1230
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bgez a2, .LBB61_329
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bgez a3, .LBB61_329
; CHECK-RV32-NEXT: j .LBB61_834
; CHECK-RV32-NEXT: .LBB61_329: # %else1234
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bgez a2, .LBB61_330
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bgez a3, .LBB61_330
; CHECK-RV32-NEXT: j .LBB61_835
; CHECK-RV32-NEXT: .LBB61_330: # %else1238
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bgez a2, .LBB61_331
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bgez a3, .LBB61_331
; CHECK-RV32-NEXT: j .LBB61_836
; CHECK-RV32-NEXT: .LBB61_331: # %else1242
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bgez a2, .LBB61_332
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bgez a3, .LBB61_332
; CHECK-RV32-NEXT: j .LBB61_837
; CHECK-RV32-NEXT: .LBB61_332: # %else1246
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bgez a2, .LBB61_333
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bgez a3, .LBB61_333
; CHECK-RV32-NEXT: j .LBB61_838
; CHECK-RV32-NEXT: .LBB61_333: # %else1250
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bgez a2, .LBB61_334
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bgez a3, .LBB61_334
; CHECK-RV32-NEXT: j .LBB61_839
; CHECK-RV32-NEXT: .LBB61_334: # %else1254
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bgez a2, .LBB61_335
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bgez a3, .LBB61_335
; CHECK-RV32-NEXT: j .LBB61_840
; CHECK-RV32-NEXT: .LBB61_335: # %else1258
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bgez a2, .LBB61_336
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bgez a3, .LBB61_336
; CHECK-RV32-NEXT: j .LBB61_841
; CHECK-RV32-NEXT: .LBB61_336: # %else1262
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_338
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_338
; CHECK-RV32-NEXT: .LBB61_337: # %cond.load1265
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 318
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 317
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 317
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_338: # %else1266
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 5
-; CHECK-RV32-NEXT: slli a2, a3, 1
-; CHECK-RV32-NEXT: bgez a2, .LBB61_340
+; CHECK-RV32-NEXT: vslidedown.vi v16, v0, 5
+; CHECK-RV32-NEXT: slli a3, a2, 1
+; CHECK-RV32-NEXT: bgez a3, .LBB61_340
; CHECK-RV32-NEXT: # %bb.339: # %cond.load1269
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 319
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a3
+; CHECK-RV32-NEXT: li a3, 319
; CHECK-RV32-NEXT: li a4, 318
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_340: # %else1270
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a2, v24
-; CHECK-RV32-NEXT: bgez a3, .LBB61_341
+; CHECK-RV32-NEXT: vmv.x.s a3, v16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_341
; CHECK-RV32-NEXT: j .LBB61_842
; CHECK-RV32-NEXT: .LBB61_341: # %else1274
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: beqz a3, .LBB61_342
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: beqz a2, .LBB61_342
; CHECK-RV32-NEXT: j .LBB61_843
; CHECK-RV32-NEXT: .LBB61_342: # %else1278
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: beqz a3, .LBB61_343
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: beqz a2, .LBB61_343
; CHECK-RV32-NEXT: j .LBB61_844
; CHECK-RV32-NEXT: .LBB61_343: # %else1282
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: beqz a3, .LBB61_344
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: beqz a2, .LBB61_344
; CHECK-RV32-NEXT: j .LBB61_845
; CHECK-RV32-NEXT: .LBB61_344: # %else1286
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: beqz a3, .LBB61_345
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: beqz a2, .LBB61_345
; CHECK-RV32-NEXT: j .LBB61_846
; CHECK-RV32-NEXT: .LBB61_345: # %else1290
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: beqz a3, .LBB61_346
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: beqz a2, .LBB61_346
; CHECK-RV32-NEXT: j .LBB61_847
; CHECK-RV32-NEXT: .LBB61_346: # %else1294
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: beqz a3, .LBB61_347
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: beqz a2, .LBB61_347
; CHECK-RV32-NEXT: j .LBB61_848
; CHECK-RV32-NEXT: .LBB61_347: # %else1298
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: beqz a3, .LBB61_348
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: beqz a2, .LBB61_348
; CHECK-RV32-NEXT: j .LBB61_849
; CHECK-RV32-NEXT: .LBB61_348: # %else1302
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: beqz a3, .LBB61_349
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: beqz a2, .LBB61_349
; CHECK-RV32-NEXT: j .LBB61_850
; CHECK-RV32-NEXT: .LBB61_349: # %else1306
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: beqz a3, .LBB61_350
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: beqz a2, .LBB61_350
; CHECK-RV32-NEXT: j .LBB61_851
; CHECK-RV32-NEXT: .LBB61_350: # %else1310
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: beqz a3, .LBB61_351
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: beqz a2, .LBB61_351
; CHECK-RV32-NEXT: j .LBB61_852
; CHECK-RV32-NEXT: .LBB61_351: # %else1314
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: beqz a3, .LBB61_352
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: beqz a2, .LBB61_352
; CHECK-RV32-NEXT: j .LBB61_853
; CHECK-RV32-NEXT: .LBB61_352: # %else1318
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bgez a3, .LBB61_353
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bgez a2, .LBB61_353
; CHECK-RV32-NEXT: j .LBB61_854
; CHECK-RV32-NEXT: .LBB61_353: # %else1322
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bgez a3, .LBB61_354
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bgez a2, .LBB61_354
; CHECK-RV32-NEXT: j .LBB61_855
; CHECK-RV32-NEXT: .LBB61_354: # %else1326
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bgez a3, .LBB61_355
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bgez a2, .LBB61_355
; CHECK-RV32-NEXT: j .LBB61_856
; CHECK-RV32-NEXT: .LBB61_355: # %else1330
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bgez a3, .LBB61_356
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bgez a2, .LBB61_356
; CHECK-RV32-NEXT: j .LBB61_857
; CHECK-RV32-NEXT: .LBB61_356: # %else1334
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_357
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_357
; CHECK-RV32-NEXT: j .LBB61_858
; CHECK-RV32-NEXT: .LBB61_357: # %else1338
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bgez a3, .LBB61_358
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bgez a2, .LBB61_358
; CHECK-RV32-NEXT: j .LBB61_859
; CHECK-RV32-NEXT: .LBB61_358: # %else1342
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bgez a3, .LBB61_359
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bgez a2, .LBB61_359
; CHECK-RV32-NEXT: j .LBB61_860
; CHECK-RV32-NEXT: .LBB61_359: # %else1346
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bgez a3, .LBB61_360
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bgez a2, .LBB61_360
; CHECK-RV32-NEXT: j .LBB61_861
; CHECK-RV32-NEXT: .LBB61_360: # %else1350
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bgez a3, .LBB61_361
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bgez a2, .LBB61_361
; CHECK-RV32-NEXT: j .LBB61_862
; CHECK-RV32-NEXT: .LBB61_361: # %else1354
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bgez a3, .LBB61_362
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bgez a2, .LBB61_362
; CHECK-RV32-NEXT: j .LBB61_863
; CHECK-RV32-NEXT: .LBB61_362: # %else1358
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bgez a3, .LBB61_363
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bgez a2, .LBB61_363
; CHECK-RV32-NEXT: j .LBB61_864
; CHECK-RV32-NEXT: .LBB61_363: # %else1362
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bgez a3, .LBB61_364
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bgez a2, .LBB61_364
; CHECK-RV32-NEXT: j .LBB61_865
; CHECK-RV32-NEXT: .LBB61_364: # %else1366
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bgez a3, .LBB61_365
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bgez a2, .LBB61_365
; CHECK-RV32-NEXT: j .LBB61_866
; CHECK-RV32-NEXT: .LBB61_365: # %else1370
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bgez a3, .LBB61_366
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bgez a2, .LBB61_366
; CHECK-RV32-NEXT: j .LBB61_867
; CHECK-RV32-NEXT: .LBB61_366: # %else1374
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bgez a3, .LBB61_367
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bgez a2, .LBB61_367
; CHECK-RV32-NEXT: j .LBB61_868
; CHECK-RV32-NEXT: .LBB61_367: # %else1378
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bgez a3, .LBB61_368
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bgez a2, .LBB61_368
; CHECK-RV32-NEXT: j .LBB61_869
; CHECK-RV32-NEXT: .LBB61_368: # %else1382
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bgez a3, .LBB61_369
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bgez a2, .LBB61_369
; CHECK-RV32-NEXT: j .LBB61_870
; CHECK-RV32-NEXT: .LBB61_369: # %else1386
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bgez a3, .LBB61_370
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bgez a2, .LBB61_370
; CHECK-RV32-NEXT: j .LBB61_871
; CHECK-RV32-NEXT: .LBB61_370: # %else1390
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_372
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_372
; CHECK-RV32-NEXT: .LBB61_371: # %cond.load1393
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 350
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 349
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 349
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_372: # %else1394
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v24, v24, a1
-; CHECK-RV32-NEXT: slli a3, a2, 1
-; CHECK-RV32-NEXT: bgez a3, .LBB61_374
+; CHECK-RV32-NEXT: vsrl.vx v16, v16, a1
+; CHECK-RV32-NEXT: slli a2, a3, 1
+; CHECK-RV32-NEXT: bgez a2, .LBB61_374
; CHECK-RV32-NEXT: # %bb.373: # %cond.load1397
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 351
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 351
; CHECK-RV32-NEXT: li a4, 350
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_374: # %else1398
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a3, v24
-; CHECK-RV32-NEXT: bgez a2, .LBB61_375
+; CHECK-RV32-NEXT: vmv.x.s a2, v16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_375
; CHECK-RV32-NEXT: j .LBB61_872
; CHECK-RV32-NEXT: .LBB61_375: # %else1402
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: beqz a2, .LBB61_376
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: beqz a3, .LBB61_376
; CHECK-RV32-NEXT: j .LBB61_873
; CHECK-RV32-NEXT: .LBB61_376: # %else1406
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: beqz a2, .LBB61_377
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: beqz a3, .LBB61_377
; CHECK-RV32-NEXT: j .LBB61_874
; CHECK-RV32-NEXT: .LBB61_377: # %else1410
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: beqz a2, .LBB61_378
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: beqz a3, .LBB61_378
; CHECK-RV32-NEXT: j .LBB61_875
; CHECK-RV32-NEXT: .LBB61_378: # %else1414
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: beqz a2, .LBB61_379
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: beqz a3, .LBB61_379
; CHECK-RV32-NEXT: j .LBB61_876
; CHECK-RV32-NEXT: .LBB61_379: # %else1418
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: beqz a2, .LBB61_380
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: beqz a3, .LBB61_380
; CHECK-RV32-NEXT: j .LBB61_877
; CHECK-RV32-NEXT: .LBB61_380: # %else1422
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: beqz a2, .LBB61_381
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: beqz a3, .LBB61_381
; CHECK-RV32-NEXT: j .LBB61_878
; CHECK-RV32-NEXT: .LBB61_381: # %else1426
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: beqz a2, .LBB61_382
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: beqz a3, .LBB61_382
; CHECK-RV32-NEXT: j .LBB61_879
; CHECK-RV32-NEXT: .LBB61_382: # %else1430
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: beqz a2, .LBB61_383
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: beqz a3, .LBB61_383
; CHECK-RV32-NEXT: j .LBB61_880
; CHECK-RV32-NEXT: .LBB61_383: # %else1434
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: beqz a2, .LBB61_384
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: beqz a3, .LBB61_384
; CHECK-RV32-NEXT: j .LBB61_881
; CHECK-RV32-NEXT: .LBB61_384: # %else1438
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: beqz a2, .LBB61_385
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: beqz a3, .LBB61_385
; CHECK-RV32-NEXT: j .LBB61_882
; CHECK-RV32-NEXT: .LBB61_385: # %else1442
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: beqz a2, .LBB61_386
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: beqz a3, .LBB61_386
; CHECK-RV32-NEXT: j .LBB61_883
; CHECK-RV32-NEXT: .LBB61_386: # %else1446
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bgez a2, .LBB61_387
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bgez a3, .LBB61_387
; CHECK-RV32-NEXT: j .LBB61_884
; CHECK-RV32-NEXT: .LBB61_387: # %else1450
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bgez a2, .LBB61_388
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bgez a3, .LBB61_388
; CHECK-RV32-NEXT: j .LBB61_885
; CHECK-RV32-NEXT: .LBB61_388: # %else1454
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bgez a2, .LBB61_389
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bgez a3, .LBB61_389
; CHECK-RV32-NEXT: j .LBB61_886
; CHECK-RV32-NEXT: .LBB61_389: # %else1458
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bgez a2, .LBB61_390
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bgez a3, .LBB61_390
; CHECK-RV32-NEXT: j .LBB61_887
; CHECK-RV32-NEXT: .LBB61_390: # %else1462
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_391
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_391
; CHECK-RV32-NEXT: j .LBB61_888
; CHECK-RV32-NEXT: .LBB61_391: # %else1466
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bgez a2, .LBB61_392
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bgez a3, .LBB61_392
; CHECK-RV32-NEXT: j .LBB61_889
; CHECK-RV32-NEXT: .LBB61_392: # %else1470
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bgez a2, .LBB61_393
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bgez a3, .LBB61_393
; CHECK-RV32-NEXT: j .LBB61_890
; CHECK-RV32-NEXT: .LBB61_393: # %else1474
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bgez a2, .LBB61_394
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bgez a3, .LBB61_394
; CHECK-RV32-NEXT: j .LBB61_891
; CHECK-RV32-NEXT: .LBB61_394: # %else1478
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bgez a2, .LBB61_395
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bgez a3, .LBB61_395
; CHECK-RV32-NEXT: j .LBB61_892
; CHECK-RV32-NEXT: .LBB61_395: # %else1482
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bgez a2, .LBB61_396
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bgez a3, .LBB61_396
; CHECK-RV32-NEXT: j .LBB61_893
; CHECK-RV32-NEXT: .LBB61_396: # %else1486
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bgez a2, .LBB61_397
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bgez a3, .LBB61_397
; CHECK-RV32-NEXT: j .LBB61_894
; CHECK-RV32-NEXT: .LBB61_397: # %else1490
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bgez a2, .LBB61_398
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bgez a3, .LBB61_398
; CHECK-RV32-NEXT: j .LBB61_895
; CHECK-RV32-NEXT: .LBB61_398: # %else1494
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bgez a2, .LBB61_399
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bgez a3, .LBB61_399
; CHECK-RV32-NEXT: j .LBB61_896
; CHECK-RV32-NEXT: .LBB61_399: # %else1498
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bgez a2, .LBB61_400
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bgez a3, .LBB61_400
; CHECK-RV32-NEXT: j .LBB61_897
; CHECK-RV32-NEXT: .LBB61_400: # %else1502
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bgez a2, .LBB61_401
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bgez a3, .LBB61_401
; CHECK-RV32-NEXT: j .LBB61_898
; CHECK-RV32-NEXT: .LBB61_401: # %else1506
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bgez a2, .LBB61_402
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bgez a3, .LBB61_402
; CHECK-RV32-NEXT: j .LBB61_899
; CHECK-RV32-NEXT: .LBB61_402: # %else1510
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bgez a2, .LBB61_403
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bgez a3, .LBB61_403
; CHECK-RV32-NEXT: j .LBB61_900
; CHECK-RV32-NEXT: .LBB61_403: # %else1514
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bgez a2, .LBB61_404
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bgez a3, .LBB61_404
; CHECK-RV32-NEXT: j .LBB61_901
; CHECK-RV32-NEXT: .LBB61_404: # %else1518
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_406
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_406
; CHECK-RV32-NEXT: .LBB61_405: # %cond.load1521
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 382
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 381
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 381
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_406: # %else1522
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v16, v0, 6
-; CHECK-RV32-NEXT: slli a2, a3, 1
-; CHECK-RV32-NEXT: bgez a2, .LBB61_408
+; CHECK-RV32-NEXT: slli a3, a2, 1
+; CHECK-RV32-NEXT: bgez a3, .LBB61_408
; CHECK-RV32-NEXT: # %bb.407: # %cond.load1525
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
-; CHECK-RV32-NEXT: li a2, 383
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a3
+; CHECK-RV32-NEXT: li a3, 383
; CHECK-RV32-NEXT: li a4, 382
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_408: # %else1526
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a2, v16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_409
+; CHECK-RV32-NEXT: vmv.x.s a3, v16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_409
; CHECK-RV32-NEXT: j .LBB61_902
; CHECK-RV32-NEXT: .LBB61_409: # %else1530
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: beqz a3, .LBB61_410
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: beqz a2, .LBB61_410
; CHECK-RV32-NEXT: j .LBB61_903
; CHECK-RV32-NEXT: .LBB61_410: # %else1534
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: beqz a3, .LBB61_411
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: beqz a2, .LBB61_411
; CHECK-RV32-NEXT: j .LBB61_904
; CHECK-RV32-NEXT: .LBB61_411: # %else1538
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: beqz a3, .LBB61_412
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: beqz a2, .LBB61_412
; CHECK-RV32-NEXT: j .LBB61_905
; CHECK-RV32-NEXT: .LBB61_412: # %else1542
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: beqz a3, .LBB61_413
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: beqz a2, .LBB61_413
; CHECK-RV32-NEXT: j .LBB61_906
; CHECK-RV32-NEXT: .LBB61_413: # %else1546
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: beqz a3, .LBB61_414
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: beqz a2, .LBB61_414
; CHECK-RV32-NEXT: j .LBB61_907
; CHECK-RV32-NEXT: .LBB61_414: # %else1550
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: beqz a3, .LBB61_415
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: beqz a2, .LBB61_415
; CHECK-RV32-NEXT: j .LBB61_908
; CHECK-RV32-NEXT: .LBB61_415: # %else1554
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: beqz a3, .LBB61_416
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: beqz a2, .LBB61_416
; CHECK-RV32-NEXT: j .LBB61_909
; CHECK-RV32-NEXT: .LBB61_416: # %else1558
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: beqz a3, .LBB61_417
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: beqz a2, .LBB61_417
; CHECK-RV32-NEXT: j .LBB61_910
; CHECK-RV32-NEXT: .LBB61_417: # %else1562
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: beqz a3, .LBB61_418
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: beqz a2, .LBB61_418
; CHECK-RV32-NEXT: j .LBB61_911
; CHECK-RV32-NEXT: .LBB61_418: # %else1566
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: beqz a3, .LBB61_419
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: beqz a2, .LBB61_419
; CHECK-RV32-NEXT: j .LBB61_912
; CHECK-RV32-NEXT: .LBB61_419: # %else1570
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: beqz a3, .LBB61_420
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: beqz a2, .LBB61_420
; CHECK-RV32-NEXT: j .LBB61_913
; CHECK-RV32-NEXT: .LBB61_420: # %else1574
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bgez a3, .LBB61_421
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bgez a2, .LBB61_421
; CHECK-RV32-NEXT: j .LBB61_914
; CHECK-RV32-NEXT: .LBB61_421: # %else1578
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bgez a3, .LBB61_422
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bgez a2, .LBB61_422
; CHECK-RV32-NEXT: j .LBB61_915
; CHECK-RV32-NEXT: .LBB61_422: # %else1582
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bgez a3, .LBB61_423
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bgez a2, .LBB61_423
; CHECK-RV32-NEXT: j .LBB61_916
; CHECK-RV32-NEXT: .LBB61_423: # %else1586
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bgez a3, .LBB61_424
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bgez a2, .LBB61_424
; CHECK-RV32-NEXT: j .LBB61_917
; CHECK-RV32-NEXT: .LBB61_424: # %else1590
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_425
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_425
; CHECK-RV32-NEXT: j .LBB61_918
; CHECK-RV32-NEXT: .LBB61_425: # %else1594
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bgez a3, .LBB61_426
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bgez a2, .LBB61_426
; CHECK-RV32-NEXT: j .LBB61_919
; CHECK-RV32-NEXT: .LBB61_426: # %else1598
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bgez a3, .LBB61_427
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bgez a2, .LBB61_427
; CHECK-RV32-NEXT: j .LBB61_920
; CHECK-RV32-NEXT: .LBB61_427: # %else1602
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bgez a3, .LBB61_428
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bgez a2, .LBB61_428
; CHECK-RV32-NEXT: j .LBB61_921
; CHECK-RV32-NEXT: .LBB61_428: # %else1606
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bgez a3, .LBB61_429
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bgez a2, .LBB61_429
; CHECK-RV32-NEXT: j .LBB61_922
; CHECK-RV32-NEXT: .LBB61_429: # %else1610
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bgez a3, .LBB61_430
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bgez a2, .LBB61_430
; CHECK-RV32-NEXT: j .LBB61_923
; CHECK-RV32-NEXT: .LBB61_430: # %else1614
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bgez a3, .LBB61_431
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bgez a2, .LBB61_431
; CHECK-RV32-NEXT: j .LBB61_924
; CHECK-RV32-NEXT: .LBB61_431: # %else1618
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bgez a3, .LBB61_432
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bgez a2, .LBB61_432
; CHECK-RV32-NEXT: j .LBB61_925
; CHECK-RV32-NEXT: .LBB61_432: # %else1622
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bgez a3, .LBB61_433
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bgez a2, .LBB61_433
; CHECK-RV32-NEXT: j .LBB61_926
; CHECK-RV32-NEXT: .LBB61_433: # %else1626
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bgez a3, .LBB61_434
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bgez a2, .LBB61_434
; CHECK-RV32-NEXT: j .LBB61_927
; CHECK-RV32-NEXT: .LBB61_434: # %else1630
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bgez a3, .LBB61_435
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bgez a2, .LBB61_435
; CHECK-RV32-NEXT: j .LBB61_928
; CHECK-RV32-NEXT: .LBB61_435: # %else1634
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bgez a3, .LBB61_436
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bgez a2, .LBB61_436
; CHECK-RV32-NEXT: j .LBB61_929
; CHECK-RV32-NEXT: .LBB61_436: # %else1638
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bgez a3, .LBB61_437
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bgez a2, .LBB61_437
; CHECK-RV32-NEXT: j .LBB61_930
; CHECK-RV32-NEXT: .LBB61_437: # %else1642
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bgez a3, .LBB61_438
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bgez a2, .LBB61_438
; CHECK-RV32-NEXT: j .LBB61_931
; CHECK-RV32-NEXT: .LBB61_438: # %else1646
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_440
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_440
; CHECK-RV32-NEXT: .LBB61_439: # %cond.load1649
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 414
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 413
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 413
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_440: # %else1650
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsrl.vx v16, v16, a1
-; CHECK-RV32-NEXT: slli a3, a2, 1
-; CHECK-RV32-NEXT: bgez a3, .LBB61_442
+; CHECK-RV32-NEXT: slli a2, a3, 1
+; CHECK-RV32-NEXT: bgez a2, .LBB61_442
; CHECK-RV32-NEXT: # %bb.441: # %cond.load1653
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 415
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 415
; CHECK-RV32-NEXT: li a4, 414
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_442: # %else1654
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a3, v16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_443
+; CHECK-RV32-NEXT: vmv.x.s a2, v16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_443
; CHECK-RV32-NEXT: j .LBB61_932
; CHECK-RV32-NEXT: .LBB61_443: # %else1658
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: beqz a2, .LBB61_444
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: beqz a3, .LBB61_444
; CHECK-RV32-NEXT: j .LBB61_933
; CHECK-RV32-NEXT: .LBB61_444: # %else1662
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: beqz a2, .LBB61_445
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: beqz a3, .LBB61_445
; CHECK-RV32-NEXT: j .LBB61_934
; CHECK-RV32-NEXT: .LBB61_445: # %else1666
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: beqz a2, .LBB61_446
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: beqz a3, .LBB61_446
; CHECK-RV32-NEXT: j .LBB61_935
; CHECK-RV32-NEXT: .LBB61_446: # %else1670
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: beqz a2, .LBB61_447
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: beqz a3, .LBB61_447
; CHECK-RV32-NEXT: j .LBB61_936
; CHECK-RV32-NEXT: .LBB61_447: # %else1674
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: beqz a2, .LBB61_448
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: beqz a3, .LBB61_448
; CHECK-RV32-NEXT: j .LBB61_937
; CHECK-RV32-NEXT: .LBB61_448: # %else1678
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: beqz a2, .LBB61_449
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: beqz a3, .LBB61_449
; CHECK-RV32-NEXT: j .LBB61_938
; CHECK-RV32-NEXT: .LBB61_449: # %else1682
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: beqz a2, .LBB61_450
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: beqz a3, .LBB61_450
; CHECK-RV32-NEXT: j .LBB61_939
; CHECK-RV32-NEXT: .LBB61_450: # %else1686
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: beqz a2, .LBB61_451
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: beqz a3, .LBB61_451
; CHECK-RV32-NEXT: j .LBB61_940
; CHECK-RV32-NEXT: .LBB61_451: # %else1690
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: beqz a2, .LBB61_452
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: beqz a3, .LBB61_452
; CHECK-RV32-NEXT: j .LBB61_941
; CHECK-RV32-NEXT: .LBB61_452: # %else1694
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: beqz a2, .LBB61_453
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: beqz a3, .LBB61_453
; CHECK-RV32-NEXT: j .LBB61_942
; CHECK-RV32-NEXT: .LBB61_453: # %else1698
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: beqz a2, .LBB61_454
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: beqz a3, .LBB61_454
; CHECK-RV32-NEXT: j .LBB61_943
; CHECK-RV32-NEXT: .LBB61_454: # %else1702
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bgez a2, .LBB61_455
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bgez a3, .LBB61_455
; CHECK-RV32-NEXT: j .LBB61_944
; CHECK-RV32-NEXT: .LBB61_455: # %else1706
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bgez a2, .LBB61_456
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bgez a3, .LBB61_456
; CHECK-RV32-NEXT: j .LBB61_945
; CHECK-RV32-NEXT: .LBB61_456: # %else1710
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bgez a2, .LBB61_457
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bgez a3, .LBB61_457
; CHECK-RV32-NEXT: j .LBB61_946
; CHECK-RV32-NEXT: .LBB61_457: # %else1714
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bgez a2, .LBB61_458
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bgez a3, .LBB61_458
; CHECK-RV32-NEXT: j .LBB61_947
; CHECK-RV32-NEXT: .LBB61_458: # %else1718
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_459
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bgez a3, .LBB61_459
; CHECK-RV32-NEXT: j .LBB61_948
; CHECK-RV32-NEXT: .LBB61_459: # %else1722
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bgez a2, .LBB61_460
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bgez a3, .LBB61_460
; CHECK-RV32-NEXT: j .LBB61_949
; CHECK-RV32-NEXT: .LBB61_460: # %else1726
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bgez a2, .LBB61_461
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bgez a3, .LBB61_461
; CHECK-RV32-NEXT: j .LBB61_950
; CHECK-RV32-NEXT: .LBB61_461: # %else1730
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bgez a2, .LBB61_462
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bgez a3, .LBB61_462
; CHECK-RV32-NEXT: j .LBB61_951
; CHECK-RV32-NEXT: .LBB61_462: # %else1734
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bgez a2, .LBB61_463
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bgez a3, .LBB61_463
; CHECK-RV32-NEXT: j .LBB61_952
; CHECK-RV32-NEXT: .LBB61_463: # %else1738
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bgez a2, .LBB61_464
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bgez a3, .LBB61_464
; CHECK-RV32-NEXT: j .LBB61_953
; CHECK-RV32-NEXT: .LBB61_464: # %else1742
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bgez a2, .LBB61_465
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bgez a3, .LBB61_465
; CHECK-RV32-NEXT: j .LBB61_954
; CHECK-RV32-NEXT: .LBB61_465: # %else1746
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bgez a2, .LBB61_466
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bgez a3, .LBB61_466
; CHECK-RV32-NEXT: j .LBB61_955
; CHECK-RV32-NEXT: .LBB61_466: # %else1750
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bgez a2, .LBB61_467
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bgez a3, .LBB61_467
; CHECK-RV32-NEXT: j .LBB61_956
; CHECK-RV32-NEXT: .LBB61_467: # %else1754
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bgez a2, .LBB61_468
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bgez a3, .LBB61_468
; CHECK-RV32-NEXT: j .LBB61_957
; CHECK-RV32-NEXT: .LBB61_468: # %else1758
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bgez a2, .LBB61_469
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bgez a3, .LBB61_469
; CHECK-RV32-NEXT: j .LBB61_958
; CHECK-RV32-NEXT: .LBB61_469: # %else1762
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bgez a2, .LBB61_470
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bgez a3, .LBB61_470
; CHECK-RV32-NEXT: j .LBB61_959
; CHECK-RV32-NEXT: .LBB61_470: # %else1766
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bgez a2, .LBB61_471
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bgez a3, .LBB61_471
; CHECK-RV32-NEXT: j .LBB61_960
; CHECK-RV32-NEXT: .LBB61_471: # %else1770
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bgez a2, .LBB61_472
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bgez a3, .LBB61_472
; CHECK-RV32-NEXT: j .LBB61_961
; CHECK-RV32-NEXT: .LBB61_472: # %else1774
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_474
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_474
; CHECK-RV32-NEXT: .LBB61_473: # %cond.load1777
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 446
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 445
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 445
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_474: # %else1778
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v16, v0, 7
-; CHECK-RV32-NEXT: slli a2, a3, 1
-; CHECK-RV32-NEXT: bgez a2, .LBB61_476
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 7
+; CHECK-RV32-NEXT: slli a3, a2, 1
+; CHECK-RV32-NEXT: bgez a3, .LBB61_476
; CHECK-RV32-NEXT: # %bb.475: # %cond.load1781
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
-; CHECK-RV32-NEXT: li a2, 447
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 447
; CHECK-RV32-NEXT: li a4, 446
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_476: # %else1782
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a2, v16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_477
+; CHECK-RV32-NEXT: vmv.x.s a3, v24
+; CHECK-RV32-NEXT: bgez a2, .LBB61_477
; CHECK-RV32-NEXT: j .LBB61_962
; CHECK-RV32-NEXT: .LBB61_477: # %else1786
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: beqz a3, .LBB61_478
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: beqz a2, .LBB61_478
; CHECK-RV32-NEXT: j .LBB61_963
; CHECK-RV32-NEXT: .LBB61_478: # %else1790
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: beqz a3, .LBB61_479
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: beqz a2, .LBB61_479
; CHECK-RV32-NEXT: j .LBB61_964
; CHECK-RV32-NEXT: .LBB61_479: # %else1794
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: beqz a3, .LBB61_480
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: beqz a2, .LBB61_480
; CHECK-RV32-NEXT: j .LBB61_965
; CHECK-RV32-NEXT: .LBB61_480: # %else1798
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: beqz a3, .LBB61_481
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: beqz a2, .LBB61_481
; CHECK-RV32-NEXT: j .LBB61_966
; CHECK-RV32-NEXT: .LBB61_481: # %else1802
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: beqz a3, .LBB61_482
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: beqz a2, .LBB61_482
; CHECK-RV32-NEXT: j .LBB61_967
; CHECK-RV32-NEXT: .LBB61_482: # %else1806
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: beqz a3, .LBB61_483
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: beqz a2, .LBB61_483
; CHECK-RV32-NEXT: j .LBB61_968
; CHECK-RV32-NEXT: .LBB61_483: # %else1810
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: beqz a3, .LBB61_484
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: beqz a2, .LBB61_484
; CHECK-RV32-NEXT: j .LBB61_969
; CHECK-RV32-NEXT: .LBB61_484: # %else1814
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: beqz a3, .LBB61_485
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: beqz a2, .LBB61_485
; CHECK-RV32-NEXT: j .LBB61_970
; CHECK-RV32-NEXT: .LBB61_485: # %else1818
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: beqz a3, .LBB61_486
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: beqz a2, .LBB61_486
; CHECK-RV32-NEXT: j .LBB61_971
; CHECK-RV32-NEXT: .LBB61_486: # %else1822
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: beqz a3, .LBB61_487
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: beqz a2, .LBB61_487
; CHECK-RV32-NEXT: j .LBB61_972
; CHECK-RV32-NEXT: .LBB61_487: # %else1826
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: beqz a3, .LBB61_488
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: beqz a2, .LBB61_488
; CHECK-RV32-NEXT: j .LBB61_973
; CHECK-RV32-NEXT: .LBB61_488: # %else1830
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bgez a3, .LBB61_489
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bgez a2, .LBB61_489
; CHECK-RV32-NEXT: j .LBB61_974
; CHECK-RV32-NEXT: .LBB61_489: # %else1834
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bgez a3, .LBB61_490
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bgez a2, .LBB61_490
; CHECK-RV32-NEXT: j .LBB61_975
; CHECK-RV32-NEXT: .LBB61_490: # %else1838
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bgez a3, .LBB61_491
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bgez a2, .LBB61_491
; CHECK-RV32-NEXT: j .LBB61_976
; CHECK-RV32-NEXT: .LBB61_491: # %else1842
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bgez a3, .LBB61_492
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bgez a2, .LBB61_492
; CHECK-RV32-NEXT: j .LBB61_977
; CHECK-RV32-NEXT: .LBB61_492: # %else1846
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bgez a3, .LBB61_493
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bgez a2, .LBB61_493
; CHECK-RV32-NEXT: j .LBB61_978
; CHECK-RV32-NEXT: .LBB61_493: # %else1850
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bgez a3, .LBB61_494
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bgez a2, .LBB61_494
; CHECK-RV32-NEXT: j .LBB61_979
; CHECK-RV32-NEXT: .LBB61_494: # %else1854
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bgez a3, .LBB61_495
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bgez a2, .LBB61_495
; CHECK-RV32-NEXT: j .LBB61_980
; CHECK-RV32-NEXT: .LBB61_495: # %else1858
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bgez a3, .LBB61_496
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bgez a2, .LBB61_496
; CHECK-RV32-NEXT: j .LBB61_981
; CHECK-RV32-NEXT: .LBB61_496: # %else1862
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bgez a3, .LBB61_497
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bgez a2, .LBB61_497
; CHECK-RV32-NEXT: j .LBB61_982
; CHECK-RV32-NEXT: .LBB61_497: # %else1866
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bgez a3, .LBB61_498
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bgez a2, .LBB61_498
; CHECK-RV32-NEXT: j .LBB61_983
; CHECK-RV32-NEXT: .LBB61_498: # %else1870
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bgez a3, .LBB61_499
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bgez a2, .LBB61_499
; CHECK-RV32-NEXT: j .LBB61_984
; CHECK-RV32-NEXT: .LBB61_499: # %else1874
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bgez a3, .LBB61_500
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bgez a2, .LBB61_500
; CHECK-RV32-NEXT: j .LBB61_985
; CHECK-RV32-NEXT: .LBB61_500: # %else1878
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bgez a3, .LBB61_501
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bgez a2, .LBB61_501
; CHECK-RV32-NEXT: j .LBB61_986
; CHECK-RV32-NEXT: .LBB61_501: # %else1882
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bgez a3, .LBB61_502
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bgez a2, .LBB61_502
; CHECK-RV32-NEXT: j .LBB61_987
; CHECK-RV32-NEXT: .LBB61_502: # %else1886
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bgez a3, .LBB61_503
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bgez a2, .LBB61_503
; CHECK-RV32-NEXT: j .LBB61_988
; CHECK-RV32-NEXT: .LBB61_503: # %else1890
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bgez a3, .LBB61_504
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bgez a2, .LBB61_504
; CHECK-RV32-NEXT: j .LBB61_989
; CHECK-RV32-NEXT: .LBB61_504: # %else1894
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bgez a3, .LBB61_505
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bgez a2, .LBB61_505
; CHECK-RV32-NEXT: j .LBB61_990
; CHECK-RV32-NEXT: .LBB61_505: # %else1898
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bgez a3, .LBB61_506
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bgez a2, .LBB61_506
; CHECK-RV32-NEXT: j .LBB61_991
; CHECK-RV32-NEXT: .LBB61_506: # %else1902
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_508
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_508
; CHECK-RV32-NEXT: .LBB61_507: # %cond.load1905
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 478
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 477
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 477
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_508: # %else1906
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v16, v16, a1
-; CHECK-RV32-NEXT: slli a1, a2, 1
+; CHECK-RV32-NEXT: vsrl.vx v16, v24, a1
+; CHECK-RV32-NEXT: slli a1, a3, 1
; CHECK-RV32-NEXT: bgez a1, .LBB61_510
; CHECK-RV32-NEXT: # %bb.509: # %cond.load1909
; CHECK-RV32-NEXT: lbu a1, 0(a0)
; CHECK-RV32-NEXT: vmv.s.x v24, a1
; CHECK-RV32-NEXT: li a1, 479
-; CHECK-RV32-NEXT: li a3, 478
+; CHECK-RV32-NEXT: li a2, 478
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_510: # %else1910
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a1, v16
-; CHECK-RV32-NEXT: bgez a2, .LBB61_511
+; CHECK-RV32-NEXT: bgez a3, .LBB61_511
; CHECK-RV32-NEXT: j .LBB61_992
; CHECK-RV32-NEXT: .LBB61_511: # %else1914
; CHECK-RV32-NEXT: andi a2, a1, 1
@@ -6479,2720 +6479,2720 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: .LBB61_1031: # %cond.load877
; CHECK-RV32-NEXT: j .LBB61_236
; CHECK-RV32-NEXT: .LBB61_752: # %cond.load889
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 224
-; CHECK-RV32-NEXT: li a3, 223
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 224
+; CHECK-RV32-NEXT: li a4, 223
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a4
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 1
-; CHECK-RV32-NEXT: bnez a2, .LBB61_753
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: bnez a3, .LBB61_753
; CHECK-RV32-NEXT: j .LBB61_240
; CHECK-RV32-NEXT: .LBB61_753: # %cond.load893
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 225
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 225
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 224
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 224
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 2
-; CHECK-RV32-NEXT: bnez a2, .LBB61_754
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: bnez a3, .LBB61_754
; CHECK-RV32-NEXT: j .LBB61_241
; CHECK-RV32-NEXT: .LBB61_754: # %cond.load897
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 226
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 226
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 225
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 225
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 4
-; CHECK-RV32-NEXT: bnez a2, .LBB61_755
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: bnez a3, .LBB61_755
; CHECK-RV32-NEXT: j .LBB61_242
; CHECK-RV32-NEXT: .LBB61_755: # %cond.load901
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 227
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 227
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 226
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 226
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 8
-; CHECK-RV32-NEXT: bnez a2, .LBB61_756
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: bnez a3, .LBB61_756
; CHECK-RV32-NEXT: j .LBB61_243
; CHECK-RV32-NEXT: .LBB61_756: # %cond.load905
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 228
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 228
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 227
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 227
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 16
-; CHECK-RV32-NEXT: bnez a2, .LBB61_757
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: bnez a3, .LBB61_757
; CHECK-RV32-NEXT: j .LBB61_244
; CHECK-RV32-NEXT: .LBB61_757: # %cond.load909
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 229
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 229
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 228
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 228
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 32
-; CHECK-RV32-NEXT: bnez a2, .LBB61_758
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: bnez a3, .LBB61_758
; CHECK-RV32-NEXT: j .LBB61_245
; CHECK-RV32-NEXT: .LBB61_758: # %cond.load913
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 230
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 230
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 229
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 229
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 64
-; CHECK-RV32-NEXT: bnez a2, .LBB61_759
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: bnez a3, .LBB61_759
; CHECK-RV32-NEXT: j .LBB61_246
; CHECK-RV32-NEXT: .LBB61_759: # %cond.load917
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 231
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 231
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 230
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 230
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 128
-; CHECK-RV32-NEXT: bnez a2, .LBB61_760
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: bnez a3, .LBB61_760
; CHECK-RV32-NEXT: j .LBB61_247
; CHECK-RV32-NEXT: .LBB61_760: # %cond.load921
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 232
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 232
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 231
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 231
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 256
-; CHECK-RV32-NEXT: bnez a2, .LBB61_761
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: bnez a3, .LBB61_761
; CHECK-RV32-NEXT: j .LBB61_248
; CHECK-RV32-NEXT: .LBB61_761: # %cond.load925
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 233
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 233
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 232
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 232
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 512
-; CHECK-RV32-NEXT: bnez a2, .LBB61_762
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: bnez a3, .LBB61_762
; CHECK-RV32-NEXT: j .LBB61_249
; CHECK-RV32-NEXT: .LBB61_762: # %cond.load929
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 234
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 234
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 233
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 233
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a4, 1024
-; CHECK-RV32-NEXT: bnez a2, .LBB61_763
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: bnez a3, .LBB61_763
; CHECK-RV32-NEXT: j .LBB61_250
; CHECK-RV32-NEXT: .LBB61_763: # %cond.load933
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 235
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 235
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 234
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 234
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 20
-; CHECK-RV32-NEXT: bltz a2, .LBB61_764
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bltz a3, .LBB61_764
; CHECK-RV32-NEXT: j .LBB61_251
; CHECK-RV32-NEXT: .LBB61_764: # %cond.load937
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 236
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 236
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 235
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 235
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 19
-; CHECK-RV32-NEXT: bltz a2, .LBB61_765
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bltz a3, .LBB61_765
; CHECK-RV32-NEXT: j .LBB61_252
; CHECK-RV32-NEXT: .LBB61_765: # %cond.load941
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 237
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 237
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 236
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 236
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 18
-; CHECK-RV32-NEXT: bltz a2, .LBB61_766
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bltz a3, .LBB61_766
; CHECK-RV32-NEXT: j .LBB61_253
; CHECK-RV32-NEXT: .LBB61_766: # %cond.load945
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 238
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 238
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 237
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 237
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 17
-; CHECK-RV32-NEXT: bltz a2, .LBB61_767
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bltz a3, .LBB61_767
; CHECK-RV32-NEXT: j .LBB61_254
; CHECK-RV32-NEXT: .LBB61_767: # %cond.load949
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 239
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 239
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 238
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 238
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 16
-; CHECK-RV32-NEXT: bltz a2, .LBB61_768
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bltz a3, .LBB61_768
; CHECK-RV32-NEXT: j .LBB61_255
; CHECK-RV32-NEXT: .LBB61_768: # %cond.load953
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 240
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 240
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 239
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 239
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 15
-; CHECK-RV32-NEXT: bltz a2, .LBB61_769
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bltz a3, .LBB61_769
; CHECK-RV32-NEXT: j .LBB61_256
; CHECK-RV32-NEXT: .LBB61_769: # %cond.load957
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 241
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 241
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 240
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 240
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 14
-; CHECK-RV32-NEXT: bltz a2, .LBB61_770
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bltz a3, .LBB61_770
; CHECK-RV32-NEXT: j .LBB61_257
; CHECK-RV32-NEXT: .LBB61_770: # %cond.load961
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 242
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 242
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 241
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 241
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 13
-; CHECK-RV32-NEXT: bltz a2, .LBB61_771
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bltz a3, .LBB61_771
; CHECK-RV32-NEXT: j .LBB61_258
; CHECK-RV32-NEXT: .LBB61_771: # %cond.load965
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 243
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 243
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 242
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
-; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 12
-; CHECK-RV32-NEXT: bltz a2, .LBB61_772
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 242
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
+; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: addi a0, a0, 1
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bltz a3, .LBB61_772
; CHECK-RV32-NEXT: j .LBB61_259
; CHECK-RV32-NEXT: .LBB61_772: # %cond.load969
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 244
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 244
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 243
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 243
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 11
-; CHECK-RV32-NEXT: bltz a2, .LBB61_773
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bltz a3, .LBB61_773
; CHECK-RV32-NEXT: j .LBB61_260
; CHECK-RV32-NEXT: .LBB61_773: # %cond.load973
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 245
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 245
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 244
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 244
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 10
-; CHECK-RV32-NEXT: bltz a2, .LBB61_774
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bltz a3, .LBB61_774
; CHECK-RV32-NEXT: j .LBB61_261
; CHECK-RV32-NEXT: .LBB61_774: # %cond.load977
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 246
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 246
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 245
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 245
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 9
-; CHECK-RV32-NEXT: bltz a2, .LBB61_775
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bltz a3, .LBB61_775
; CHECK-RV32-NEXT: j .LBB61_262
; CHECK-RV32-NEXT: .LBB61_775: # %cond.load981
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 247
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 247
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 246
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 246
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 8
-; CHECK-RV32-NEXT: bltz a2, .LBB61_776
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bltz a3, .LBB61_776
; CHECK-RV32-NEXT: j .LBB61_263
; CHECK-RV32-NEXT: .LBB61_776: # %cond.load985
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 248
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 248
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 247
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 247
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 7
-; CHECK-RV32-NEXT: bltz a2, .LBB61_777
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bltz a3, .LBB61_777
; CHECK-RV32-NEXT: j .LBB61_264
; CHECK-RV32-NEXT: .LBB61_777: # %cond.load989
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 249
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 249
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 248
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 248
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 6
-; CHECK-RV32-NEXT: bltz a2, .LBB61_778
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bltz a3, .LBB61_778
; CHECK-RV32-NEXT: j .LBB61_265
; CHECK-RV32-NEXT: .LBB61_778: # %cond.load993
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 250
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 250
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 249
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 249
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 5
-; CHECK-RV32-NEXT: bltz a2, .LBB61_779
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bltz a3, .LBB61_779
; CHECK-RV32-NEXT: j .LBB61_266
; CHECK-RV32-NEXT: .LBB61_779: # %cond.load997
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 251
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 251
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 250
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 250
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 4
-; CHECK-RV32-NEXT: bltz a2, .LBB61_780
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bltz a3, .LBB61_780
; CHECK-RV32-NEXT: j .LBB61_267
; CHECK-RV32-NEXT: .LBB61_780: # %cond.load1001
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 252
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 252
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 251
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 251
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 3
-; CHECK-RV32-NEXT: bltz a2, .LBB61_781
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bltz a3, .LBB61_781
; CHECK-RV32-NEXT: j .LBB61_268
; CHECK-RV32-NEXT: .LBB61_781: # %cond.load1005
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: li a3, 253
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: li a4, 253
+; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
-; CHECK-RV32-NEXT: li a2, 252
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: li a3, 252
+; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV32-NEXT: vmv4r.v v8, v16
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a4, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_1032
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_1032
; CHECK-RV32-NEXT: j .LBB61_269
; CHECK-RV32-NEXT: .LBB61_1032: # %cond.load1005
; CHECK-RV32-NEXT: j .LBB61_270
; CHECK-RV32-NEXT: .LBB61_782: # %cond.load1017
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 256
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 256
; CHECK-RV32-NEXT: li a4, 255
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
; CHECK-RV32-NEXT: vmv4r.v v8, v20
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: bnez a3, .LBB61_783
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: bnez a2, .LBB61_783
; CHECK-RV32-NEXT: j .LBB61_274
; CHECK-RV32-NEXT: .LBB61_783: # %cond.load1021
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 257
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 256
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 256
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: bnez a3, .LBB61_784
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: bnez a2, .LBB61_784
; CHECK-RV32-NEXT: j .LBB61_275
; CHECK-RV32-NEXT: .LBB61_784: # %cond.load1025
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 258
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 257
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 257
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: bnez a3, .LBB61_785
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: bnez a2, .LBB61_785
; CHECK-RV32-NEXT: j .LBB61_276
; CHECK-RV32-NEXT: .LBB61_785: # %cond.load1029
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 259
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 258
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 258
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: bnez a3, .LBB61_786
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: bnez a2, .LBB61_786
; CHECK-RV32-NEXT: j .LBB61_277
; CHECK-RV32-NEXT: .LBB61_786: # %cond.load1033
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 260
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 259
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 259
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: bnez a3, .LBB61_787
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: bnez a2, .LBB61_787
; CHECK-RV32-NEXT: j .LBB61_278
; CHECK-RV32-NEXT: .LBB61_787: # %cond.load1037
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 261
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 260
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 260
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: bnez a3, .LBB61_788
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: bnez a2, .LBB61_788
; CHECK-RV32-NEXT: j .LBB61_279
; CHECK-RV32-NEXT: .LBB61_788: # %cond.load1041
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 262
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 261
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 261
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: bnez a3, .LBB61_789
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: bnez a2, .LBB61_789
; CHECK-RV32-NEXT: j .LBB61_280
; CHECK-RV32-NEXT: .LBB61_789: # %cond.load1045
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 263
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 262
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 262
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: bnez a3, .LBB61_790
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: bnez a2, .LBB61_790
; CHECK-RV32-NEXT: j .LBB61_281
; CHECK-RV32-NEXT: .LBB61_790: # %cond.load1049
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 264
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 263
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 263
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: bnez a3, .LBB61_791
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: bnez a2, .LBB61_791
; CHECK-RV32-NEXT: j .LBB61_282
; CHECK-RV32-NEXT: .LBB61_791: # %cond.load1053
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 265
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 264
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 264
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: bnez a3, .LBB61_792
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: bnez a2, .LBB61_792
; CHECK-RV32-NEXT: j .LBB61_283
; CHECK-RV32-NEXT: .LBB61_792: # %cond.load1057
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 266
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 265
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 265
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: bnez a3, .LBB61_793
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: bnez a2, .LBB61_793
; CHECK-RV32-NEXT: j .LBB61_284
; CHECK-RV32-NEXT: .LBB61_793: # %cond.load1061
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 267
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 266
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 266
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bltz a3, .LBB61_794
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bltz a2, .LBB61_794
; CHECK-RV32-NEXT: j .LBB61_285
; CHECK-RV32-NEXT: .LBB61_794: # %cond.load1065
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 268
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 267
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 267
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bltz a3, .LBB61_795
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bltz a2, .LBB61_795
; CHECK-RV32-NEXT: j .LBB61_286
; CHECK-RV32-NEXT: .LBB61_795: # %cond.load1069
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 269
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 268
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 268
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bltz a3, .LBB61_796
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bltz a2, .LBB61_796
; CHECK-RV32-NEXT: j .LBB61_287
; CHECK-RV32-NEXT: .LBB61_796: # %cond.load1073
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 270
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 269
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 269
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bltz a3, .LBB61_797
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bltz a2, .LBB61_797
; CHECK-RV32-NEXT: j .LBB61_288
; CHECK-RV32-NEXT: .LBB61_797: # %cond.load1077
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 271
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 270
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 270
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bltz a3, .LBB61_798
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bltz a2, .LBB61_798
; CHECK-RV32-NEXT: j .LBB61_289
; CHECK-RV32-NEXT: .LBB61_798: # %cond.load1081
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 272
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 271
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 271
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bltz a3, .LBB61_799
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bltz a2, .LBB61_799
; CHECK-RV32-NEXT: j .LBB61_290
; CHECK-RV32-NEXT: .LBB61_799: # %cond.load1085
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 273
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 272
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 272
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bltz a3, .LBB61_800
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bltz a2, .LBB61_800
; CHECK-RV32-NEXT: j .LBB61_291
; CHECK-RV32-NEXT: .LBB61_800: # %cond.load1089
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 274
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 273
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 273
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bltz a3, .LBB61_801
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bltz a2, .LBB61_801
; CHECK-RV32-NEXT: j .LBB61_292
; CHECK-RV32-NEXT: .LBB61_801: # %cond.load1093
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 275
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 274
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 274
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bltz a3, .LBB61_802
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bltz a2, .LBB61_802
; CHECK-RV32-NEXT: j .LBB61_293
; CHECK-RV32-NEXT: .LBB61_802: # %cond.load1097
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 276
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 275
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 275
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bltz a3, .LBB61_803
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bltz a2, .LBB61_803
; CHECK-RV32-NEXT: j .LBB61_294
; CHECK-RV32-NEXT: .LBB61_803: # %cond.load1101
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 277
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 276
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 276
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bltz a3, .LBB61_804
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bltz a2, .LBB61_804
; CHECK-RV32-NEXT: j .LBB61_295
; CHECK-RV32-NEXT: .LBB61_804: # %cond.load1105
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 278
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 277
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 277
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bltz a3, .LBB61_805
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bltz a2, .LBB61_805
; CHECK-RV32-NEXT: j .LBB61_296
; CHECK-RV32-NEXT: .LBB61_805: # %cond.load1109
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 279
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 278
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 278
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bltz a3, .LBB61_806
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bltz a2, .LBB61_806
; CHECK-RV32-NEXT: j .LBB61_297
; CHECK-RV32-NEXT: .LBB61_806: # %cond.load1113
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 280
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 279
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 279
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bltz a3, .LBB61_807
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bltz a2, .LBB61_807
; CHECK-RV32-NEXT: j .LBB61_298
; CHECK-RV32-NEXT: .LBB61_807: # %cond.load1117
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 281
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 280
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 280
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bltz a3, .LBB61_808
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bltz a2, .LBB61_808
; CHECK-RV32-NEXT: j .LBB61_299
; CHECK-RV32-NEXT: .LBB61_808: # %cond.load1121
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 282
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 281
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 281
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bltz a3, .LBB61_809
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bltz a2, .LBB61_809
; CHECK-RV32-NEXT: j .LBB61_300
; CHECK-RV32-NEXT: .LBB61_809: # %cond.load1125
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 283
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 282
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 282
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bltz a3, .LBB61_810
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bltz a2, .LBB61_810
; CHECK-RV32-NEXT: j .LBB61_301
; CHECK-RV32-NEXT: .LBB61_810: # %cond.load1129
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 284
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 283
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 283
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bltz a3, .LBB61_811
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bltz a2, .LBB61_811
; CHECK-RV32-NEXT: j .LBB61_302
; CHECK-RV32-NEXT: .LBB61_811: # %cond.load1133
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 285
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 284
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 284
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_1033
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_1033
; CHECK-RV32-NEXT: j .LBB61_303
; CHECK-RV32-NEXT: .LBB61_1033: # %cond.load1133
; CHECK-RV32-NEXT: j .LBB61_304
; CHECK-RV32-NEXT: .LBB61_812: # %cond.load1145
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 288
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 288
; CHECK-RV32-NEXT: li a4, 287
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: bnez a2, .LBB61_813
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: bnez a3, .LBB61_813
; CHECK-RV32-NEXT: j .LBB61_308
; CHECK-RV32-NEXT: .LBB61_813: # %cond.load1149
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 289
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 288
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 288
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: bnez a2, .LBB61_814
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: bnez a3, .LBB61_814
; CHECK-RV32-NEXT: j .LBB61_309
; CHECK-RV32-NEXT: .LBB61_814: # %cond.load1153
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 290
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 289
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 289
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: bnez a2, .LBB61_815
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: bnez a3, .LBB61_815
; CHECK-RV32-NEXT: j .LBB61_310
; CHECK-RV32-NEXT: .LBB61_815: # %cond.load1157
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 291
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 290
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 290
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: bnez a2, .LBB61_816
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: bnez a3, .LBB61_816
; CHECK-RV32-NEXT: j .LBB61_311
; CHECK-RV32-NEXT: .LBB61_816: # %cond.load1161
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 292
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 291
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 291
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: bnez a2, .LBB61_817
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: bnez a3, .LBB61_817
; CHECK-RV32-NEXT: j .LBB61_312
; CHECK-RV32-NEXT: .LBB61_817: # %cond.load1165
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 293
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 292
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 292
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: bnez a2, .LBB61_818
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: bnez a3, .LBB61_818
; CHECK-RV32-NEXT: j .LBB61_313
; CHECK-RV32-NEXT: .LBB61_818: # %cond.load1169
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 294
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 293
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 293
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: bnez a2, .LBB61_819
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: bnez a3, .LBB61_819
; CHECK-RV32-NEXT: j .LBB61_314
; CHECK-RV32-NEXT: .LBB61_819: # %cond.load1173
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 295
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 294
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 294
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: bnez a2, .LBB61_820
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: bnez a3, .LBB61_820
; CHECK-RV32-NEXT: j .LBB61_315
; CHECK-RV32-NEXT: .LBB61_820: # %cond.load1177
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 296
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 295
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 295
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: bnez a2, .LBB61_821
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: bnez a3, .LBB61_821
; CHECK-RV32-NEXT: j .LBB61_316
; CHECK-RV32-NEXT: .LBB61_821: # %cond.load1181
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 297
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 296
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 296
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: bnez a2, .LBB61_822
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: bnez a3, .LBB61_822
; CHECK-RV32-NEXT: j .LBB61_317
; CHECK-RV32-NEXT: .LBB61_822: # %cond.load1185
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 298
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 297
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 297
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: bnez a2, .LBB61_823
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: bnez a3, .LBB61_823
; CHECK-RV32-NEXT: j .LBB61_318
; CHECK-RV32-NEXT: .LBB61_823: # %cond.load1189
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 299
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 298
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 298
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bltz a2, .LBB61_824
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bltz a3, .LBB61_824
; CHECK-RV32-NEXT: j .LBB61_319
; CHECK-RV32-NEXT: .LBB61_824: # %cond.load1193
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 300
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 299
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 299
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bltz a2, .LBB61_825
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bltz a3, .LBB61_825
; CHECK-RV32-NEXT: j .LBB61_320
; CHECK-RV32-NEXT: .LBB61_825: # %cond.load1197
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 301
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 300
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 300
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bltz a2, .LBB61_826
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bltz a3, .LBB61_826
; CHECK-RV32-NEXT: j .LBB61_321
; CHECK-RV32-NEXT: .LBB61_826: # %cond.load1201
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 302
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 301
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 301
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bltz a2, .LBB61_827
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bltz a3, .LBB61_827
; CHECK-RV32-NEXT: j .LBB61_322
; CHECK-RV32-NEXT: .LBB61_827: # %cond.load1205
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 303
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 302
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 302
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bltz a2, .LBB61_828
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bltz a3, .LBB61_828
; CHECK-RV32-NEXT: j .LBB61_323
; CHECK-RV32-NEXT: .LBB61_828: # %cond.load1209
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 304
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 303
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 303
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bltz a2, .LBB61_829
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bltz a3, .LBB61_829
; CHECK-RV32-NEXT: j .LBB61_324
; CHECK-RV32-NEXT: .LBB61_829: # %cond.load1213
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 305
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 304
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 304
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bltz a2, .LBB61_830
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bltz a3, .LBB61_830
; CHECK-RV32-NEXT: j .LBB61_325
; CHECK-RV32-NEXT: .LBB61_830: # %cond.load1217
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 306
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 305
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 305
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bltz a2, .LBB61_831
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bltz a3, .LBB61_831
; CHECK-RV32-NEXT: j .LBB61_326
; CHECK-RV32-NEXT: .LBB61_831: # %cond.load1221
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 307
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 306
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 306
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bltz a2, .LBB61_832
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bltz a3, .LBB61_832
; CHECK-RV32-NEXT: j .LBB61_327
; CHECK-RV32-NEXT: .LBB61_832: # %cond.load1225
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 308
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 307
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 307
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bltz a2, .LBB61_833
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bltz a3, .LBB61_833
; CHECK-RV32-NEXT: j .LBB61_328
; CHECK-RV32-NEXT: .LBB61_833: # %cond.load1229
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 309
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 308
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 308
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bltz a2, .LBB61_834
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bltz a3, .LBB61_834
; CHECK-RV32-NEXT: j .LBB61_329
; CHECK-RV32-NEXT: .LBB61_834: # %cond.load1233
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 310
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 309
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 309
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bltz a2, .LBB61_835
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bltz a3, .LBB61_835
; CHECK-RV32-NEXT: j .LBB61_330
; CHECK-RV32-NEXT: .LBB61_835: # %cond.load1237
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 311
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 310
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 310
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bltz a2, .LBB61_836
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bltz a3, .LBB61_836
; CHECK-RV32-NEXT: j .LBB61_331
; CHECK-RV32-NEXT: .LBB61_836: # %cond.load1241
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 312
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 311
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 311
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bltz a2, .LBB61_837
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bltz a3, .LBB61_837
; CHECK-RV32-NEXT: j .LBB61_332
; CHECK-RV32-NEXT: .LBB61_837: # %cond.load1245
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 313
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 312
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 312
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bltz a2, .LBB61_838
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bltz a3, .LBB61_838
; CHECK-RV32-NEXT: j .LBB61_333
; CHECK-RV32-NEXT: .LBB61_838: # %cond.load1249
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 314
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 313
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 313
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bltz a2, .LBB61_839
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bltz a3, .LBB61_839
; CHECK-RV32-NEXT: j .LBB61_334
; CHECK-RV32-NEXT: .LBB61_839: # %cond.load1253
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 315
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 314
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 314
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bltz a2, .LBB61_840
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bltz a3, .LBB61_840
; CHECK-RV32-NEXT: j .LBB61_335
; CHECK-RV32-NEXT: .LBB61_840: # %cond.load1257
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 316
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 315
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 315
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bltz a2, .LBB61_841
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bltz a3, .LBB61_841
; CHECK-RV32-NEXT: j .LBB61_336
; CHECK-RV32-NEXT: .LBB61_841: # %cond.load1261
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 317
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 316
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 316
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_1034
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_1034
; CHECK-RV32-NEXT: j .LBB61_337
; CHECK-RV32-NEXT: .LBB61_1034: # %cond.load1261
; CHECK-RV32-NEXT: j .LBB61_338
; CHECK-RV32-NEXT: .LBB61_842: # %cond.load1273
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 320
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 320
; CHECK-RV32-NEXT: li a4, 319
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: bnez a3, .LBB61_843
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: bnez a2, .LBB61_843
; CHECK-RV32-NEXT: j .LBB61_342
; CHECK-RV32-NEXT: .LBB61_843: # %cond.load1277
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 321
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 320
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 320
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: bnez a3, .LBB61_844
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: bnez a2, .LBB61_844
; CHECK-RV32-NEXT: j .LBB61_343
; CHECK-RV32-NEXT: .LBB61_844: # %cond.load1281
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 322
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 321
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 321
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: bnez a3, .LBB61_845
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: bnez a2, .LBB61_845
; CHECK-RV32-NEXT: j .LBB61_344
; CHECK-RV32-NEXT: .LBB61_845: # %cond.load1285
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 323
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 322
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 322
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: bnez a3, .LBB61_846
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: bnez a2, .LBB61_846
; CHECK-RV32-NEXT: j .LBB61_345
; CHECK-RV32-NEXT: .LBB61_846: # %cond.load1289
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 324
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 323
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 323
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: bnez a3, .LBB61_847
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: bnez a2, .LBB61_847
; CHECK-RV32-NEXT: j .LBB61_346
; CHECK-RV32-NEXT: .LBB61_847: # %cond.load1293
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 325
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 324
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 324
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: bnez a3, .LBB61_848
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: bnez a2, .LBB61_848
; CHECK-RV32-NEXT: j .LBB61_347
; CHECK-RV32-NEXT: .LBB61_848: # %cond.load1297
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 326
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 325
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 325
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: bnez a3, .LBB61_849
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: bnez a2, .LBB61_849
; CHECK-RV32-NEXT: j .LBB61_348
; CHECK-RV32-NEXT: .LBB61_849: # %cond.load1301
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 327
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 326
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 326
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: bnez a3, .LBB61_850
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: bnez a2, .LBB61_850
; CHECK-RV32-NEXT: j .LBB61_349
; CHECK-RV32-NEXT: .LBB61_850: # %cond.load1305
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 328
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 327
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 327
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: bnez a3, .LBB61_851
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: bnez a2, .LBB61_851
; CHECK-RV32-NEXT: j .LBB61_350
; CHECK-RV32-NEXT: .LBB61_851: # %cond.load1309
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 329
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 328
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 328
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: bnez a3, .LBB61_852
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: bnez a2, .LBB61_852
; CHECK-RV32-NEXT: j .LBB61_351
; CHECK-RV32-NEXT: .LBB61_852: # %cond.load1313
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 330
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 329
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 329
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: bnez a3, .LBB61_853
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: bnez a2, .LBB61_853
; CHECK-RV32-NEXT: j .LBB61_352
; CHECK-RV32-NEXT: .LBB61_853: # %cond.load1317
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 331
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 330
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 330
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bltz a3, .LBB61_854
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bltz a2, .LBB61_854
; CHECK-RV32-NEXT: j .LBB61_353
; CHECK-RV32-NEXT: .LBB61_854: # %cond.load1321
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 332
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 331
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 331
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bltz a3, .LBB61_855
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bltz a2, .LBB61_855
; CHECK-RV32-NEXT: j .LBB61_354
; CHECK-RV32-NEXT: .LBB61_855: # %cond.load1325
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 333
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 332
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 332
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bltz a3, .LBB61_856
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bltz a2, .LBB61_856
; CHECK-RV32-NEXT: j .LBB61_355
; CHECK-RV32-NEXT: .LBB61_856: # %cond.load1329
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 334
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 333
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 333
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bltz a3, .LBB61_857
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bltz a2, .LBB61_857
; CHECK-RV32-NEXT: j .LBB61_356
; CHECK-RV32-NEXT: .LBB61_857: # %cond.load1333
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 335
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 334
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 334
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bltz a3, .LBB61_858
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bltz a2, .LBB61_858
; CHECK-RV32-NEXT: j .LBB61_357
; CHECK-RV32-NEXT: .LBB61_858: # %cond.load1337
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 336
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 335
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 335
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bltz a3, .LBB61_859
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bltz a2, .LBB61_859
; CHECK-RV32-NEXT: j .LBB61_358
; CHECK-RV32-NEXT: .LBB61_859: # %cond.load1341
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 337
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 336
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 336
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bltz a3, .LBB61_860
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bltz a2, .LBB61_860
; CHECK-RV32-NEXT: j .LBB61_359
; CHECK-RV32-NEXT: .LBB61_860: # %cond.load1345
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 338
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 337
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 337
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bltz a3, .LBB61_861
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bltz a2, .LBB61_861
; CHECK-RV32-NEXT: j .LBB61_360
; CHECK-RV32-NEXT: .LBB61_861: # %cond.load1349
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 339
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 338
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 338
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bltz a3, .LBB61_862
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bltz a2, .LBB61_862
; CHECK-RV32-NEXT: j .LBB61_361
; CHECK-RV32-NEXT: .LBB61_862: # %cond.load1353
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 340
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 339
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 339
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bltz a3, .LBB61_863
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bltz a2, .LBB61_863
; CHECK-RV32-NEXT: j .LBB61_362
; CHECK-RV32-NEXT: .LBB61_863: # %cond.load1357
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 341
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 340
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 340
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bltz a3, .LBB61_864
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bltz a2, .LBB61_864
; CHECK-RV32-NEXT: j .LBB61_363
; CHECK-RV32-NEXT: .LBB61_864: # %cond.load1361
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 342
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 341
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 341
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bltz a3, .LBB61_865
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bltz a2, .LBB61_865
; CHECK-RV32-NEXT: j .LBB61_364
; CHECK-RV32-NEXT: .LBB61_865: # %cond.load1365
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 343
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 342
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 342
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bltz a3, .LBB61_866
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bltz a2, .LBB61_866
; CHECK-RV32-NEXT: j .LBB61_365
; CHECK-RV32-NEXT: .LBB61_866: # %cond.load1369
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 344
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 343
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 343
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bltz a3, .LBB61_867
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bltz a2, .LBB61_867
; CHECK-RV32-NEXT: j .LBB61_366
; CHECK-RV32-NEXT: .LBB61_867: # %cond.load1373
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 345
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 344
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 344
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bltz a3, .LBB61_868
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bltz a2, .LBB61_868
; CHECK-RV32-NEXT: j .LBB61_367
; CHECK-RV32-NEXT: .LBB61_868: # %cond.load1377
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 346
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 345
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 345
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bltz a3, .LBB61_869
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bltz a2, .LBB61_869
; CHECK-RV32-NEXT: j .LBB61_368
; CHECK-RV32-NEXT: .LBB61_869: # %cond.load1381
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 347
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 346
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 346
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bltz a3, .LBB61_870
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bltz a2, .LBB61_870
; CHECK-RV32-NEXT: j .LBB61_369
; CHECK-RV32-NEXT: .LBB61_870: # %cond.load1385
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 348
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 347
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 347
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bltz a3, .LBB61_871
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bltz a2, .LBB61_871
; CHECK-RV32-NEXT: j .LBB61_370
; CHECK-RV32-NEXT: .LBB61_871: # %cond.load1389
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 349
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a3
-; CHECK-RV32-NEXT: li a3, 348
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 348
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_1035
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_1035
; CHECK-RV32-NEXT: j .LBB61_371
; CHECK-RV32-NEXT: .LBB61_1035: # %cond.load1389
; CHECK-RV32-NEXT: j .LBB61_372
; CHECK-RV32-NEXT: .LBB61_872: # %cond.load1401
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 352
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 352
; CHECK-RV32-NEXT: li a4, 351
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: bnez a2, .LBB61_873
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: bnez a3, .LBB61_873
; CHECK-RV32-NEXT: j .LBB61_376
; CHECK-RV32-NEXT: .LBB61_873: # %cond.load1405
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 353
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 352
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 352
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: bnez a2, .LBB61_874
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: bnez a3, .LBB61_874
; CHECK-RV32-NEXT: j .LBB61_377
; CHECK-RV32-NEXT: .LBB61_874: # %cond.load1409
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 354
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 353
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 353
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: bnez a2, .LBB61_875
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: bnez a3, .LBB61_875
; CHECK-RV32-NEXT: j .LBB61_378
; CHECK-RV32-NEXT: .LBB61_875: # %cond.load1413
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 355
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 354
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 354
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: bnez a2, .LBB61_876
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: bnez a3, .LBB61_876
; CHECK-RV32-NEXT: j .LBB61_379
; CHECK-RV32-NEXT: .LBB61_876: # %cond.load1417
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 356
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 355
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 355
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: bnez a2, .LBB61_877
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: bnez a3, .LBB61_877
; CHECK-RV32-NEXT: j .LBB61_380
; CHECK-RV32-NEXT: .LBB61_877: # %cond.load1421
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 357
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 356
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 356
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: bnez a2, .LBB61_878
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: bnez a3, .LBB61_878
; CHECK-RV32-NEXT: j .LBB61_381
; CHECK-RV32-NEXT: .LBB61_878: # %cond.load1425
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 358
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 357
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 357
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: bnez a2, .LBB61_879
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: bnez a3, .LBB61_879
; CHECK-RV32-NEXT: j .LBB61_382
; CHECK-RV32-NEXT: .LBB61_879: # %cond.load1429
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 359
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 358
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 358
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: bnez a2, .LBB61_880
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: bnez a3, .LBB61_880
; CHECK-RV32-NEXT: j .LBB61_383
; CHECK-RV32-NEXT: .LBB61_880: # %cond.load1433
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 360
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 359
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 359
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: bnez a2, .LBB61_881
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: bnez a3, .LBB61_881
; CHECK-RV32-NEXT: j .LBB61_384
; CHECK-RV32-NEXT: .LBB61_881: # %cond.load1437
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 361
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 360
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 360
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: bnez a2, .LBB61_882
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: bnez a3, .LBB61_882
; CHECK-RV32-NEXT: j .LBB61_385
; CHECK-RV32-NEXT: .LBB61_882: # %cond.load1441
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 362
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 361
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 361
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: bnez a2, .LBB61_883
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: bnez a3, .LBB61_883
; CHECK-RV32-NEXT: j .LBB61_386
; CHECK-RV32-NEXT: .LBB61_883: # %cond.load1445
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 363
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 362
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 362
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bltz a2, .LBB61_884
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bltz a3, .LBB61_884
; CHECK-RV32-NEXT: j .LBB61_387
; CHECK-RV32-NEXT: .LBB61_884: # %cond.load1449
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 364
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 363
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 363
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bltz a2, .LBB61_885
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bltz a3, .LBB61_885
; CHECK-RV32-NEXT: j .LBB61_388
; CHECK-RV32-NEXT: .LBB61_885: # %cond.load1453
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 365
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 364
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 364
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bltz a2, .LBB61_886
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bltz a3, .LBB61_886
; CHECK-RV32-NEXT: j .LBB61_389
; CHECK-RV32-NEXT: .LBB61_886: # %cond.load1457
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 366
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 365
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 365
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bltz a2, .LBB61_887
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bltz a3, .LBB61_887
; CHECK-RV32-NEXT: j .LBB61_390
; CHECK-RV32-NEXT: .LBB61_887: # %cond.load1461
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 367
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 366
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 366
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bltz a2, .LBB61_888
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bltz a3, .LBB61_888
; CHECK-RV32-NEXT: j .LBB61_391
; CHECK-RV32-NEXT: .LBB61_888: # %cond.load1465
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 368
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 367
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 367
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bltz a2, .LBB61_889
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bltz a3, .LBB61_889
; CHECK-RV32-NEXT: j .LBB61_392
; CHECK-RV32-NEXT: .LBB61_889: # %cond.load1469
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 369
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 368
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 368
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bltz a2, .LBB61_890
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bltz a3, .LBB61_890
; CHECK-RV32-NEXT: j .LBB61_393
; CHECK-RV32-NEXT: .LBB61_890: # %cond.load1473
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 370
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 369
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 369
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bltz a2, .LBB61_891
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bltz a3, .LBB61_891
; CHECK-RV32-NEXT: j .LBB61_394
; CHECK-RV32-NEXT: .LBB61_891: # %cond.load1477
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 371
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 370
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 370
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bltz a2, .LBB61_892
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bltz a3, .LBB61_892
; CHECK-RV32-NEXT: j .LBB61_395
; CHECK-RV32-NEXT: .LBB61_892: # %cond.load1481
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 372
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 371
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 371
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bltz a2, .LBB61_893
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bltz a3, .LBB61_893
; CHECK-RV32-NEXT: j .LBB61_396
; CHECK-RV32-NEXT: .LBB61_893: # %cond.load1485
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 373
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 372
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 372
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bltz a2, .LBB61_894
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bltz a3, .LBB61_894
; CHECK-RV32-NEXT: j .LBB61_397
; CHECK-RV32-NEXT: .LBB61_894: # %cond.load1489
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 374
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 373
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 373
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bltz a2, .LBB61_895
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bltz a3, .LBB61_895
; CHECK-RV32-NEXT: j .LBB61_398
; CHECK-RV32-NEXT: .LBB61_895: # %cond.load1493
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 375
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 374
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 374
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bltz a2, .LBB61_896
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bltz a3, .LBB61_896
; CHECK-RV32-NEXT: j .LBB61_399
; CHECK-RV32-NEXT: .LBB61_896: # %cond.load1497
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 376
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 375
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 375
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bltz a2, .LBB61_897
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bltz a3, .LBB61_897
; CHECK-RV32-NEXT: j .LBB61_400
; CHECK-RV32-NEXT: .LBB61_897: # %cond.load1501
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 377
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 376
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 376
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bltz a2, .LBB61_898
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bltz a3, .LBB61_898
; CHECK-RV32-NEXT: j .LBB61_401
; CHECK-RV32-NEXT: .LBB61_898: # %cond.load1505
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 378
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 377
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 377
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bltz a2, .LBB61_899
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bltz a3, .LBB61_899
; CHECK-RV32-NEXT: j .LBB61_402
; CHECK-RV32-NEXT: .LBB61_899: # %cond.load1509
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 379
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 378
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 378
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bltz a2, .LBB61_900
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bltz a3, .LBB61_900
; CHECK-RV32-NEXT: j .LBB61_403
; CHECK-RV32-NEXT: .LBB61_900: # %cond.load1513
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 380
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 379
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 379
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bltz a2, .LBB61_901
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bltz a3, .LBB61_901
; CHECK-RV32-NEXT: j .LBB61_404
; CHECK-RV32-NEXT: .LBB61_901: # %cond.load1517
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 381
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 380
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 380
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_1036
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_1036
; CHECK-RV32-NEXT: j .LBB61_405
; CHECK-RV32-NEXT: .LBB61_1036: # %cond.load1517
; CHECK-RV32-NEXT: j .LBB61_406
; CHECK-RV32-NEXT: .LBB61_902: # %cond.load1529
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 384
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 384
; CHECK-RV32-NEXT: li a4, 383
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: bnez a3, .LBB61_903
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: bnez a2, .LBB61_903
; CHECK-RV32-NEXT: j .LBB61_410
; CHECK-RV32-NEXT: .LBB61_903: # %cond.load1533
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 385
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 384
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 384
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: bnez a3, .LBB61_904
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: bnez a2, .LBB61_904
; CHECK-RV32-NEXT: j .LBB61_411
; CHECK-RV32-NEXT: .LBB61_904: # %cond.load1537
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 386
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 385
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 385
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: bnez a3, .LBB61_905
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: bnez a2, .LBB61_905
; CHECK-RV32-NEXT: j .LBB61_412
; CHECK-RV32-NEXT: .LBB61_905: # %cond.load1541
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 387
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 386
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 386
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: bnez a3, .LBB61_906
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: bnez a2, .LBB61_906
; CHECK-RV32-NEXT: j .LBB61_413
; CHECK-RV32-NEXT: .LBB61_906: # %cond.load1545
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 388
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 387
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 387
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: bnez a3, .LBB61_907
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: bnez a2, .LBB61_907
; CHECK-RV32-NEXT: j .LBB61_414
; CHECK-RV32-NEXT: .LBB61_907: # %cond.load1549
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 389
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 388
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 388
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: bnez a3, .LBB61_908
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: bnez a2, .LBB61_908
; CHECK-RV32-NEXT: j .LBB61_415
; CHECK-RV32-NEXT: .LBB61_908: # %cond.load1553
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 390
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 389
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 389
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: bnez a3, .LBB61_909
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: bnez a2, .LBB61_909
; CHECK-RV32-NEXT: j .LBB61_416
; CHECK-RV32-NEXT: .LBB61_909: # %cond.load1557
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 391
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 390
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 390
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: bnez a3, .LBB61_910
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: bnez a2, .LBB61_910
; CHECK-RV32-NEXT: j .LBB61_417
; CHECK-RV32-NEXT: .LBB61_910: # %cond.load1561
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 392
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 391
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 391
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: bnez a3, .LBB61_911
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: bnez a2, .LBB61_911
; CHECK-RV32-NEXT: j .LBB61_418
; CHECK-RV32-NEXT: .LBB61_911: # %cond.load1565
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 393
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 392
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 392
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: bnez a3, .LBB61_912
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: bnez a2, .LBB61_912
; CHECK-RV32-NEXT: j .LBB61_419
; CHECK-RV32-NEXT: .LBB61_912: # %cond.load1569
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 394
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 393
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 393
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: bnez a3, .LBB61_913
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: bnez a2, .LBB61_913
; CHECK-RV32-NEXT: j .LBB61_420
; CHECK-RV32-NEXT: .LBB61_913: # %cond.load1573
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 395
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 394
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 394
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bltz a3, .LBB61_914
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bltz a2, .LBB61_914
; CHECK-RV32-NEXT: j .LBB61_421
; CHECK-RV32-NEXT: .LBB61_914: # %cond.load1577
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 396
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 395
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 395
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bltz a3, .LBB61_915
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bltz a2, .LBB61_915
; CHECK-RV32-NEXT: j .LBB61_422
; CHECK-RV32-NEXT: .LBB61_915: # %cond.load1581
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 397
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 396
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 396
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bltz a3, .LBB61_916
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bltz a2, .LBB61_916
; CHECK-RV32-NEXT: j .LBB61_423
; CHECK-RV32-NEXT: .LBB61_916: # %cond.load1585
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 398
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 397
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 397
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bltz a3, .LBB61_917
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bltz a2, .LBB61_917
; CHECK-RV32-NEXT: j .LBB61_424
; CHECK-RV32-NEXT: .LBB61_917: # %cond.load1589
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 399
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 398
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 398
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bltz a3, .LBB61_918
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bltz a2, .LBB61_918
; CHECK-RV32-NEXT: j .LBB61_425
; CHECK-RV32-NEXT: .LBB61_918: # %cond.load1593
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 400
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 399
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 399
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bltz a3, .LBB61_919
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bltz a2, .LBB61_919
; CHECK-RV32-NEXT: j .LBB61_426
; CHECK-RV32-NEXT: .LBB61_919: # %cond.load1597
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 401
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 400
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 400
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bltz a3, .LBB61_920
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bltz a2, .LBB61_920
; CHECK-RV32-NEXT: j .LBB61_427
; CHECK-RV32-NEXT: .LBB61_920: # %cond.load1601
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 402
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 401
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 401
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bltz a3, .LBB61_921
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bltz a2, .LBB61_921
; CHECK-RV32-NEXT: j .LBB61_428
; CHECK-RV32-NEXT: .LBB61_921: # %cond.load1605
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 403
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 402
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 402
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bltz a3, .LBB61_922
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bltz a2, .LBB61_922
; CHECK-RV32-NEXT: j .LBB61_429
; CHECK-RV32-NEXT: .LBB61_922: # %cond.load1609
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 404
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 403
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 403
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bltz a3, .LBB61_923
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bltz a2, .LBB61_923
; CHECK-RV32-NEXT: j .LBB61_430
; CHECK-RV32-NEXT: .LBB61_923: # %cond.load1613
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 405
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 404
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 404
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bltz a3, .LBB61_924
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bltz a2, .LBB61_924
; CHECK-RV32-NEXT: j .LBB61_431
; CHECK-RV32-NEXT: .LBB61_924: # %cond.load1617
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 406
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 405
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 405
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bltz a3, .LBB61_925
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bltz a2, .LBB61_925
; CHECK-RV32-NEXT: j .LBB61_432
; CHECK-RV32-NEXT: .LBB61_925: # %cond.load1621
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 407
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 406
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 406
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bltz a3, .LBB61_926
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bltz a2, .LBB61_926
; CHECK-RV32-NEXT: j .LBB61_433
; CHECK-RV32-NEXT: .LBB61_926: # %cond.load1625
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 408
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 407
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 407
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bltz a3, .LBB61_927
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bltz a2, .LBB61_927
; CHECK-RV32-NEXT: j .LBB61_434
; CHECK-RV32-NEXT: .LBB61_927: # %cond.load1629
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 409
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 408
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 408
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bltz a3, .LBB61_928
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bltz a2, .LBB61_928
; CHECK-RV32-NEXT: j .LBB61_435
; CHECK-RV32-NEXT: .LBB61_928: # %cond.load1633
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 410
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 409
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 409
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bltz a3, .LBB61_929
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bltz a2, .LBB61_929
; CHECK-RV32-NEXT: j .LBB61_436
; CHECK-RV32-NEXT: .LBB61_929: # %cond.load1637
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 411
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 410
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 410
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bltz a3, .LBB61_930
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bltz a2, .LBB61_930
; CHECK-RV32-NEXT: j .LBB61_437
; CHECK-RV32-NEXT: .LBB61_930: # %cond.load1641
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 412
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 411
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 411
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bltz a3, .LBB61_931
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bltz a2, .LBB61_931
; CHECK-RV32-NEXT: j .LBB61_438
; CHECK-RV32-NEXT: .LBB61_931: # %cond.load1645
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 413
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 412
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: li a2, 412
+; CHECK-RV32-NEXT: vslideup.vx v8, v24, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_1037
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_1037
; CHECK-RV32-NEXT: j .LBB61_439
; CHECK-RV32-NEXT: .LBB61_1037: # %cond.load1645
; CHECK-RV32-NEXT: j .LBB61_440
; CHECK-RV32-NEXT: .LBB61_932: # %cond.load1657
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 416
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 416
; CHECK-RV32-NEXT: li a4, 415
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1
-; CHECK-RV32-NEXT: bnez a2, .LBB61_933
+; CHECK-RV32-NEXT: andi a3, a2, 1
+; CHECK-RV32-NEXT: bnez a3, .LBB61_933
; CHECK-RV32-NEXT: j .LBB61_444
; CHECK-RV32-NEXT: .LBB61_933: # %cond.load1661
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 417
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 416
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 416
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 2
-; CHECK-RV32-NEXT: bnez a2, .LBB61_934
+; CHECK-RV32-NEXT: andi a3, a2, 2
+; CHECK-RV32-NEXT: bnez a3, .LBB61_934
; CHECK-RV32-NEXT: j .LBB61_445
; CHECK-RV32-NEXT: .LBB61_934: # %cond.load1665
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 418
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 417
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 417
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 4
-; CHECK-RV32-NEXT: bnez a2, .LBB61_935
+; CHECK-RV32-NEXT: andi a3, a2, 4
+; CHECK-RV32-NEXT: bnez a3, .LBB61_935
; CHECK-RV32-NEXT: j .LBB61_446
; CHECK-RV32-NEXT: .LBB61_935: # %cond.load1669
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 419
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 418
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 418
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 8
-; CHECK-RV32-NEXT: bnez a2, .LBB61_936
+; CHECK-RV32-NEXT: andi a3, a2, 8
+; CHECK-RV32-NEXT: bnez a3, .LBB61_936
; CHECK-RV32-NEXT: j .LBB61_447
; CHECK-RV32-NEXT: .LBB61_936: # %cond.load1673
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 420
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 419
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 419
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 16
-; CHECK-RV32-NEXT: bnez a2, .LBB61_937
+; CHECK-RV32-NEXT: andi a3, a2, 16
+; CHECK-RV32-NEXT: bnez a3, .LBB61_937
; CHECK-RV32-NEXT: j .LBB61_448
; CHECK-RV32-NEXT: .LBB61_937: # %cond.load1677
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 421
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 420
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 420
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 32
-; CHECK-RV32-NEXT: bnez a2, .LBB61_938
+; CHECK-RV32-NEXT: andi a3, a2, 32
+; CHECK-RV32-NEXT: bnez a3, .LBB61_938
; CHECK-RV32-NEXT: j .LBB61_449
; CHECK-RV32-NEXT: .LBB61_938: # %cond.load1681
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 422
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 421
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 421
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 64
-; CHECK-RV32-NEXT: bnez a2, .LBB61_939
+; CHECK-RV32-NEXT: andi a3, a2, 64
+; CHECK-RV32-NEXT: bnez a3, .LBB61_939
; CHECK-RV32-NEXT: j .LBB61_450
; CHECK-RV32-NEXT: .LBB61_939: # %cond.load1685
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 423
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 422
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 422
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 128
-; CHECK-RV32-NEXT: bnez a2, .LBB61_940
+; CHECK-RV32-NEXT: andi a3, a2, 128
+; CHECK-RV32-NEXT: bnez a3, .LBB61_940
; CHECK-RV32-NEXT: j .LBB61_451
; CHECK-RV32-NEXT: .LBB61_940: # %cond.load1689
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 424
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 423
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 423
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 256
-; CHECK-RV32-NEXT: bnez a2, .LBB61_941
+; CHECK-RV32-NEXT: andi a3, a2, 256
+; CHECK-RV32-NEXT: bnez a3, .LBB61_941
; CHECK-RV32-NEXT: j .LBB61_452
; CHECK-RV32-NEXT: .LBB61_941: # %cond.load1693
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 425
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 424
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 424
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 512
-; CHECK-RV32-NEXT: bnez a2, .LBB61_942
+; CHECK-RV32-NEXT: andi a3, a2, 512
+; CHECK-RV32-NEXT: bnez a3, .LBB61_942
; CHECK-RV32-NEXT: j .LBB61_453
; CHECK-RV32-NEXT: .LBB61_942: # %cond.load1697
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 426
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 425
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 425
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a2, a3, 1024
-; CHECK-RV32-NEXT: bnez a2, .LBB61_943
+; CHECK-RV32-NEXT: andi a3, a2, 1024
+; CHECK-RV32-NEXT: bnez a3, .LBB61_943
; CHECK-RV32-NEXT: j .LBB61_454
; CHECK-RV32-NEXT: .LBB61_943: # %cond.load1701
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 427
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 426
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 426
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 20
-; CHECK-RV32-NEXT: bltz a2, .LBB61_944
+; CHECK-RV32-NEXT: slli a3, a2, 20
+; CHECK-RV32-NEXT: bltz a3, .LBB61_944
; CHECK-RV32-NEXT: j .LBB61_455
; CHECK-RV32-NEXT: .LBB61_944: # %cond.load1705
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 428
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 427
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 427
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 19
-; CHECK-RV32-NEXT: bltz a2, .LBB61_945
+; CHECK-RV32-NEXT: slli a3, a2, 19
+; CHECK-RV32-NEXT: bltz a3, .LBB61_945
; CHECK-RV32-NEXT: j .LBB61_456
; CHECK-RV32-NEXT: .LBB61_945: # %cond.load1709
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 429
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 428
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 428
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 18
-; CHECK-RV32-NEXT: bltz a2, .LBB61_946
+; CHECK-RV32-NEXT: slli a3, a2, 18
+; CHECK-RV32-NEXT: bltz a3, .LBB61_946
; CHECK-RV32-NEXT: j .LBB61_457
; CHECK-RV32-NEXT: .LBB61_946: # %cond.load1713
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 430
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 429
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
-; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 17
-; CHECK-RV32-NEXT: bltz a2, .LBB61_947
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 429
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV32-NEXT: addi a0, a0, 1
+; CHECK-RV32-NEXT: slli a3, a2, 17
+; CHECK-RV32-NEXT: bltz a3, .LBB61_947
; CHECK-RV32-NEXT: j .LBB61_458
; CHECK-RV32-NEXT: .LBB61_947: # %cond.load1717
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 431
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 430
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 430
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 16
-; CHECK-RV32-NEXT: bltz a2, .LBB61_948
+; CHECK-RV32-NEXT: slli a3, a2, 16
+; CHECK-RV32-NEXT: bltz a3, .LBB61_948
; CHECK-RV32-NEXT: j .LBB61_459
; CHECK-RV32-NEXT: .LBB61_948: # %cond.load1721
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 432
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 431
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 431
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 15
-; CHECK-RV32-NEXT: bltz a2, .LBB61_949
+; CHECK-RV32-NEXT: slli a3, a2, 15
+; CHECK-RV32-NEXT: bltz a3, .LBB61_949
; CHECK-RV32-NEXT: j .LBB61_460
; CHECK-RV32-NEXT: .LBB61_949: # %cond.load1725
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 433
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 432
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 432
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 14
-; CHECK-RV32-NEXT: bltz a2, .LBB61_950
+; CHECK-RV32-NEXT: slli a3, a2, 14
+; CHECK-RV32-NEXT: bltz a3, .LBB61_950
; CHECK-RV32-NEXT: j .LBB61_461
; CHECK-RV32-NEXT: .LBB61_950: # %cond.load1729
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 434
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 433
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 433
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 13
-; CHECK-RV32-NEXT: bltz a2, .LBB61_951
+; CHECK-RV32-NEXT: slli a3, a2, 13
+; CHECK-RV32-NEXT: bltz a3, .LBB61_951
; CHECK-RV32-NEXT: j .LBB61_462
; CHECK-RV32-NEXT: .LBB61_951: # %cond.load1733
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 435
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 434
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 434
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 12
-; CHECK-RV32-NEXT: bltz a2, .LBB61_952
+; CHECK-RV32-NEXT: slli a3, a2, 12
+; CHECK-RV32-NEXT: bltz a3, .LBB61_952
; CHECK-RV32-NEXT: j .LBB61_463
; CHECK-RV32-NEXT: .LBB61_952: # %cond.load1737
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 436
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 435
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 435
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 11
-; CHECK-RV32-NEXT: bltz a2, .LBB61_953
+; CHECK-RV32-NEXT: slli a3, a2, 11
+; CHECK-RV32-NEXT: bltz a3, .LBB61_953
; CHECK-RV32-NEXT: j .LBB61_464
; CHECK-RV32-NEXT: .LBB61_953: # %cond.load1741
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 437
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 436
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 436
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 10
-; CHECK-RV32-NEXT: bltz a2, .LBB61_954
+; CHECK-RV32-NEXT: slli a3, a2, 10
+; CHECK-RV32-NEXT: bltz a3, .LBB61_954
; CHECK-RV32-NEXT: j .LBB61_465
; CHECK-RV32-NEXT: .LBB61_954: # %cond.load1745
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 438
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 437
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 437
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 9
-; CHECK-RV32-NEXT: bltz a2, .LBB61_955
+; CHECK-RV32-NEXT: slli a3, a2, 9
+; CHECK-RV32-NEXT: bltz a3, .LBB61_955
; CHECK-RV32-NEXT: j .LBB61_466
; CHECK-RV32-NEXT: .LBB61_955: # %cond.load1749
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 439
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 438
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 438
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 8
-; CHECK-RV32-NEXT: bltz a2, .LBB61_956
+; CHECK-RV32-NEXT: slli a3, a2, 8
+; CHECK-RV32-NEXT: bltz a3, .LBB61_956
; CHECK-RV32-NEXT: j .LBB61_467
; CHECK-RV32-NEXT: .LBB61_956: # %cond.load1753
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 440
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 439
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 439
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 7
-; CHECK-RV32-NEXT: bltz a2, .LBB61_957
+; CHECK-RV32-NEXT: slli a3, a2, 7
+; CHECK-RV32-NEXT: bltz a3, .LBB61_957
; CHECK-RV32-NEXT: j .LBB61_468
; CHECK-RV32-NEXT: .LBB61_957: # %cond.load1757
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 441
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 440
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 440
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 6
-; CHECK-RV32-NEXT: bltz a2, .LBB61_958
+; CHECK-RV32-NEXT: slli a3, a2, 6
+; CHECK-RV32-NEXT: bltz a3, .LBB61_958
; CHECK-RV32-NEXT: j .LBB61_469
; CHECK-RV32-NEXT: .LBB61_958: # %cond.load1761
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 442
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 441
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 441
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 5
-; CHECK-RV32-NEXT: bltz a2, .LBB61_959
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: bltz a3, .LBB61_959
; CHECK-RV32-NEXT: j .LBB61_470
; CHECK-RV32-NEXT: .LBB61_959: # %cond.load1765
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 443
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 442
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 442
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 4
-; CHECK-RV32-NEXT: bltz a2, .LBB61_960
+; CHECK-RV32-NEXT: slli a3, a2, 4
+; CHECK-RV32-NEXT: bltz a3, .LBB61_960
; CHECK-RV32-NEXT: j .LBB61_471
; CHECK-RV32-NEXT: .LBB61_960: # %cond.load1769
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 444
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 443
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 443
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 3
-; CHECK-RV32-NEXT: bltz a2, .LBB61_961
+; CHECK-RV32-NEXT: slli a3, a2, 3
+; CHECK-RV32-NEXT: bltz a3, .LBB61_961
; CHECK-RV32-NEXT: j .LBB61_472
; CHECK-RV32-NEXT: .LBB61_961: # %cond.load1773
-; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 445
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v16, a2
-; CHECK-RV32-NEXT: li a2, 444
-; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
+; CHECK-RV32-NEXT: li a3, 444
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a2, a3, 2
-; CHECK-RV32-NEXT: bgez a2, .LBB61_1038
+; CHECK-RV32-NEXT: slli a3, a2, 2
+; CHECK-RV32-NEXT: bgez a3, .LBB61_1038
; CHECK-RV32-NEXT: j .LBB61_473
; CHECK-RV32-NEXT: .LBB61_1038: # %cond.load1773
; CHECK-RV32-NEXT: j .LBB61_474
; CHECK-RV32-NEXT: .LBB61_962: # %cond.load1785
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 448
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 448
; CHECK-RV32-NEXT: li a4, 447
-; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a4
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1
-; CHECK-RV32-NEXT: bnez a3, .LBB61_963
+; CHECK-RV32-NEXT: andi a2, a3, 1
+; CHECK-RV32-NEXT: bnez a2, .LBB61_963
; CHECK-RV32-NEXT: j .LBB61_478
; CHECK-RV32-NEXT: .LBB61_963: # %cond.load1789
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 449
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 448
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 448
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 2
-; CHECK-RV32-NEXT: bnez a3, .LBB61_964
+; CHECK-RV32-NEXT: andi a2, a3, 2
+; CHECK-RV32-NEXT: bnez a2, .LBB61_964
; CHECK-RV32-NEXT: j .LBB61_479
; CHECK-RV32-NEXT: .LBB61_964: # %cond.load1793
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 450
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 449
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 449
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 4
-; CHECK-RV32-NEXT: bnez a3, .LBB61_965
+; CHECK-RV32-NEXT: andi a2, a3, 4
+; CHECK-RV32-NEXT: bnez a2, .LBB61_965
; CHECK-RV32-NEXT: j .LBB61_480
; CHECK-RV32-NEXT: .LBB61_965: # %cond.load1797
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 451
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 450
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 450
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 8
-; CHECK-RV32-NEXT: bnez a3, .LBB61_966
+; CHECK-RV32-NEXT: andi a2, a3, 8
+; CHECK-RV32-NEXT: bnez a2, .LBB61_966
; CHECK-RV32-NEXT: j .LBB61_481
; CHECK-RV32-NEXT: .LBB61_966: # %cond.load1801
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 452
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 451
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 451
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 16
-; CHECK-RV32-NEXT: bnez a3, .LBB61_967
+; CHECK-RV32-NEXT: andi a2, a3, 16
+; CHECK-RV32-NEXT: bnez a2, .LBB61_967
; CHECK-RV32-NEXT: j .LBB61_482
; CHECK-RV32-NEXT: .LBB61_967: # %cond.load1805
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 453
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 452
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 452
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 32
-; CHECK-RV32-NEXT: bnez a3, .LBB61_968
+; CHECK-RV32-NEXT: andi a2, a3, 32
+; CHECK-RV32-NEXT: bnez a2, .LBB61_968
; CHECK-RV32-NEXT: j .LBB61_483
; CHECK-RV32-NEXT: .LBB61_968: # %cond.load1809
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 454
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 453
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 453
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 64
-; CHECK-RV32-NEXT: bnez a3, .LBB61_969
+; CHECK-RV32-NEXT: andi a2, a3, 64
+; CHECK-RV32-NEXT: bnez a2, .LBB61_969
; CHECK-RV32-NEXT: j .LBB61_484
; CHECK-RV32-NEXT: .LBB61_969: # %cond.load1813
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 455
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 454
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 454
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 128
-; CHECK-RV32-NEXT: bnez a3, .LBB61_970
+; CHECK-RV32-NEXT: andi a2, a3, 128
+; CHECK-RV32-NEXT: bnez a2, .LBB61_970
; CHECK-RV32-NEXT: j .LBB61_485
; CHECK-RV32-NEXT: .LBB61_970: # %cond.load1817
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 456
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 455
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 455
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 256
-; CHECK-RV32-NEXT: bnez a3, .LBB61_971
+; CHECK-RV32-NEXT: andi a2, a3, 256
+; CHECK-RV32-NEXT: bnez a2, .LBB61_971
; CHECK-RV32-NEXT: j .LBB61_486
; CHECK-RV32-NEXT: .LBB61_971: # %cond.load1821
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 457
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 456
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 456
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 512
-; CHECK-RV32-NEXT: bnez a3, .LBB61_972
+; CHECK-RV32-NEXT: andi a2, a3, 512
+; CHECK-RV32-NEXT: bnez a2, .LBB61_972
; CHECK-RV32-NEXT: j .LBB61_487
; CHECK-RV32-NEXT: .LBB61_972: # %cond.load1825
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 458
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 457
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 457
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: andi a3, a2, 1024
-; CHECK-RV32-NEXT: bnez a3, .LBB61_973
+; CHECK-RV32-NEXT: andi a2, a3, 1024
+; CHECK-RV32-NEXT: bnez a2, .LBB61_973
; CHECK-RV32-NEXT: j .LBB61_488
; CHECK-RV32-NEXT: .LBB61_973: # %cond.load1829
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 459
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 458
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 458
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 20
-; CHECK-RV32-NEXT: bltz a3, .LBB61_974
+; CHECK-RV32-NEXT: slli a2, a3, 20
+; CHECK-RV32-NEXT: bltz a2, .LBB61_974
; CHECK-RV32-NEXT: j .LBB61_489
; CHECK-RV32-NEXT: .LBB61_974: # %cond.load1833
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 460
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 459
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 459
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 19
-; CHECK-RV32-NEXT: bltz a3, .LBB61_975
+; CHECK-RV32-NEXT: slli a2, a3, 19
+; CHECK-RV32-NEXT: bltz a2, .LBB61_975
; CHECK-RV32-NEXT: j .LBB61_490
; CHECK-RV32-NEXT: .LBB61_975: # %cond.load1837
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 461
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 460
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 460
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 18
-; CHECK-RV32-NEXT: bltz a3, .LBB61_976
+; CHECK-RV32-NEXT: slli a2, a3, 18
+; CHECK-RV32-NEXT: bltz a2, .LBB61_976
; CHECK-RV32-NEXT: j .LBB61_491
; CHECK-RV32-NEXT: .LBB61_976: # %cond.load1841
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 462
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 461
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 461
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 17
-; CHECK-RV32-NEXT: bltz a3, .LBB61_977
+; CHECK-RV32-NEXT: slli a2, a3, 17
+; CHECK-RV32-NEXT: bltz a2, .LBB61_977
; CHECK-RV32-NEXT: j .LBB61_492
; CHECK-RV32-NEXT: .LBB61_977: # %cond.load1845
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 463
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 462
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 462
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 16
-; CHECK-RV32-NEXT: bltz a3, .LBB61_978
+; CHECK-RV32-NEXT: slli a2, a3, 16
+; CHECK-RV32-NEXT: bltz a2, .LBB61_978
; CHECK-RV32-NEXT: j .LBB61_493
; CHECK-RV32-NEXT: .LBB61_978: # %cond.load1849
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 464
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 463
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 463
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 15
-; CHECK-RV32-NEXT: bltz a3, .LBB61_979
+; CHECK-RV32-NEXT: slli a2, a3, 15
+; CHECK-RV32-NEXT: bltz a2, .LBB61_979
; CHECK-RV32-NEXT: j .LBB61_494
; CHECK-RV32-NEXT: .LBB61_979: # %cond.load1853
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 465
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 464
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 464
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 14
-; CHECK-RV32-NEXT: bltz a3, .LBB61_980
+; CHECK-RV32-NEXT: slli a2, a3, 14
+; CHECK-RV32-NEXT: bltz a2, .LBB61_980
; CHECK-RV32-NEXT: j .LBB61_495
; CHECK-RV32-NEXT: .LBB61_980: # %cond.load1857
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 466
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 465
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 465
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 13
-; CHECK-RV32-NEXT: bltz a3, .LBB61_981
+; CHECK-RV32-NEXT: slli a2, a3, 13
+; CHECK-RV32-NEXT: bltz a2, .LBB61_981
; CHECK-RV32-NEXT: j .LBB61_496
; CHECK-RV32-NEXT: .LBB61_981: # %cond.load1861
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 467
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 466
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 466
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 12
-; CHECK-RV32-NEXT: bltz a3, .LBB61_982
+; CHECK-RV32-NEXT: slli a2, a3, 12
+; CHECK-RV32-NEXT: bltz a2, .LBB61_982
; CHECK-RV32-NEXT: j .LBB61_497
; CHECK-RV32-NEXT: .LBB61_982: # %cond.load1865
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 468
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 467
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 467
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 11
-; CHECK-RV32-NEXT: bltz a3, .LBB61_983
+; CHECK-RV32-NEXT: slli a2, a3, 11
+; CHECK-RV32-NEXT: bltz a2, .LBB61_983
; CHECK-RV32-NEXT: j .LBB61_498
; CHECK-RV32-NEXT: .LBB61_983: # %cond.load1869
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 469
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 468
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 468
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 10
-; CHECK-RV32-NEXT: bltz a3, .LBB61_984
+; CHECK-RV32-NEXT: slli a2, a3, 10
+; CHECK-RV32-NEXT: bltz a2, .LBB61_984
; CHECK-RV32-NEXT: j .LBB61_499
; CHECK-RV32-NEXT: .LBB61_984: # %cond.load1873
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 470
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 469
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 469
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 9
-; CHECK-RV32-NEXT: bltz a3, .LBB61_985
+; CHECK-RV32-NEXT: slli a2, a3, 9
+; CHECK-RV32-NEXT: bltz a2, .LBB61_985
; CHECK-RV32-NEXT: j .LBB61_500
; CHECK-RV32-NEXT: .LBB61_985: # %cond.load1877
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 471
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 470
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 470
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: bltz a3, .LBB61_986
+; CHECK-RV32-NEXT: slli a2, a3, 8
+; CHECK-RV32-NEXT: bltz a2, .LBB61_986
; CHECK-RV32-NEXT: j .LBB61_501
; CHECK-RV32-NEXT: .LBB61_986: # %cond.load1881
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 472
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 471
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 471
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 7
-; CHECK-RV32-NEXT: bltz a3, .LBB61_987
+; CHECK-RV32-NEXT: slli a2, a3, 7
+; CHECK-RV32-NEXT: bltz a2, .LBB61_987
; CHECK-RV32-NEXT: j .LBB61_502
; CHECK-RV32-NEXT: .LBB61_987: # %cond.load1885
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 473
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 472
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 472
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 6
-; CHECK-RV32-NEXT: bltz a3, .LBB61_988
+; CHECK-RV32-NEXT: slli a2, a3, 6
+; CHECK-RV32-NEXT: bltz a2, .LBB61_988
; CHECK-RV32-NEXT: j .LBB61_503
; CHECK-RV32-NEXT: .LBB61_988: # %cond.load1889
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 474
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 473
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 473
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: bltz a3, .LBB61_989
+; CHECK-RV32-NEXT: slli a2, a3, 5
+; CHECK-RV32-NEXT: bltz a2, .LBB61_989
; CHECK-RV32-NEXT: j .LBB61_504
; CHECK-RV32-NEXT: .LBB61_989: # %cond.load1893
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 475
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 474
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 474
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 4
-; CHECK-RV32-NEXT: bltz a3, .LBB61_990
+; CHECK-RV32-NEXT: slli a2, a3, 4
+; CHECK-RV32-NEXT: bltz a2, .LBB61_990
; CHECK-RV32-NEXT: j .LBB61_505
; CHECK-RV32-NEXT: .LBB61_990: # %cond.load1897
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 476
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 475
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 475
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 3
-; CHECK-RV32-NEXT: bltz a3, .LBB61_991
+; CHECK-RV32-NEXT: slli a2, a3, 3
+; CHECK-RV32-NEXT: bltz a2, .LBB61_991
; CHECK-RV32-NEXT: j .LBB61_506
; CHECK-RV32-NEXT: .LBB61_991: # %cond.load1901
-; CHECK-RV32-NEXT: lbu a3, 0(a0)
+; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 477
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
-; CHECK-RV32-NEXT: li a3, 476
-; CHECK-RV32-NEXT: vslideup.vx v8, v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
+; CHECK-RV32-NEXT: li a2, 476
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
-; CHECK-RV32-NEXT: slli a3, a2, 2
-; CHECK-RV32-NEXT: bgez a3, .LBB61_1039
+; CHECK-RV32-NEXT: slli a2, a3, 2
+; CHECK-RV32-NEXT: bgez a2, .LBB61_1039
; CHECK-RV32-NEXT: j .LBB61_507
; CHECK-RV32-NEXT: .LBB61_1039: # %cond.load1901
; CHECK-RV32-NEXT: j .LBB61_508
@@ -9559,8102 +9559,8102 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-LABEL: test_expandload_v512i8_vlen512:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v0
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: beqz a2, .LBB61_1
+; CHECK-RV64-NEXT: vmv.x.s a2, v0
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: beqz a1, .LBB61_1
; CHECK-RV64-NEXT: j .LBB61_527
; CHECK-RV64-NEXT: .LBB61_1: # %else
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: beqz a2, .LBB61_2
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: beqz a1, .LBB61_2
; CHECK-RV64-NEXT: j .LBB61_528
; CHECK-RV64-NEXT: .LBB61_2: # %else2
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: beqz a2, .LBB61_3
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: beqz a1, .LBB61_3
; CHECK-RV64-NEXT: j .LBB61_529
; CHECK-RV64-NEXT: .LBB61_3: # %else6
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: beqz a2, .LBB61_4
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: beqz a1, .LBB61_4
; CHECK-RV64-NEXT: j .LBB61_530
; CHECK-RV64-NEXT: .LBB61_4: # %else10
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: beqz a2, .LBB61_5
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: beqz a1, .LBB61_5
; CHECK-RV64-NEXT: j .LBB61_531
; CHECK-RV64-NEXT: .LBB61_5: # %else14
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: beqz a2, .LBB61_6
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: beqz a1, .LBB61_6
; CHECK-RV64-NEXT: j .LBB61_532
; CHECK-RV64-NEXT: .LBB61_6: # %else18
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: beqz a2, .LBB61_7
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: beqz a1, .LBB61_7
; CHECK-RV64-NEXT: j .LBB61_533
; CHECK-RV64-NEXT: .LBB61_7: # %else22
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: beqz a2, .LBB61_8
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: beqz a1, .LBB61_8
; CHECK-RV64-NEXT: j .LBB61_534
; CHECK-RV64-NEXT: .LBB61_8: # %else26
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: beqz a2, .LBB61_9
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: beqz a1, .LBB61_9
; CHECK-RV64-NEXT: j .LBB61_535
; CHECK-RV64-NEXT: .LBB61_9: # %else30
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: beqz a2, .LBB61_10
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: beqz a1, .LBB61_10
; CHECK-RV64-NEXT: j .LBB61_536
; CHECK-RV64-NEXT: .LBB61_10: # %else34
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: beqz a2, .LBB61_11
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: beqz a1, .LBB61_11
; CHECK-RV64-NEXT: j .LBB61_537
; CHECK-RV64-NEXT: .LBB61_11: # %else38
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bgez a2, .LBB61_12
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bgez a1, .LBB61_12
; CHECK-RV64-NEXT: j .LBB61_538
; CHECK-RV64-NEXT: .LBB61_12: # %else42
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bgez a2, .LBB61_13
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bgez a1, .LBB61_13
; CHECK-RV64-NEXT: j .LBB61_539
; CHECK-RV64-NEXT: .LBB61_13: # %else46
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bgez a2, .LBB61_14
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bgez a1, .LBB61_14
; CHECK-RV64-NEXT: j .LBB61_540
; CHECK-RV64-NEXT: .LBB61_14: # %else50
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bgez a2, .LBB61_15
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bgez a1, .LBB61_15
; CHECK-RV64-NEXT: j .LBB61_541
; CHECK-RV64-NEXT: .LBB61_15: # %else54
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bgez a2, .LBB61_16
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bgez a1, .LBB61_16
; CHECK-RV64-NEXT: j .LBB61_542
; CHECK-RV64-NEXT: .LBB61_16: # %else58
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bgez a2, .LBB61_17
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bgez a1, .LBB61_17
; CHECK-RV64-NEXT: j .LBB61_543
; CHECK-RV64-NEXT: .LBB61_17: # %else62
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bgez a2, .LBB61_18
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bgez a1, .LBB61_18
; CHECK-RV64-NEXT: j .LBB61_544
; CHECK-RV64-NEXT: .LBB61_18: # %else66
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bgez a2, .LBB61_19
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bgez a1, .LBB61_19
; CHECK-RV64-NEXT: j .LBB61_545
; CHECK-RV64-NEXT: .LBB61_19: # %else70
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bgez a2, .LBB61_20
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bgez a1, .LBB61_20
; CHECK-RV64-NEXT: j .LBB61_546
; CHECK-RV64-NEXT: .LBB61_20: # %else74
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bgez a2, .LBB61_21
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bgez a1, .LBB61_21
; CHECK-RV64-NEXT: j .LBB61_547
; CHECK-RV64-NEXT: .LBB61_21: # %else78
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bgez a2, .LBB61_22
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bgez a1, .LBB61_22
; CHECK-RV64-NEXT: j .LBB61_548
; CHECK-RV64-NEXT: .LBB61_22: # %else82
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bgez a2, .LBB61_23
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bgez a1, .LBB61_23
; CHECK-RV64-NEXT: j .LBB61_549
; CHECK-RV64-NEXT: .LBB61_23: # %else86
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bgez a2, .LBB61_24
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bgez a1, .LBB61_24
; CHECK-RV64-NEXT: j .LBB61_550
; CHECK-RV64-NEXT: .LBB61_24: # %else90
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bgez a2, .LBB61_25
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bgez a1, .LBB61_25
; CHECK-RV64-NEXT: j .LBB61_551
; CHECK-RV64-NEXT: .LBB61_25: # %else94
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bgez a2, .LBB61_26
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bgez a1, .LBB61_26
; CHECK-RV64-NEXT: j .LBB61_552
; CHECK-RV64-NEXT: .LBB61_26: # %else98
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bgez a2, .LBB61_27
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bgez a1, .LBB61_27
; CHECK-RV64-NEXT: j .LBB61_553
; CHECK-RV64-NEXT: .LBB61_27: # %else102
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bgez a2, .LBB61_28
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bgez a1, .LBB61_28
; CHECK-RV64-NEXT: j .LBB61_554
; CHECK-RV64-NEXT: .LBB61_28: # %else106
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bgez a2, .LBB61_29
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bgez a1, .LBB61_29
; CHECK-RV64-NEXT: j .LBB61_555
; CHECK-RV64-NEXT: .LBB61_29: # %else110
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bgez a2, .LBB61_30
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bgez a1, .LBB61_30
; CHECK-RV64-NEXT: j .LBB61_556
; CHECK-RV64-NEXT: .LBB61_30: # %else114
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bgez a2, .LBB61_31
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bgez a1, .LBB61_31
; CHECK-RV64-NEXT: j .LBB61_557
; CHECK-RV64-NEXT: .LBB61_31: # %else118
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bgez a2, .LBB61_32
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bgez a1, .LBB61_32
; CHECK-RV64-NEXT: j .LBB61_558
; CHECK-RV64-NEXT: .LBB61_32: # %else122
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bgez a2, .LBB61_33
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bgez a1, .LBB61_33
; CHECK-RV64-NEXT: j .LBB61_559
; CHECK-RV64-NEXT: .LBB61_33: # %else126
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bgez a2, .LBB61_34
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bgez a1, .LBB61_34
; CHECK-RV64-NEXT: j .LBB61_560
; CHECK-RV64-NEXT: .LBB61_34: # %else130
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bgez a2, .LBB61_35
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bgez a1, .LBB61_35
; CHECK-RV64-NEXT: j .LBB61_561
; CHECK-RV64-NEXT: .LBB61_35: # %else134
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bgez a2, .LBB61_36
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bgez a1, .LBB61_36
; CHECK-RV64-NEXT: j .LBB61_562
; CHECK-RV64-NEXT: .LBB61_36: # %else138
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bgez a2, .LBB61_37
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bgez a1, .LBB61_37
; CHECK-RV64-NEXT: j .LBB61_563
; CHECK-RV64-NEXT: .LBB61_37: # %else142
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bgez a2, .LBB61_38
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bgez a1, .LBB61_38
; CHECK-RV64-NEXT: j .LBB61_564
; CHECK-RV64-NEXT: .LBB61_38: # %else146
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bgez a2, .LBB61_39
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bgez a1, .LBB61_39
; CHECK-RV64-NEXT: j .LBB61_565
; CHECK-RV64-NEXT: .LBB61_39: # %else150
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bgez a2, .LBB61_40
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bgez a1, .LBB61_40
; CHECK-RV64-NEXT: j .LBB61_566
; CHECK-RV64-NEXT: .LBB61_40: # %else154
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bgez a2, .LBB61_41
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bgez a1, .LBB61_41
; CHECK-RV64-NEXT: j .LBB61_567
; CHECK-RV64-NEXT: .LBB61_41: # %else158
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bgez a2, .LBB61_42
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bgez a1, .LBB61_42
; CHECK-RV64-NEXT: j .LBB61_568
; CHECK-RV64-NEXT: .LBB61_42: # %else162
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bgez a2, .LBB61_43
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bgez a1, .LBB61_43
; CHECK-RV64-NEXT: j .LBB61_569
; CHECK-RV64-NEXT: .LBB61_43: # %else166
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bgez a2, .LBB61_44
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bgez a1, .LBB61_44
; CHECK-RV64-NEXT: j .LBB61_570
; CHECK-RV64-NEXT: .LBB61_44: # %else170
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bgez a2, .LBB61_45
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bgez a1, .LBB61_45
; CHECK-RV64-NEXT: j .LBB61_571
; CHECK-RV64-NEXT: .LBB61_45: # %else174
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bgez a2, .LBB61_46
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bgez a1, .LBB61_46
; CHECK-RV64-NEXT: j .LBB61_572
; CHECK-RV64-NEXT: .LBB61_46: # %else178
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bgez a2, .LBB61_47
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bgez a1, .LBB61_47
; CHECK-RV64-NEXT: j .LBB61_573
; CHECK-RV64-NEXT: .LBB61_47: # %else182
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_48
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_48
; CHECK-RV64-NEXT: j .LBB61_574
; CHECK-RV64-NEXT: .LBB61_48: # %else186
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bgez a2, .LBB61_49
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bgez a1, .LBB61_49
; CHECK-RV64-NEXT: j .LBB61_575
; CHECK-RV64-NEXT: .LBB61_49: # %else190
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bgez a2, .LBB61_50
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bgez a1, .LBB61_50
; CHECK-RV64-NEXT: j .LBB61_576
; CHECK-RV64-NEXT: .LBB61_50: # %else194
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bgez a2, .LBB61_51
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bgez a1, .LBB61_51
; CHECK-RV64-NEXT: j .LBB61_577
; CHECK-RV64-NEXT: .LBB61_51: # %else198
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bgez a2, .LBB61_52
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bgez a1, .LBB61_52
; CHECK-RV64-NEXT: j .LBB61_578
; CHECK-RV64-NEXT: .LBB61_52: # %else202
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bgez a2, .LBB61_53
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bgez a1, .LBB61_53
; CHECK-RV64-NEXT: j .LBB61_579
; CHECK-RV64-NEXT: .LBB61_53: # %else206
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bgez a2, .LBB61_54
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bgez a1, .LBB61_54
; CHECK-RV64-NEXT: j .LBB61_580
; CHECK-RV64-NEXT: .LBB61_54: # %else210
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bgez a2, .LBB61_55
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bgez a1, .LBB61_55
; CHECK-RV64-NEXT: j .LBB61_581
; CHECK-RV64-NEXT: .LBB61_55: # %else214
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bgez a2, .LBB61_56
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bgez a1, .LBB61_56
; CHECK-RV64-NEXT: j .LBB61_582
; CHECK-RV64-NEXT: .LBB61_56: # %else218
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bgez a2, .LBB61_57
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bgez a1, .LBB61_57
; CHECK-RV64-NEXT: j .LBB61_583
; CHECK-RV64-NEXT: .LBB61_57: # %else222
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bgez a2, .LBB61_58
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bgez a1, .LBB61_58
; CHECK-RV64-NEXT: j .LBB61_584
; CHECK-RV64-NEXT: .LBB61_58: # %else226
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bgez a2, .LBB61_59
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bgez a1, .LBB61_59
; CHECK-RV64-NEXT: j .LBB61_585
; CHECK-RV64-NEXT: .LBB61_59: # %else230
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bgez a2, .LBB61_60
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bgez a1, .LBB61_60
; CHECK-RV64-NEXT: j .LBB61_586
; CHECK-RV64-NEXT: .LBB61_60: # %else234
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bgez a2, .LBB61_61
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bgez a1, .LBB61_61
; CHECK-RV64-NEXT: j .LBB61_587
; CHECK-RV64-NEXT: .LBB61_61: # %else238
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_63
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_63
; CHECK-RV64-NEXT: .LBB61_62: # %cond.load241
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 62
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 61
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 61
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_63: # %else242
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 1
-; CHECK-RV64-NEXT: bgez a2, .LBB61_65
+; CHECK-RV64-NEXT: slli a1, a2, 1
+; CHECK-RV64-NEXT: bgez a1, .LBB61_65
; CHECK-RV64-NEXT: # %bb.64: # %cond.load245
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v17, a2
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v17, a1
; CHECK-RV64-NEXT: vmv1r.v v18, v8
-; CHECK-RV64-NEXT: li a2, 63
+; CHECK-RV64-NEXT: li a1, 63
; CHECK-RV64-NEXT: li a3, 62
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m1, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v18, v17, a3
; CHECK-RV64-NEXT: vmv1r.v v8, v18
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_65: # %else246
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a2, v16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_66
+; CHECK-RV64-NEXT: vmv.x.s a1, v16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_66
; CHECK-RV64-NEXT: j .LBB61_588
; CHECK-RV64-NEXT: .LBB61_66: # %else250
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: beqz a1, .LBB61_67
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: beqz a2, .LBB61_67
; CHECK-RV64-NEXT: j .LBB61_589
; CHECK-RV64-NEXT: .LBB61_67: # %else254
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: beqz a1, .LBB61_68
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: beqz a2, .LBB61_68
; CHECK-RV64-NEXT: j .LBB61_590
; CHECK-RV64-NEXT: .LBB61_68: # %else258
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: beqz a1, .LBB61_69
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: beqz a2, .LBB61_69
; CHECK-RV64-NEXT: j .LBB61_591
; CHECK-RV64-NEXT: .LBB61_69: # %else262
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: beqz a1, .LBB61_70
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: beqz a2, .LBB61_70
; CHECK-RV64-NEXT: j .LBB61_592
; CHECK-RV64-NEXT: .LBB61_70: # %else266
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: beqz a1, .LBB61_71
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: beqz a2, .LBB61_71
; CHECK-RV64-NEXT: j .LBB61_593
; CHECK-RV64-NEXT: .LBB61_71: # %else270
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: beqz a1, .LBB61_72
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: beqz a2, .LBB61_72
; CHECK-RV64-NEXT: j .LBB61_594
; CHECK-RV64-NEXT: .LBB61_72: # %else274
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: beqz a1, .LBB61_73
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: beqz a2, .LBB61_73
; CHECK-RV64-NEXT: j .LBB61_595
; CHECK-RV64-NEXT: .LBB61_73: # %else278
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: beqz a1, .LBB61_74
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: beqz a2, .LBB61_74
; CHECK-RV64-NEXT: j .LBB61_596
; CHECK-RV64-NEXT: .LBB61_74: # %else282
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: beqz a1, .LBB61_75
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: beqz a2, .LBB61_75
; CHECK-RV64-NEXT: j .LBB61_597
; CHECK-RV64-NEXT: .LBB61_75: # %else286
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: beqz a1, .LBB61_76
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: beqz a2, .LBB61_76
; CHECK-RV64-NEXT: j .LBB61_598
; CHECK-RV64-NEXT: .LBB61_76: # %else290
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: beqz a1, .LBB61_77
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: beqz a2, .LBB61_77
; CHECK-RV64-NEXT: j .LBB61_599
; CHECK-RV64-NEXT: .LBB61_77: # %else294
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bgez a1, .LBB61_78
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bgez a2, .LBB61_78
; CHECK-RV64-NEXT: j .LBB61_600
; CHECK-RV64-NEXT: .LBB61_78: # %else298
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bgez a1, .LBB61_79
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bgez a2, .LBB61_79
; CHECK-RV64-NEXT: j .LBB61_601
; CHECK-RV64-NEXT: .LBB61_79: # %else302
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bgez a1, .LBB61_80
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bgez a2, .LBB61_80
; CHECK-RV64-NEXT: j .LBB61_602
; CHECK-RV64-NEXT: .LBB61_80: # %else306
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bgez a1, .LBB61_81
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bgez a2, .LBB61_81
; CHECK-RV64-NEXT: j .LBB61_603
; CHECK-RV64-NEXT: .LBB61_81: # %else310
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bgez a1, .LBB61_82
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bgez a2, .LBB61_82
; CHECK-RV64-NEXT: j .LBB61_604
; CHECK-RV64-NEXT: .LBB61_82: # %else314
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bgez a1, .LBB61_83
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bgez a2, .LBB61_83
; CHECK-RV64-NEXT: j .LBB61_605
; CHECK-RV64-NEXT: .LBB61_83: # %else318
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bgez a1, .LBB61_84
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bgez a2, .LBB61_84
; CHECK-RV64-NEXT: j .LBB61_606
; CHECK-RV64-NEXT: .LBB61_84: # %else322
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bgez a1, .LBB61_85
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bgez a2, .LBB61_85
; CHECK-RV64-NEXT: j .LBB61_607
; CHECK-RV64-NEXT: .LBB61_85: # %else326
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bgez a1, .LBB61_86
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bgez a2, .LBB61_86
; CHECK-RV64-NEXT: j .LBB61_608
; CHECK-RV64-NEXT: .LBB61_86: # %else330
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bgez a1, .LBB61_87
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bgez a2, .LBB61_87
; CHECK-RV64-NEXT: j .LBB61_609
; CHECK-RV64-NEXT: .LBB61_87: # %else334
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bgez a1, .LBB61_88
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bgez a2, .LBB61_88
; CHECK-RV64-NEXT: j .LBB61_610
; CHECK-RV64-NEXT: .LBB61_88: # %else338
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bgez a1, .LBB61_89
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bgez a2, .LBB61_89
; CHECK-RV64-NEXT: j .LBB61_611
; CHECK-RV64-NEXT: .LBB61_89: # %else342
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bgez a1, .LBB61_90
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bgez a2, .LBB61_90
; CHECK-RV64-NEXT: j .LBB61_612
; CHECK-RV64-NEXT: .LBB61_90: # %else346
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bgez a1, .LBB61_91
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bgez a2, .LBB61_91
; CHECK-RV64-NEXT: j .LBB61_613
; CHECK-RV64-NEXT: .LBB61_91: # %else350
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bgez a1, .LBB61_92
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bgez a2, .LBB61_92
; CHECK-RV64-NEXT: j .LBB61_614
; CHECK-RV64-NEXT: .LBB61_92: # %else354
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bgez a1, .LBB61_93
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bgez a2, .LBB61_93
; CHECK-RV64-NEXT: j .LBB61_615
; CHECK-RV64-NEXT: .LBB61_93: # %else358
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bgez a1, .LBB61_94
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bgez a2, .LBB61_94
; CHECK-RV64-NEXT: j .LBB61_616
; CHECK-RV64-NEXT: .LBB61_94: # %else362
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bgez a1, .LBB61_95
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bgez a2, .LBB61_95
; CHECK-RV64-NEXT: j .LBB61_617
; CHECK-RV64-NEXT: .LBB61_95: # %else366
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bgez a1, .LBB61_96
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bgez a2, .LBB61_96
; CHECK-RV64-NEXT: j .LBB61_618
; CHECK-RV64-NEXT: .LBB61_96: # %else370
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bgez a1, .LBB61_97
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bgez a2, .LBB61_97
; CHECK-RV64-NEXT: j .LBB61_619
; CHECK-RV64-NEXT: .LBB61_97: # %else374
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bgez a1, .LBB61_98
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bgez a2, .LBB61_98
; CHECK-RV64-NEXT: j .LBB61_620
; CHECK-RV64-NEXT: .LBB61_98: # %else378
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bgez a1, .LBB61_99
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bgez a2, .LBB61_99
; CHECK-RV64-NEXT: j .LBB61_621
; CHECK-RV64-NEXT: .LBB61_99: # %else382
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bgez a1, .LBB61_100
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bgez a2, .LBB61_100
; CHECK-RV64-NEXT: j .LBB61_622
; CHECK-RV64-NEXT: .LBB61_100: # %else386
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bgez a1, .LBB61_101
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bgez a2, .LBB61_101
; CHECK-RV64-NEXT: j .LBB61_623
; CHECK-RV64-NEXT: .LBB61_101: # %else390
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bgez a1, .LBB61_102
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bgez a2, .LBB61_102
; CHECK-RV64-NEXT: j .LBB61_624
; CHECK-RV64-NEXT: .LBB61_102: # %else394
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bgez a1, .LBB61_103
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bgez a2, .LBB61_103
; CHECK-RV64-NEXT: j .LBB61_625
; CHECK-RV64-NEXT: .LBB61_103: # %else398
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bgez a1, .LBB61_104
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bgez a2, .LBB61_104
; CHECK-RV64-NEXT: j .LBB61_626
; CHECK-RV64-NEXT: .LBB61_104: # %else402
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bgez a1, .LBB61_105
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bgez a2, .LBB61_105
; CHECK-RV64-NEXT: j .LBB61_627
; CHECK-RV64-NEXT: .LBB61_105: # %else406
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bgez a1, .LBB61_106
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bgez a2, .LBB61_106
; CHECK-RV64-NEXT: j .LBB61_628
; CHECK-RV64-NEXT: .LBB61_106: # %else410
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bgez a1, .LBB61_107
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bgez a2, .LBB61_107
; CHECK-RV64-NEXT: j .LBB61_629
; CHECK-RV64-NEXT: .LBB61_107: # %else414
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bgez a1, .LBB61_108
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bgez a2, .LBB61_108
; CHECK-RV64-NEXT: j .LBB61_630
; CHECK-RV64-NEXT: .LBB61_108: # %else418
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bgez a1, .LBB61_109
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bgez a2, .LBB61_109
; CHECK-RV64-NEXT: j .LBB61_631
; CHECK-RV64-NEXT: .LBB61_109: # %else422
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bgez a1, .LBB61_110
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bgez a2, .LBB61_110
; CHECK-RV64-NEXT: j .LBB61_632
; CHECK-RV64-NEXT: .LBB61_110: # %else426
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bgez a1, .LBB61_111
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bgez a2, .LBB61_111
; CHECK-RV64-NEXT: j .LBB61_633
; CHECK-RV64-NEXT: .LBB61_111: # %else430
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bgez a1, .LBB61_112
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bgez a2, .LBB61_112
; CHECK-RV64-NEXT: j .LBB61_634
; CHECK-RV64-NEXT: .LBB61_112: # %else434
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bgez a1, .LBB61_113
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bgez a2, .LBB61_113
; CHECK-RV64-NEXT: j .LBB61_635
; CHECK-RV64-NEXT: .LBB61_113: # %else438
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_114
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_114
; CHECK-RV64-NEXT: j .LBB61_636
; CHECK-RV64-NEXT: .LBB61_114: # %else442
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bgez a1, .LBB61_115
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bgez a2, .LBB61_115
; CHECK-RV64-NEXT: j .LBB61_637
; CHECK-RV64-NEXT: .LBB61_115: # %else446
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bgez a1, .LBB61_116
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bgez a2, .LBB61_116
; CHECK-RV64-NEXT: j .LBB61_638
; CHECK-RV64-NEXT: .LBB61_116: # %else450
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bgez a1, .LBB61_117
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bgez a2, .LBB61_117
; CHECK-RV64-NEXT: j .LBB61_639
; CHECK-RV64-NEXT: .LBB61_117: # %else454
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bgez a1, .LBB61_118
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bgez a2, .LBB61_118
; CHECK-RV64-NEXT: j .LBB61_640
; CHECK-RV64-NEXT: .LBB61_118: # %else458
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bgez a1, .LBB61_119
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bgez a2, .LBB61_119
; CHECK-RV64-NEXT: j .LBB61_641
; CHECK-RV64-NEXT: .LBB61_119: # %else462
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bgez a1, .LBB61_120
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bgez a2, .LBB61_120
; CHECK-RV64-NEXT: j .LBB61_642
; CHECK-RV64-NEXT: .LBB61_120: # %else466
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bgez a1, .LBB61_121
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bgez a2, .LBB61_121
; CHECK-RV64-NEXT: j .LBB61_643
; CHECK-RV64-NEXT: .LBB61_121: # %else470
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bgez a1, .LBB61_122
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bgez a2, .LBB61_122
; CHECK-RV64-NEXT: j .LBB61_644
; CHECK-RV64-NEXT: .LBB61_122: # %else474
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bgez a1, .LBB61_123
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bgez a2, .LBB61_123
; CHECK-RV64-NEXT: j .LBB61_645
; CHECK-RV64-NEXT: .LBB61_123: # %else478
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bgez a1, .LBB61_124
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bgez a2, .LBB61_124
; CHECK-RV64-NEXT: j .LBB61_646
; CHECK-RV64-NEXT: .LBB61_124: # %else482
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bgez a1, .LBB61_125
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bgez a2, .LBB61_125
; CHECK-RV64-NEXT: j .LBB61_647
; CHECK-RV64-NEXT: .LBB61_125: # %else486
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bgez a1, .LBB61_126
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bgez a2, .LBB61_126
; CHECK-RV64-NEXT: j .LBB61_648
; CHECK-RV64-NEXT: .LBB61_126: # %else490
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bgez a1, .LBB61_127
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bgez a2, .LBB61_127
; CHECK-RV64-NEXT: j .LBB61_649
; CHECK-RV64-NEXT: .LBB61_127: # %else494
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_129
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_129
; CHECK-RV64-NEXT: .LBB61_128: # %cond.load497
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 126
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 125
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 125
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_129: # %else498
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-RV64-NEXT: slli a1, a2, 1
-; CHECK-RV64-NEXT: bgez a1, .LBB61_131
+; CHECK-RV64-NEXT: slli a2, a1, 1
+; CHECK-RV64-NEXT: bgez a2, .LBB61_131
; CHECK-RV64-NEXT: # %bb.130: # %cond.load501
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: vmv2r.v v18, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 127
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 127
; CHECK-RV64-NEXT: li a3, 126
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m2, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v18, v20, a3
; CHECK-RV64-NEXT: vmv2r.v v8, v18
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_131: # %else502
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_132
+; CHECK-RV64-NEXT: vmv.x.s a2, v16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_132
; CHECK-RV64-NEXT: j .LBB61_650
; CHECK-RV64-NEXT: .LBB61_132: # %else506
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: beqz a2, .LBB61_133
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: beqz a1, .LBB61_133
; CHECK-RV64-NEXT: j .LBB61_651
; CHECK-RV64-NEXT: .LBB61_133: # %else510
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: beqz a2, .LBB61_134
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: beqz a1, .LBB61_134
; CHECK-RV64-NEXT: j .LBB61_652
; CHECK-RV64-NEXT: .LBB61_134: # %else514
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: beqz a2, .LBB61_135
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: beqz a1, .LBB61_135
; CHECK-RV64-NEXT: j .LBB61_653
; CHECK-RV64-NEXT: .LBB61_135: # %else518
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: beqz a2, .LBB61_136
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: beqz a1, .LBB61_136
; CHECK-RV64-NEXT: j .LBB61_654
; CHECK-RV64-NEXT: .LBB61_136: # %else522
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: beqz a2, .LBB61_137
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: beqz a1, .LBB61_137
; CHECK-RV64-NEXT: j .LBB61_655
; CHECK-RV64-NEXT: .LBB61_137: # %else526
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: beqz a2, .LBB61_138
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: beqz a1, .LBB61_138
; CHECK-RV64-NEXT: j .LBB61_656
; CHECK-RV64-NEXT: .LBB61_138: # %else530
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: beqz a2, .LBB61_139
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: beqz a1, .LBB61_139
; CHECK-RV64-NEXT: j .LBB61_657
; CHECK-RV64-NEXT: .LBB61_139: # %else534
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: beqz a2, .LBB61_140
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: beqz a1, .LBB61_140
; CHECK-RV64-NEXT: j .LBB61_658
; CHECK-RV64-NEXT: .LBB61_140: # %else538
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: beqz a2, .LBB61_141
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: beqz a1, .LBB61_141
; CHECK-RV64-NEXT: j .LBB61_659
; CHECK-RV64-NEXT: .LBB61_141: # %else542
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: beqz a2, .LBB61_142
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: beqz a1, .LBB61_142
; CHECK-RV64-NEXT: j .LBB61_660
; CHECK-RV64-NEXT: .LBB61_142: # %else546
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: beqz a2, .LBB61_143
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: beqz a1, .LBB61_143
; CHECK-RV64-NEXT: j .LBB61_661
; CHECK-RV64-NEXT: .LBB61_143: # %else550
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bgez a2, .LBB61_144
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bgez a1, .LBB61_144
; CHECK-RV64-NEXT: j .LBB61_662
; CHECK-RV64-NEXT: .LBB61_144: # %else554
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bgez a2, .LBB61_145
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bgez a1, .LBB61_145
; CHECK-RV64-NEXT: j .LBB61_663
; CHECK-RV64-NEXT: .LBB61_145: # %else558
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bgez a2, .LBB61_146
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bgez a1, .LBB61_146
; CHECK-RV64-NEXT: j .LBB61_664
; CHECK-RV64-NEXT: .LBB61_146: # %else562
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bgez a2, .LBB61_147
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bgez a1, .LBB61_147
; CHECK-RV64-NEXT: j .LBB61_665
; CHECK-RV64-NEXT: .LBB61_147: # %else566
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bgez a2, .LBB61_148
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bgez a1, .LBB61_148
; CHECK-RV64-NEXT: j .LBB61_666
; CHECK-RV64-NEXT: .LBB61_148: # %else570
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bgez a2, .LBB61_149
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bgez a1, .LBB61_149
; CHECK-RV64-NEXT: j .LBB61_667
; CHECK-RV64-NEXT: .LBB61_149: # %else574
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bgez a2, .LBB61_150
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bgez a1, .LBB61_150
; CHECK-RV64-NEXT: j .LBB61_668
; CHECK-RV64-NEXT: .LBB61_150: # %else578
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bgez a2, .LBB61_151
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bgez a1, .LBB61_151
; CHECK-RV64-NEXT: j .LBB61_669
; CHECK-RV64-NEXT: .LBB61_151: # %else582
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bgez a2, .LBB61_152
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bgez a1, .LBB61_152
; CHECK-RV64-NEXT: j .LBB61_670
; CHECK-RV64-NEXT: .LBB61_152: # %else586
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bgez a2, .LBB61_153
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bgez a1, .LBB61_153
; CHECK-RV64-NEXT: j .LBB61_671
; CHECK-RV64-NEXT: .LBB61_153: # %else590
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bgez a2, .LBB61_154
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bgez a1, .LBB61_154
; CHECK-RV64-NEXT: j .LBB61_672
; CHECK-RV64-NEXT: .LBB61_154: # %else594
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bgez a2, .LBB61_155
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bgez a1, .LBB61_155
; CHECK-RV64-NEXT: j .LBB61_673
; CHECK-RV64-NEXT: .LBB61_155: # %else598
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bgez a2, .LBB61_156
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bgez a1, .LBB61_156
; CHECK-RV64-NEXT: j .LBB61_674
; CHECK-RV64-NEXT: .LBB61_156: # %else602
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bgez a2, .LBB61_157
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bgez a1, .LBB61_157
; CHECK-RV64-NEXT: j .LBB61_675
; CHECK-RV64-NEXT: .LBB61_157: # %else606
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bgez a2, .LBB61_158
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bgez a1, .LBB61_158
; CHECK-RV64-NEXT: j .LBB61_676
; CHECK-RV64-NEXT: .LBB61_158: # %else610
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bgez a2, .LBB61_159
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bgez a1, .LBB61_159
; CHECK-RV64-NEXT: j .LBB61_677
; CHECK-RV64-NEXT: .LBB61_159: # %else614
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bgez a2, .LBB61_160
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bgez a1, .LBB61_160
; CHECK-RV64-NEXT: j .LBB61_678
; CHECK-RV64-NEXT: .LBB61_160: # %else618
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bgez a2, .LBB61_161
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bgez a1, .LBB61_161
; CHECK-RV64-NEXT: j .LBB61_679
; CHECK-RV64-NEXT: .LBB61_161: # %else622
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bgez a2, .LBB61_162
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bgez a1, .LBB61_162
; CHECK-RV64-NEXT: j .LBB61_680
; CHECK-RV64-NEXT: .LBB61_162: # %else626
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bgez a2, .LBB61_163
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bgez a1, .LBB61_163
; CHECK-RV64-NEXT: j .LBB61_681
; CHECK-RV64-NEXT: .LBB61_163: # %else630
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bgez a2, .LBB61_164
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bgez a1, .LBB61_164
; CHECK-RV64-NEXT: j .LBB61_682
; CHECK-RV64-NEXT: .LBB61_164: # %else634
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bgez a2, .LBB61_165
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bgez a1, .LBB61_165
; CHECK-RV64-NEXT: j .LBB61_683
; CHECK-RV64-NEXT: .LBB61_165: # %else638
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bgez a2, .LBB61_166
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bgez a1, .LBB61_166
; CHECK-RV64-NEXT: j .LBB61_684
; CHECK-RV64-NEXT: .LBB61_166: # %else642
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bgez a2, .LBB61_167
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bgez a1, .LBB61_167
; CHECK-RV64-NEXT: j .LBB61_685
; CHECK-RV64-NEXT: .LBB61_167: # %else646
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bgez a2, .LBB61_168
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bgez a1, .LBB61_168
; CHECK-RV64-NEXT: j .LBB61_686
; CHECK-RV64-NEXT: .LBB61_168: # %else650
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bgez a2, .LBB61_169
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bgez a1, .LBB61_169
; CHECK-RV64-NEXT: j .LBB61_687
; CHECK-RV64-NEXT: .LBB61_169: # %else654
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bgez a2, .LBB61_170
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bgez a1, .LBB61_170
; CHECK-RV64-NEXT: j .LBB61_688
; CHECK-RV64-NEXT: .LBB61_170: # %else658
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bgez a2, .LBB61_171
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bgez a1, .LBB61_171
; CHECK-RV64-NEXT: j .LBB61_689
; CHECK-RV64-NEXT: .LBB61_171: # %else662
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bgez a2, .LBB61_172
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bgez a1, .LBB61_172
; CHECK-RV64-NEXT: j .LBB61_690
; CHECK-RV64-NEXT: .LBB61_172: # %else666
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bgez a2, .LBB61_173
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bgez a1, .LBB61_173
; CHECK-RV64-NEXT: j .LBB61_691
; CHECK-RV64-NEXT: .LBB61_173: # %else670
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bgez a2, .LBB61_174
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bgez a1, .LBB61_174
; CHECK-RV64-NEXT: j .LBB61_692
; CHECK-RV64-NEXT: .LBB61_174: # %else674
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bgez a2, .LBB61_175
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bgez a1, .LBB61_175
; CHECK-RV64-NEXT: j .LBB61_693
; CHECK-RV64-NEXT: .LBB61_175: # %else678
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bgez a2, .LBB61_176
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bgez a1, .LBB61_176
; CHECK-RV64-NEXT: j .LBB61_694
; CHECK-RV64-NEXT: .LBB61_176: # %else682
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bgez a2, .LBB61_177
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bgez a1, .LBB61_177
; CHECK-RV64-NEXT: j .LBB61_695
; CHECK-RV64-NEXT: .LBB61_177: # %else686
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bgez a2, .LBB61_178
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bgez a1, .LBB61_178
; CHECK-RV64-NEXT: j .LBB61_696
; CHECK-RV64-NEXT: .LBB61_178: # %else690
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bgez a2, .LBB61_179
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bgez a1, .LBB61_179
; CHECK-RV64-NEXT: j .LBB61_697
; CHECK-RV64-NEXT: .LBB61_179: # %else694
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_180
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_180
; CHECK-RV64-NEXT: j .LBB61_698
; CHECK-RV64-NEXT: .LBB61_180: # %else698
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bgez a2, .LBB61_181
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bgez a1, .LBB61_181
; CHECK-RV64-NEXT: j .LBB61_699
; CHECK-RV64-NEXT: .LBB61_181: # %else702
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bgez a2, .LBB61_182
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bgez a1, .LBB61_182
; CHECK-RV64-NEXT: j .LBB61_700
; CHECK-RV64-NEXT: .LBB61_182: # %else706
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bgez a2, .LBB61_183
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bgez a1, .LBB61_183
; CHECK-RV64-NEXT: j .LBB61_701
; CHECK-RV64-NEXT: .LBB61_183: # %else710
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bgez a2, .LBB61_184
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bgez a1, .LBB61_184
; CHECK-RV64-NEXT: j .LBB61_702
; CHECK-RV64-NEXT: .LBB61_184: # %else714
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bgez a2, .LBB61_185
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bgez a1, .LBB61_185
; CHECK-RV64-NEXT: j .LBB61_703
; CHECK-RV64-NEXT: .LBB61_185: # %else718
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bgez a2, .LBB61_186
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bgez a1, .LBB61_186
; CHECK-RV64-NEXT: j .LBB61_704
; CHECK-RV64-NEXT: .LBB61_186: # %else722
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bgez a2, .LBB61_187
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bgez a1, .LBB61_187
; CHECK-RV64-NEXT: j .LBB61_705
; CHECK-RV64-NEXT: .LBB61_187: # %else726
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bgez a2, .LBB61_188
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bgez a1, .LBB61_188
; CHECK-RV64-NEXT: j .LBB61_706
; CHECK-RV64-NEXT: .LBB61_188: # %else730
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bgez a2, .LBB61_189
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bgez a1, .LBB61_189
; CHECK-RV64-NEXT: j .LBB61_707
; CHECK-RV64-NEXT: .LBB61_189: # %else734
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bgez a2, .LBB61_190
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bgez a1, .LBB61_190
; CHECK-RV64-NEXT: j .LBB61_708
; CHECK-RV64-NEXT: .LBB61_190: # %else738
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bgez a2, .LBB61_191
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bgez a1, .LBB61_191
; CHECK-RV64-NEXT: j .LBB61_709
; CHECK-RV64-NEXT: .LBB61_191: # %else742
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bgez a2, .LBB61_192
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bgez a1, .LBB61_192
; CHECK-RV64-NEXT: j .LBB61_710
; CHECK-RV64-NEXT: .LBB61_192: # %else746
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bgez a2, .LBB61_193
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bgez a1, .LBB61_193
; CHECK-RV64-NEXT: j .LBB61_711
; CHECK-RV64-NEXT: .LBB61_193: # %else750
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_195
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_195
; CHECK-RV64-NEXT: .LBB61_194: # %cond.load753
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 190
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 189
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 189
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_195: # %else754
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 3
-; CHECK-RV64-NEXT: slli a2, a1, 1
-; CHECK-RV64-NEXT: bgez a2, .LBB61_197
+; CHECK-RV64-NEXT: slli a1, a2, 1
+; CHECK-RV64-NEXT: bgez a1, .LBB61_197
; CHECK-RV64-NEXT: # %bb.196: # %cond.load757
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vmv4r.v v20, v8
-; CHECK-RV64-NEXT: vmv.s.x v24, a2
-; CHECK-RV64-NEXT: li a2, 191
+; CHECK-RV64-NEXT: vmv.s.x v24, a1
+; CHECK-RV64-NEXT: li a1, 191
; CHECK-RV64-NEXT: li a3, 190
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v20, v24, a3
; CHECK-RV64-NEXT: vmv4r.v v8, v20
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_197: # %else758
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a2, v16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_198
+; CHECK-RV64-NEXT: vmv.x.s a1, v16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_198
; CHECK-RV64-NEXT: j .LBB61_712
; CHECK-RV64-NEXT: .LBB61_198: # %else762
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: beqz a1, .LBB61_199
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: beqz a2, .LBB61_199
; CHECK-RV64-NEXT: j .LBB61_713
; CHECK-RV64-NEXT: .LBB61_199: # %else766
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: beqz a1, .LBB61_200
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: beqz a2, .LBB61_200
; CHECK-RV64-NEXT: j .LBB61_714
; CHECK-RV64-NEXT: .LBB61_200: # %else770
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: beqz a1, .LBB61_201
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: beqz a2, .LBB61_201
; CHECK-RV64-NEXT: j .LBB61_715
; CHECK-RV64-NEXT: .LBB61_201: # %else774
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: beqz a1, .LBB61_202
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: beqz a2, .LBB61_202
; CHECK-RV64-NEXT: j .LBB61_716
; CHECK-RV64-NEXT: .LBB61_202: # %else778
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: beqz a1, .LBB61_203
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: beqz a2, .LBB61_203
; CHECK-RV64-NEXT: j .LBB61_717
; CHECK-RV64-NEXT: .LBB61_203: # %else782
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: beqz a1, .LBB61_204
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: beqz a2, .LBB61_204
; CHECK-RV64-NEXT: j .LBB61_718
; CHECK-RV64-NEXT: .LBB61_204: # %else786
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: beqz a1, .LBB61_205
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: beqz a2, .LBB61_205
; CHECK-RV64-NEXT: j .LBB61_719
; CHECK-RV64-NEXT: .LBB61_205: # %else790
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: beqz a1, .LBB61_206
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: beqz a2, .LBB61_206
; CHECK-RV64-NEXT: j .LBB61_720
; CHECK-RV64-NEXT: .LBB61_206: # %else794
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: beqz a1, .LBB61_207
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: beqz a2, .LBB61_207
; CHECK-RV64-NEXT: j .LBB61_721
; CHECK-RV64-NEXT: .LBB61_207: # %else798
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: beqz a1, .LBB61_208
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: beqz a2, .LBB61_208
; CHECK-RV64-NEXT: j .LBB61_722
; CHECK-RV64-NEXT: .LBB61_208: # %else802
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: beqz a1, .LBB61_209
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: beqz a2, .LBB61_209
; CHECK-RV64-NEXT: j .LBB61_723
; CHECK-RV64-NEXT: .LBB61_209: # %else806
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bgez a1, .LBB61_210
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bgez a2, .LBB61_210
; CHECK-RV64-NEXT: j .LBB61_724
; CHECK-RV64-NEXT: .LBB61_210: # %else810
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bgez a1, .LBB61_211
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bgez a2, .LBB61_211
; CHECK-RV64-NEXT: j .LBB61_725
; CHECK-RV64-NEXT: .LBB61_211: # %else814
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bgez a1, .LBB61_212
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bgez a2, .LBB61_212
; CHECK-RV64-NEXT: j .LBB61_726
; CHECK-RV64-NEXT: .LBB61_212: # %else818
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bgez a1, .LBB61_213
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bgez a2, .LBB61_213
; CHECK-RV64-NEXT: j .LBB61_727
; CHECK-RV64-NEXT: .LBB61_213: # %else822
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bgez a1, .LBB61_214
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bgez a2, .LBB61_214
; CHECK-RV64-NEXT: j .LBB61_728
; CHECK-RV64-NEXT: .LBB61_214: # %else826
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bgez a1, .LBB61_215
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bgez a2, .LBB61_215
; CHECK-RV64-NEXT: j .LBB61_729
; CHECK-RV64-NEXT: .LBB61_215: # %else830
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bgez a1, .LBB61_216
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bgez a2, .LBB61_216
; CHECK-RV64-NEXT: j .LBB61_730
; CHECK-RV64-NEXT: .LBB61_216: # %else834
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bgez a1, .LBB61_217
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bgez a2, .LBB61_217
; CHECK-RV64-NEXT: j .LBB61_731
; CHECK-RV64-NEXT: .LBB61_217: # %else838
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bgez a1, .LBB61_218
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bgez a2, .LBB61_218
; CHECK-RV64-NEXT: j .LBB61_732
; CHECK-RV64-NEXT: .LBB61_218: # %else842
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bgez a1, .LBB61_219
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bgez a2, .LBB61_219
; CHECK-RV64-NEXT: j .LBB61_733
; CHECK-RV64-NEXT: .LBB61_219: # %else846
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bgez a1, .LBB61_220
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bgez a2, .LBB61_220
; CHECK-RV64-NEXT: j .LBB61_734
; CHECK-RV64-NEXT: .LBB61_220: # %else850
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bgez a1, .LBB61_221
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bgez a2, .LBB61_221
; CHECK-RV64-NEXT: j .LBB61_735
; CHECK-RV64-NEXT: .LBB61_221: # %else854
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bgez a1, .LBB61_222
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bgez a2, .LBB61_222
; CHECK-RV64-NEXT: j .LBB61_736
; CHECK-RV64-NEXT: .LBB61_222: # %else858
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bgez a1, .LBB61_223
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bgez a2, .LBB61_223
; CHECK-RV64-NEXT: j .LBB61_737
; CHECK-RV64-NEXT: .LBB61_223: # %else862
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bgez a1, .LBB61_224
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bgez a2, .LBB61_224
; CHECK-RV64-NEXT: j .LBB61_738
; CHECK-RV64-NEXT: .LBB61_224: # %else866
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bgez a1, .LBB61_225
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bgez a2, .LBB61_225
; CHECK-RV64-NEXT: j .LBB61_739
; CHECK-RV64-NEXT: .LBB61_225: # %else870
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bgez a1, .LBB61_226
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bgez a2, .LBB61_226
; CHECK-RV64-NEXT: j .LBB61_740
; CHECK-RV64-NEXT: .LBB61_226: # %else874
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bgez a1, .LBB61_227
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bgez a2, .LBB61_227
; CHECK-RV64-NEXT: j .LBB61_741
; CHECK-RV64-NEXT: .LBB61_227: # %else878
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bgez a1, .LBB61_228
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bgez a2, .LBB61_228
; CHECK-RV64-NEXT: j .LBB61_742
; CHECK-RV64-NEXT: .LBB61_228: # %else882
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bgez a1, .LBB61_229
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bgez a2, .LBB61_229
; CHECK-RV64-NEXT: j .LBB61_743
; CHECK-RV64-NEXT: .LBB61_229: # %else886
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bgez a1, .LBB61_230
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bgez a2, .LBB61_230
; CHECK-RV64-NEXT: j .LBB61_744
; CHECK-RV64-NEXT: .LBB61_230: # %else890
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bgez a1, .LBB61_231
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bgez a2, .LBB61_231
; CHECK-RV64-NEXT: j .LBB61_745
; CHECK-RV64-NEXT: .LBB61_231: # %else894
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bgez a1, .LBB61_232
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bgez a2, .LBB61_232
; CHECK-RV64-NEXT: j .LBB61_746
; CHECK-RV64-NEXT: .LBB61_232: # %else898
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bgez a1, .LBB61_233
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bgez a2, .LBB61_233
; CHECK-RV64-NEXT: j .LBB61_747
; CHECK-RV64-NEXT: .LBB61_233: # %else902
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bgez a1, .LBB61_234
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bgez a2, .LBB61_234
; CHECK-RV64-NEXT: j .LBB61_748
; CHECK-RV64-NEXT: .LBB61_234: # %else906
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bgez a1, .LBB61_235
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bgez a2, .LBB61_235
; CHECK-RV64-NEXT: j .LBB61_749
; CHECK-RV64-NEXT: .LBB61_235: # %else910
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bgez a1, .LBB61_236
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bgez a2, .LBB61_236
; CHECK-RV64-NEXT: j .LBB61_750
; CHECK-RV64-NEXT: .LBB61_236: # %else914
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bgez a1, .LBB61_237
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bgez a2, .LBB61_237
; CHECK-RV64-NEXT: j .LBB61_751
; CHECK-RV64-NEXT: .LBB61_237: # %else918
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bgez a1, .LBB61_238
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bgez a2, .LBB61_238
; CHECK-RV64-NEXT: j .LBB61_752
; CHECK-RV64-NEXT: .LBB61_238: # %else922
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bgez a1, .LBB61_239
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bgez a2, .LBB61_239
; CHECK-RV64-NEXT: j .LBB61_753
; CHECK-RV64-NEXT: .LBB61_239: # %else926
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bgez a1, .LBB61_240
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bgez a2, .LBB61_240
; CHECK-RV64-NEXT: j .LBB61_754
; CHECK-RV64-NEXT: .LBB61_240: # %else930
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bgez a1, .LBB61_241
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bgez a2, .LBB61_241
; CHECK-RV64-NEXT: j .LBB61_755
; CHECK-RV64-NEXT: .LBB61_241: # %else934
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bgez a1, .LBB61_242
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bgez a2, .LBB61_242
; CHECK-RV64-NEXT: j .LBB61_756
; CHECK-RV64-NEXT: .LBB61_242: # %else938
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bgez a1, .LBB61_243
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bgez a2, .LBB61_243
; CHECK-RV64-NEXT: j .LBB61_757
; CHECK-RV64-NEXT: .LBB61_243: # %else942
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bgez a1, .LBB61_244
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bgez a2, .LBB61_244
; CHECK-RV64-NEXT: j .LBB61_758
; CHECK-RV64-NEXT: .LBB61_244: # %else946
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bgez a1, .LBB61_245
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bgez a2, .LBB61_245
; CHECK-RV64-NEXT: j .LBB61_759
; CHECK-RV64-NEXT: .LBB61_245: # %else950
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_246
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_246
; CHECK-RV64-NEXT: j .LBB61_760
; CHECK-RV64-NEXT: .LBB61_246: # %else954
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bgez a1, .LBB61_247
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bgez a2, .LBB61_247
; CHECK-RV64-NEXT: j .LBB61_761
; CHECK-RV64-NEXT: .LBB61_247: # %else958
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bgez a1, .LBB61_248
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bgez a2, .LBB61_248
; CHECK-RV64-NEXT: j .LBB61_762
; CHECK-RV64-NEXT: .LBB61_248: # %else962
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bgez a1, .LBB61_249
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bgez a2, .LBB61_249
; CHECK-RV64-NEXT: j .LBB61_763
; CHECK-RV64-NEXT: .LBB61_249: # %else966
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bgez a1, .LBB61_250
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bgez a2, .LBB61_250
; CHECK-RV64-NEXT: j .LBB61_764
; CHECK-RV64-NEXT: .LBB61_250: # %else970
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bgez a1, .LBB61_251
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bgez a2, .LBB61_251
; CHECK-RV64-NEXT: j .LBB61_765
; CHECK-RV64-NEXT: .LBB61_251: # %else974
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bgez a1, .LBB61_252
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bgez a2, .LBB61_252
; CHECK-RV64-NEXT: j .LBB61_766
; CHECK-RV64-NEXT: .LBB61_252: # %else978
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bgez a1, .LBB61_253
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bgez a2, .LBB61_253
; CHECK-RV64-NEXT: j .LBB61_767
; CHECK-RV64-NEXT: .LBB61_253: # %else982
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bgez a1, .LBB61_254
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bgez a2, .LBB61_254
; CHECK-RV64-NEXT: j .LBB61_768
; CHECK-RV64-NEXT: .LBB61_254: # %else986
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bgez a1, .LBB61_255
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bgez a2, .LBB61_255
; CHECK-RV64-NEXT: j .LBB61_769
; CHECK-RV64-NEXT: .LBB61_255: # %else990
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bgez a1, .LBB61_256
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bgez a2, .LBB61_256
; CHECK-RV64-NEXT: j .LBB61_770
; CHECK-RV64-NEXT: .LBB61_256: # %else994
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bgez a1, .LBB61_257
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bgez a2, .LBB61_257
; CHECK-RV64-NEXT: j .LBB61_771
; CHECK-RV64-NEXT: .LBB61_257: # %else998
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bgez a1, .LBB61_258
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bgez a2, .LBB61_258
; CHECK-RV64-NEXT: j .LBB61_772
; CHECK-RV64-NEXT: .LBB61_258: # %else1002
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bgez a1, .LBB61_259
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bgez a2, .LBB61_259
; CHECK-RV64-NEXT: j .LBB61_773
; CHECK-RV64-NEXT: .LBB61_259: # %else1006
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_261
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_261
; CHECK-RV64-NEXT: .LBB61_260: # %cond.load1009
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 254
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 253
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 253
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_261: # %else1010
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 4
-; CHECK-RV64-NEXT: slli a1, a2, 1
-; CHECK-RV64-NEXT: bgez a1, .LBB61_263
+; CHECK-RV64-NEXT: slli a2, a1, 1
+; CHECK-RV64-NEXT: bgez a2, .LBB61_263
; CHECK-RV64-NEXT: # %bb.262: # %cond.load1013
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: vmv4r.v v20, v8
-; CHECK-RV64-NEXT: vmv.s.x v24, a1
-; CHECK-RV64-NEXT: li a1, 255
+; CHECK-RV64-NEXT: vmv.s.x v24, a2
+; CHECK-RV64-NEXT: li a2, 255
; CHECK-RV64-NEXT: li a3, 254
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v20, v24, a3
; CHECK-RV64-NEXT: vmv4r.v v8, v20
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_263: # %else1014
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_264
+; CHECK-RV64-NEXT: vmv.x.s a2, v16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_264
; CHECK-RV64-NEXT: j .LBB61_774
; CHECK-RV64-NEXT: .LBB61_264: # %else1018
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: beqz a2, .LBB61_265
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: beqz a1, .LBB61_265
; CHECK-RV64-NEXT: j .LBB61_775
; CHECK-RV64-NEXT: .LBB61_265: # %else1022
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: beqz a2, .LBB61_266
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: beqz a1, .LBB61_266
; CHECK-RV64-NEXT: j .LBB61_776
; CHECK-RV64-NEXT: .LBB61_266: # %else1026
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: beqz a2, .LBB61_267
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: beqz a1, .LBB61_267
; CHECK-RV64-NEXT: j .LBB61_777
; CHECK-RV64-NEXT: .LBB61_267: # %else1030
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: beqz a2, .LBB61_268
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: beqz a1, .LBB61_268
; CHECK-RV64-NEXT: j .LBB61_778
; CHECK-RV64-NEXT: .LBB61_268: # %else1034
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: beqz a2, .LBB61_269
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: beqz a1, .LBB61_269
; CHECK-RV64-NEXT: j .LBB61_779
; CHECK-RV64-NEXT: .LBB61_269: # %else1038
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: beqz a2, .LBB61_270
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: beqz a1, .LBB61_270
; CHECK-RV64-NEXT: j .LBB61_780
; CHECK-RV64-NEXT: .LBB61_270: # %else1042
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: beqz a2, .LBB61_271
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: beqz a1, .LBB61_271
; CHECK-RV64-NEXT: j .LBB61_781
; CHECK-RV64-NEXT: .LBB61_271: # %else1046
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: beqz a2, .LBB61_272
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: beqz a1, .LBB61_272
; CHECK-RV64-NEXT: j .LBB61_782
; CHECK-RV64-NEXT: .LBB61_272: # %else1050
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: beqz a2, .LBB61_273
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: beqz a1, .LBB61_273
; CHECK-RV64-NEXT: j .LBB61_783
; CHECK-RV64-NEXT: .LBB61_273: # %else1054
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: beqz a2, .LBB61_274
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: beqz a1, .LBB61_274
; CHECK-RV64-NEXT: j .LBB61_784
; CHECK-RV64-NEXT: .LBB61_274: # %else1058
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: beqz a2, .LBB61_275
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: beqz a1, .LBB61_275
; CHECK-RV64-NEXT: j .LBB61_785
; CHECK-RV64-NEXT: .LBB61_275: # %else1062
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bgez a2, .LBB61_276
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bgez a1, .LBB61_276
; CHECK-RV64-NEXT: j .LBB61_786
; CHECK-RV64-NEXT: .LBB61_276: # %else1066
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bgez a2, .LBB61_277
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bgez a1, .LBB61_277
; CHECK-RV64-NEXT: j .LBB61_787
; CHECK-RV64-NEXT: .LBB61_277: # %else1070
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bgez a2, .LBB61_278
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bgez a1, .LBB61_278
; CHECK-RV64-NEXT: j .LBB61_788
; CHECK-RV64-NEXT: .LBB61_278: # %else1074
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bgez a2, .LBB61_279
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bgez a1, .LBB61_279
; CHECK-RV64-NEXT: j .LBB61_789
; CHECK-RV64-NEXT: .LBB61_279: # %else1078
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bgez a2, .LBB61_280
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bgez a1, .LBB61_280
; CHECK-RV64-NEXT: j .LBB61_790
; CHECK-RV64-NEXT: .LBB61_280: # %else1082
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bgez a2, .LBB61_281
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bgez a1, .LBB61_281
; CHECK-RV64-NEXT: j .LBB61_791
; CHECK-RV64-NEXT: .LBB61_281: # %else1086
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bgez a2, .LBB61_282
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bgez a1, .LBB61_282
; CHECK-RV64-NEXT: j .LBB61_792
; CHECK-RV64-NEXT: .LBB61_282: # %else1090
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bgez a2, .LBB61_283
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bgez a1, .LBB61_283
; CHECK-RV64-NEXT: j .LBB61_793
; CHECK-RV64-NEXT: .LBB61_283: # %else1094
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bgez a2, .LBB61_284
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bgez a1, .LBB61_284
; CHECK-RV64-NEXT: j .LBB61_794
; CHECK-RV64-NEXT: .LBB61_284: # %else1098
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bgez a2, .LBB61_285
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bgez a1, .LBB61_285
; CHECK-RV64-NEXT: j .LBB61_795
; CHECK-RV64-NEXT: .LBB61_285: # %else1102
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bgez a2, .LBB61_286
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bgez a1, .LBB61_286
; CHECK-RV64-NEXT: j .LBB61_796
; CHECK-RV64-NEXT: .LBB61_286: # %else1106
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bgez a2, .LBB61_287
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bgez a1, .LBB61_287
; CHECK-RV64-NEXT: j .LBB61_797
; CHECK-RV64-NEXT: .LBB61_287: # %else1110
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bgez a2, .LBB61_288
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bgez a1, .LBB61_288
; CHECK-RV64-NEXT: j .LBB61_798
; CHECK-RV64-NEXT: .LBB61_288: # %else1114
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bgez a2, .LBB61_289
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bgez a1, .LBB61_289
; CHECK-RV64-NEXT: j .LBB61_799
; CHECK-RV64-NEXT: .LBB61_289: # %else1118
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bgez a2, .LBB61_290
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bgez a1, .LBB61_290
; CHECK-RV64-NEXT: j .LBB61_800
; CHECK-RV64-NEXT: .LBB61_290: # %else1122
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bgez a2, .LBB61_291
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bgez a1, .LBB61_291
; CHECK-RV64-NEXT: j .LBB61_801
; CHECK-RV64-NEXT: .LBB61_291: # %else1126
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bgez a2, .LBB61_292
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bgez a1, .LBB61_292
; CHECK-RV64-NEXT: j .LBB61_802
; CHECK-RV64-NEXT: .LBB61_292: # %else1130
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bgez a2, .LBB61_293
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bgez a1, .LBB61_293
; CHECK-RV64-NEXT: j .LBB61_803
; CHECK-RV64-NEXT: .LBB61_293: # %else1134
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bgez a2, .LBB61_294
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bgez a1, .LBB61_294
; CHECK-RV64-NEXT: j .LBB61_804
; CHECK-RV64-NEXT: .LBB61_294: # %else1138
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bgez a2, .LBB61_295
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bgez a1, .LBB61_295
; CHECK-RV64-NEXT: j .LBB61_805
; CHECK-RV64-NEXT: .LBB61_295: # %else1142
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bgez a2, .LBB61_296
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bgez a1, .LBB61_296
; CHECK-RV64-NEXT: j .LBB61_806
; CHECK-RV64-NEXT: .LBB61_296: # %else1146
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bgez a2, .LBB61_297
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bgez a1, .LBB61_297
; CHECK-RV64-NEXT: j .LBB61_807
; CHECK-RV64-NEXT: .LBB61_297: # %else1150
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bgez a2, .LBB61_298
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bgez a1, .LBB61_298
; CHECK-RV64-NEXT: j .LBB61_808
; CHECK-RV64-NEXT: .LBB61_298: # %else1154
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bgez a2, .LBB61_299
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bgez a1, .LBB61_299
; CHECK-RV64-NEXT: j .LBB61_809
; CHECK-RV64-NEXT: .LBB61_299: # %else1158
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bgez a2, .LBB61_300
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bgez a1, .LBB61_300
; CHECK-RV64-NEXT: j .LBB61_810
; CHECK-RV64-NEXT: .LBB61_300: # %else1162
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bgez a2, .LBB61_301
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bgez a1, .LBB61_301
; CHECK-RV64-NEXT: j .LBB61_811
; CHECK-RV64-NEXT: .LBB61_301: # %else1166
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bgez a2, .LBB61_302
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bgez a1, .LBB61_302
; CHECK-RV64-NEXT: j .LBB61_812
; CHECK-RV64-NEXT: .LBB61_302: # %else1170
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bgez a2, .LBB61_303
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bgez a1, .LBB61_303
; CHECK-RV64-NEXT: j .LBB61_813
; CHECK-RV64-NEXT: .LBB61_303: # %else1174
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bgez a2, .LBB61_304
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bgez a1, .LBB61_304
; CHECK-RV64-NEXT: j .LBB61_814
; CHECK-RV64-NEXT: .LBB61_304: # %else1178
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bgez a2, .LBB61_305
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bgez a1, .LBB61_305
; CHECK-RV64-NEXT: j .LBB61_815
; CHECK-RV64-NEXT: .LBB61_305: # %else1182
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bgez a2, .LBB61_306
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bgez a1, .LBB61_306
; CHECK-RV64-NEXT: j .LBB61_816
; CHECK-RV64-NEXT: .LBB61_306: # %else1186
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bgez a2, .LBB61_307
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bgez a1, .LBB61_307
; CHECK-RV64-NEXT: j .LBB61_817
; CHECK-RV64-NEXT: .LBB61_307: # %else1190
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bgez a2, .LBB61_308
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bgez a1, .LBB61_308
; CHECK-RV64-NEXT: j .LBB61_818
; CHECK-RV64-NEXT: .LBB61_308: # %else1194
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bgez a2, .LBB61_309
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bgez a1, .LBB61_309
; CHECK-RV64-NEXT: j .LBB61_819
; CHECK-RV64-NEXT: .LBB61_309: # %else1198
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bgez a2, .LBB61_310
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bgez a1, .LBB61_310
; CHECK-RV64-NEXT: j .LBB61_820
; CHECK-RV64-NEXT: .LBB61_310: # %else1202
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bgez a2, .LBB61_311
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bgez a1, .LBB61_311
; CHECK-RV64-NEXT: j .LBB61_821
; CHECK-RV64-NEXT: .LBB61_311: # %else1206
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_312
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_312
; CHECK-RV64-NEXT: j .LBB61_822
; CHECK-RV64-NEXT: .LBB61_312: # %else1210
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bgez a2, .LBB61_313
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bgez a1, .LBB61_313
; CHECK-RV64-NEXT: j .LBB61_823
; CHECK-RV64-NEXT: .LBB61_313: # %else1214
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bgez a2, .LBB61_314
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bgez a1, .LBB61_314
; CHECK-RV64-NEXT: j .LBB61_824
; CHECK-RV64-NEXT: .LBB61_314: # %else1218
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bgez a2, .LBB61_315
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bgez a1, .LBB61_315
; CHECK-RV64-NEXT: j .LBB61_825
; CHECK-RV64-NEXT: .LBB61_315: # %else1222
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bgez a2, .LBB61_316
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bgez a1, .LBB61_316
; CHECK-RV64-NEXT: j .LBB61_826
; CHECK-RV64-NEXT: .LBB61_316: # %else1226
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bgez a2, .LBB61_317
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bgez a1, .LBB61_317
; CHECK-RV64-NEXT: j .LBB61_827
; CHECK-RV64-NEXT: .LBB61_317: # %else1230
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bgez a2, .LBB61_318
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bgez a1, .LBB61_318
; CHECK-RV64-NEXT: j .LBB61_828
; CHECK-RV64-NEXT: .LBB61_318: # %else1234
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bgez a2, .LBB61_319
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bgez a1, .LBB61_319
; CHECK-RV64-NEXT: j .LBB61_829
; CHECK-RV64-NEXT: .LBB61_319: # %else1238
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bgez a2, .LBB61_320
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bgez a1, .LBB61_320
; CHECK-RV64-NEXT: j .LBB61_830
; CHECK-RV64-NEXT: .LBB61_320: # %else1242
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bgez a2, .LBB61_321
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bgez a1, .LBB61_321
; CHECK-RV64-NEXT: j .LBB61_831
; CHECK-RV64-NEXT: .LBB61_321: # %else1246
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bgez a2, .LBB61_322
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bgez a1, .LBB61_322
; CHECK-RV64-NEXT: j .LBB61_832
; CHECK-RV64-NEXT: .LBB61_322: # %else1250
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bgez a2, .LBB61_323
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bgez a1, .LBB61_323
; CHECK-RV64-NEXT: j .LBB61_833
; CHECK-RV64-NEXT: .LBB61_323: # %else1254
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bgez a2, .LBB61_324
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bgez a1, .LBB61_324
; CHECK-RV64-NEXT: j .LBB61_834
; CHECK-RV64-NEXT: .LBB61_324: # %else1258
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bgez a2, .LBB61_325
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bgez a1, .LBB61_325
; CHECK-RV64-NEXT: j .LBB61_835
; CHECK-RV64-NEXT: .LBB61_325: # %else1262
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_327
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_327
; CHECK-RV64-NEXT: .LBB61_326: # %cond.load1265
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 318
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 317
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 317
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_327: # %else1266
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 5
-; CHECK-RV64-NEXT: slli a2, a1, 1
-; CHECK-RV64-NEXT: bgez a2, .LBB61_329
+; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 5
+; CHECK-RV64-NEXT: slli a1, a2, 1
+; CHECK-RV64-NEXT: bgez a1, .LBB61_329
; CHECK-RV64-NEXT: # %bb.328: # %cond.load1269
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 319
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v24, a1
+; CHECK-RV64-NEXT: li a1, 319
; CHECK-RV64-NEXT: li a3, 318
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vslideup.vx v8, v24, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_329: # %else1270
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a2, v24
-; CHECK-RV64-NEXT: bgez a1, .LBB61_330
+; CHECK-RV64-NEXT: vmv.x.s a1, v16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_330
; CHECK-RV64-NEXT: j .LBB61_836
; CHECK-RV64-NEXT: .LBB61_330: # %else1274
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: beqz a1, .LBB61_331
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: beqz a2, .LBB61_331
; CHECK-RV64-NEXT: j .LBB61_837
; CHECK-RV64-NEXT: .LBB61_331: # %else1278
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: beqz a1, .LBB61_332
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: beqz a2, .LBB61_332
; CHECK-RV64-NEXT: j .LBB61_838
; CHECK-RV64-NEXT: .LBB61_332: # %else1282
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: beqz a1, .LBB61_333
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: beqz a2, .LBB61_333
; CHECK-RV64-NEXT: j .LBB61_839
; CHECK-RV64-NEXT: .LBB61_333: # %else1286
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: beqz a1, .LBB61_334
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: beqz a2, .LBB61_334
; CHECK-RV64-NEXT: j .LBB61_840
; CHECK-RV64-NEXT: .LBB61_334: # %else1290
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: beqz a1, .LBB61_335
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: beqz a2, .LBB61_335
; CHECK-RV64-NEXT: j .LBB61_841
; CHECK-RV64-NEXT: .LBB61_335: # %else1294
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: beqz a1, .LBB61_336
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: beqz a2, .LBB61_336
; CHECK-RV64-NEXT: j .LBB61_842
; CHECK-RV64-NEXT: .LBB61_336: # %else1298
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: beqz a1, .LBB61_337
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: beqz a2, .LBB61_337
; CHECK-RV64-NEXT: j .LBB61_843
; CHECK-RV64-NEXT: .LBB61_337: # %else1302
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: beqz a1, .LBB61_338
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: beqz a2, .LBB61_338
; CHECK-RV64-NEXT: j .LBB61_844
; CHECK-RV64-NEXT: .LBB61_338: # %else1306
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: beqz a1, .LBB61_339
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: beqz a2, .LBB61_339
; CHECK-RV64-NEXT: j .LBB61_845
; CHECK-RV64-NEXT: .LBB61_339: # %else1310
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: beqz a1, .LBB61_340
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: beqz a2, .LBB61_340
; CHECK-RV64-NEXT: j .LBB61_846
; CHECK-RV64-NEXT: .LBB61_340: # %else1314
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: beqz a1, .LBB61_341
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: beqz a2, .LBB61_341
; CHECK-RV64-NEXT: j .LBB61_847
; CHECK-RV64-NEXT: .LBB61_341: # %else1318
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bgez a1, .LBB61_342
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bgez a2, .LBB61_342
; CHECK-RV64-NEXT: j .LBB61_848
; CHECK-RV64-NEXT: .LBB61_342: # %else1322
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bgez a1, .LBB61_343
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bgez a2, .LBB61_343
; CHECK-RV64-NEXT: j .LBB61_849
; CHECK-RV64-NEXT: .LBB61_343: # %else1326
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bgez a1, .LBB61_344
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bgez a2, .LBB61_344
; CHECK-RV64-NEXT: j .LBB61_850
; CHECK-RV64-NEXT: .LBB61_344: # %else1330
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bgez a1, .LBB61_345
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bgez a2, .LBB61_345
; CHECK-RV64-NEXT: j .LBB61_851
; CHECK-RV64-NEXT: .LBB61_345: # %else1334
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bgez a1, .LBB61_346
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bgez a2, .LBB61_346
; CHECK-RV64-NEXT: j .LBB61_852
; CHECK-RV64-NEXT: .LBB61_346: # %else1338
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bgez a1, .LBB61_347
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bgez a2, .LBB61_347
; CHECK-RV64-NEXT: j .LBB61_853
; CHECK-RV64-NEXT: .LBB61_347: # %else1342
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bgez a1, .LBB61_348
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bgez a2, .LBB61_348
; CHECK-RV64-NEXT: j .LBB61_854
; CHECK-RV64-NEXT: .LBB61_348: # %else1346
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bgez a1, .LBB61_349
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bgez a2, .LBB61_349
; CHECK-RV64-NEXT: j .LBB61_855
; CHECK-RV64-NEXT: .LBB61_349: # %else1350
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bgez a1, .LBB61_350
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bgez a2, .LBB61_350
; CHECK-RV64-NEXT: j .LBB61_856
; CHECK-RV64-NEXT: .LBB61_350: # %else1354
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bgez a1, .LBB61_351
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bgez a2, .LBB61_351
; CHECK-RV64-NEXT: j .LBB61_857
; CHECK-RV64-NEXT: .LBB61_351: # %else1358
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bgez a1, .LBB61_352
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bgez a2, .LBB61_352
; CHECK-RV64-NEXT: j .LBB61_858
; CHECK-RV64-NEXT: .LBB61_352: # %else1362
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bgez a1, .LBB61_353
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bgez a2, .LBB61_353
; CHECK-RV64-NEXT: j .LBB61_859
; CHECK-RV64-NEXT: .LBB61_353: # %else1366
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bgez a1, .LBB61_354
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bgez a2, .LBB61_354
; CHECK-RV64-NEXT: j .LBB61_860
; CHECK-RV64-NEXT: .LBB61_354: # %else1370
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bgez a1, .LBB61_355
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bgez a2, .LBB61_355
; CHECK-RV64-NEXT: j .LBB61_861
; CHECK-RV64-NEXT: .LBB61_355: # %else1374
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bgez a1, .LBB61_356
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bgez a2, .LBB61_356
; CHECK-RV64-NEXT: j .LBB61_862
; CHECK-RV64-NEXT: .LBB61_356: # %else1378
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bgez a1, .LBB61_357
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bgez a2, .LBB61_357
; CHECK-RV64-NEXT: j .LBB61_863
; CHECK-RV64-NEXT: .LBB61_357: # %else1382
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bgez a1, .LBB61_358
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bgez a2, .LBB61_358
; CHECK-RV64-NEXT: j .LBB61_864
; CHECK-RV64-NEXT: .LBB61_358: # %else1386
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bgez a1, .LBB61_359
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bgez a2, .LBB61_359
; CHECK-RV64-NEXT: j .LBB61_865
; CHECK-RV64-NEXT: .LBB61_359: # %else1390
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bgez a1, .LBB61_360
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bgez a2, .LBB61_360
; CHECK-RV64-NEXT: j .LBB61_866
; CHECK-RV64-NEXT: .LBB61_360: # %else1394
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bgez a1, .LBB61_361
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bgez a2, .LBB61_361
; CHECK-RV64-NEXT: j .LBB61_867
; CHECK-RV64-NEXT: .LBB61_361: # %else1398
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bgez a1, .LBB61_362
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bgez a2, .LBB61_362
; CHECK-RV64-NEXT: j .LBB61_868
; CHECK-RV64-NEXT: .LBB61_362: # %else1402
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bgez a1, .LBB61_363
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bgez a2, .LBB61_363
; CHECK-RV64-NEXT: j .LBB61_869
; CHECK-RV64-NEXT: .LBB61_363: # %else1406
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bgez a1, .LBB61_364
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bgez a2, .LBB61_364
; CHECK-RV64-NEXT: j .LBB61_870
; CHECK-RV64-NEXT: .LBB61_364: # %else1410
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bgez a1, .LBB61_365
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bgez a2, .LBB61_365
; CHECK-RV64-NEXT: j .LBB61_871
; CHECK-RV64-NEXT: .LBB61_365: # %else1414
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bgez a1, .LBB61_366
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bgez a2, .LBB61_366
; CHECK-RV64-NEXT: j .LBB61_872
; CHECK-RV64-NEXT: .LBB61_366: # %else1418
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bgez a1, .LBB61_367
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bgez a2, .LBB61_367
; CHECK-RV64-NEXT: j .LBB61_873
; CHECK-RV64-NEXT: .LBB61_367: # %else1422
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bgez a1, .LBB61_368
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bgez a2, .LBB61_368
; CHECK-RV64-NEXT: j .LBB61_874
; CHECK-RV64-NEXT: .LBB61_368: # %else1426
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bgez a1, .LBB61_369
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bgez a2, .LBB61_369
; CHECK-RV64-NEXT: j .LBB61_875
; CHECK-RV64-NEXT: .LBB61_369: # %else1430
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bgez a1, .LBB61_370
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bgez a2, .LBB61_370
; CHECK-RV64-NEXT: j .LBB61_876
; CHECK-RV64-NEXT: .LBB61_370: # %else1434
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bgez a1, .LBB61_371
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bgez a2, .LBB61_371
; CHECK-RV64-NEXT: j .LBB61_877
; CHECK-RV64-NEXT: .LBB61_371: # %else1438
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bgez a1, .LBB61_372
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bgez a2, .LBB61_372
; CHECK-RV64-NEXT: j .LBB61_878
; CHECK-RV64-NEXT: .LBB61_372: # %else1442
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bgez a1, .LBB61_373
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bgez a2, .LBB61_373
; CHECK-RV64-NEXT: j .LBB61_879
; CHECK-RV64-NEXT: .LBB61_373: # %else1446
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bgez a1, .LBB61_374
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bgez a2, .LBB61_374
; CHECK-RV64-NEXT: j .LBB61_880
; CHECK-RV64-NEXT: .LBB61_374: # %else1450
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bgez a1, .LBB61_375
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bgez a2, .LBB61_375
; CHECK-RV64-NEXT: j .LBB61_881
; CHECK-RV64-NEXT: .LBB61_375: # %else1454
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bgez a1, .LBB61_376
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bgez a2, .LBB61_376
; CHECK-RV64-NEXT: j .LBB61_882
; CHECK-RV64-NEXT: .LBB61_376: # %else1458
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bgez a1, .LBB61_377
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bgez a2, .LBB61_377
; CHECK-RV64-NEXT: j .LBB61_883
; CHECK-RV64-NEXT: .LBB61_377: # %else1462
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_378
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_378
; CHECK-RV64-NEXT: j .LBB61_884
; CHECK-RV64-NEXT: .LBB61_378: # %else1466
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bgez a1, .LBB61_379
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bgez a2, .LBB61_379
; CHECK-RV64-NEXT: j .LBB61_885
; CHECK-RV64-NEXT: .LBB61_379: # %else1470
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bgez a1, .LBB61_380
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bgez a2, .LBB61_380
; CHECK-RV64-NEXT: j .LBB61_886
; CHECK-RV64-NEXT: .LBB61_380: # %else1474
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bgez a1, .LBB61_381
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bgez a2, .LBB61_381
; CHECK-RV64-NEXT: j .LBB61_887
; CHECK-RV64-NEXT: .LBB61_381: # %else1478
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bgez a1, .LBB61_382
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bgez a2, .LBB61_382
; CHECK-RV64-NEXT: j .LBB61_888
; CHECK-RV64-NEXT: .LBB61_382: # %else1482
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bgez a1, .LBB61_383
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bgez a2, .LBB61_383
; CHECK-RV64-NEXT: j .LBB61_889
; CHECK-RV64-NEXT: .LBB61_383: # %else1486
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bgez a1, .LBB61_384
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bgez a2, .LBB61_384
; CHECK-RV64-NEXT: j .LBB61_890
; CHECK-RV64-NEXT: .LBB61_384: # %else1490
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bgez a1, .LBB61_385
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bgez a2, .LBB61_385
; CHECK-RV64-NEXT: j .LBB61_891
; CHECK-RV64-NEXT: .LBB61_385: # %else1494
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bgez a1, .LBB61_386
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bgez a2, .LBB61_386
; CHECK-RV64-NEXT: j .LBB61_892
; CHECK-RV64-NEXT: .LBB61_386: # %else1498
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bgez a1, .LBB61_387
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bgez a2, .LBB61_387
; CHECK-RV64-NEXT: j .LBB61_893
; CHECK-RV64-NEXT: .LBB61_387: # %else1502
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bgez a1, .LBB61_388
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bgez a2, .LBB61_388
; CHECK-RV64-NEXT: j .LBB61_894
; CHECK-RV64-NEXT: .LBB61_388: # %else1506
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bgez a1, .LBB61_389
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bgez a2, .LBB61_389
; CHECK-RV64-NEXT: j .LBB61_895
; CHECK-RV64-NEXT: .LBB61_389: # %else1510
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bgez a1, .LBB61_390
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bgez a2, .LBB61_390
; CHECK-RV64-NEXT: j .LBB61_896
; CHECK-RV64-NEXT: .LBB61_390: # %else1514
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bgez a1, .LBB61_391
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bgez a2, .LBB61_391
; CHECK-RV64-NEXT: j .LBB61_897
; CHECK-RV64-NEXT: .LBB61_391: # %else1518
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_393
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_393
; CHECK-RV64-NEXT: .LBB61_392: # %cond.load1521
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 382
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 381
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 381
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_393: # %else1522
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 6
-; CHECK-RV64-NEXT: slli a1, a2, 1
-; CHECK-RV64-NEXT: bgez a1, .LBB61_395
+; CHECK-RV64-NEXT: slli a2, a1, 1
+; CHECK-RV64-NEXT: bgez a2, .LBB61_395
; CHECK-RV64-NEXT: # %bb.394: # %cond.load1525
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v24, a1
-; CHECK-RV64-NEXT: li a1, 383
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v24, a2
+; CHECK-RV64-NEXT: li a2, 383
; CHECK-RV64-NEXT: li a3, 382
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v24, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_395: # %else1526
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_396
+; CHECK-RV64-NEXT: vmv.x.s a2, v16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_396
; CHECK-RV64-NEXT: j .LBB61_898
; CHECK-RV64-NEXT: .LBB61_396: # %else1530
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: beqz a2, .LBB61_397
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: beqz a1, .LBB61_397
; CHECK-RV64-NEXT: j .LBB61_899
; CHECK-RV64-NEXT: .LBB61_397: # %else1534
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: beqz a2, .LBB61_398
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: beqz a1, .LBB61_398
; CHECK-RV64-NEXT: j .LBB61_900
; CHECK-RV64-NEXT: .LBB61_398: # %else1538
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: beqz a2, .LBB61_399
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: beqz a1, .LBB61_399
; CHECK-RV64-NEXT: j .LBB61_901
; CHECK-RV64-NEXT: .LBB61_399: # %else1542
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: beqz a2, .LBB61_400
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: beqz a1, .LBB61_400
; CHECK-RV64-NEXT: j .LBB61_902
; CHECK-RV64-NEXT: .LBB61_400: # %else1546
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: beqz a2, .LBB61_401
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: beqz a1, .LBB61_401
; CHECK-RV64-NEXT: j .LBB61_903
; CHECK-RV64-NEXT: .LBB61_401: # %else1550
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: beqz a2, .LBB61_402
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: beqz a1, .LBB61_402
; CHECK-RV64-NEXT: j .LBB61_904
; CHECK-RV64-NEXT: .LBB61_402: # %else1554
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: beqz a2, .LBB61_403
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: beqz a1, .LBB61_403
; CHECK-RV64-NEXT: j .LBB61_905
; CHECK-RV64-NEXT: .LBB61_403: # %else1558
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: beqz a2, .LBB61_404
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: beqz a1, .LBB61_404
; CHECK-RV64-NEXT: j .LBB61_906
; CHECK-RV64-NEXT: .LBB61_404: # %else1562
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: beqz a2, .LBB61_405
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: beqz a1, .LBB61_405
; CHECK-RV64-NEXT: j .LBB61_907
; CHECK-RV64-NEXT: .LBB61_405: # %else1566
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: beqz a2, .LBB61_406
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: beqz a1, .LBB61_406
; CHECK-RV64-NEXT: j .LBB61_908
; CHECK-RV64-NEXT: .LBB61_406: # %else1570
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: beqz a2, .LBB61_407
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: beqz a1, .LBB61_407
; CHECK-RV64-NEXT: j .LBB61_909
; CHECK-RV64-NEXT: .LBB61_407: # %else1574
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bgez a2, .LBB61_408
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bgez a1, .LBB61_408
; CHECK-RV64-NEXT: j .LBB61_910
; CHECK-RV64-NEXT: .LBB61_408: # %else1578
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bgez a2, .LBB61_409
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bgez a1, .LBB61_409
; CHECK-RV64-NEXT: j .LBB61_911
; CHECK-RV64-NEXT: .LBB61_409: # %else1582
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bgez a2, .LBB61_410
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bgez a1, .LBB61_410
; CHECK-RV64-NEXT: j .LBB61_912
; CHECK-RV64-NEXT: .LBB61_410: # %else1586
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bgez a2, .LBB61_411
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bgez a1, .LBB61_411
; CHECK-RV64-NEXT: j .LBB61_913
; CHECK-RV64-NEXT: .LBB61_411: # %else1590
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bgez a2, .LBB61_412
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bgez a1, .LBB61_412
; CHECK-RV64-NEXT: j .LBB61_914
; CHECK-RV64-NEXT: .LBB61_412: # %else1594
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bgez a2, .LBB61_413
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bgez a1, .LBB61_413
; CHECK-RV64-NEXT: j .LBB61_915
; CHECK-RV64-NEXT: .LBB61_413: # %else1598
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bgez a2, .LBB61_414
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bgez a1, .LBB61_414
; CHECK-RV64-NEXT: j .LBB61_916
; CHECK-RV64-NEXT: .LBB61_414: # %else1602
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bgez a2, .LBB61_415
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bgez a1, .LBB61_415
; CHECK-RV64-NEXT: j .LBB61_917
; CHECK-RV64-NEXT: .LBB61_415: # %else1606
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bgez a2, .LBB61_416
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bgez a1, .LBB61_416
; CHECK-RV64-NEXT: j .LBB61_918
; CHECK-RV64-NEXT: .LBB61_416: # %else1610
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bgez a2, .LBB61_417
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bgez a1, .LBB61_417
; CHECK-RV64-NEXT: j .LBB61_919
; CHECK-RV64-NEXT: .LBB61_417: # %else1614
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bgez a2, .LBB61_418
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bgez a1, .LBB61_418
; CHECK-RV64-NEXT: j .LBB61_920
; CHECK-RV64-NEXT: .LBB61_418: # %else1618
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bgez a2, .LBB61_419
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bgez a1, .LBB61_419
; CHECK-RV64-NEXT: j .LBB61_921
; CHECK-RV64-NEXT: .LBB61_419: # %else1622
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bgez a2, .LBB61_420
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bgez a1, .LBB61_420
; CHECK-RV64-NEXT: j .LBB61_922
; CHECK-RV64-NEXT: .LBB61_420: # %else1626
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bgez a2, .LBB61_421
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bgez a1, .LBB61_421
; CHECK-RV64-NEXT: j .LBB61_923
; CHECK-RV64-NEXT: .LBB61_421: # %else1630
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bgez a2, .LBB61_422
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bgez a1, .LBB61_422
; CHECK-RV64-NEXT: j .LBB61_924
; CHECK-RV64-NEXT: .LBB61_422: # %else1634
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bgez a2, .LBB61_423
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bgez a1, .LBB61_423
; CHECK-RV64-NEXT: j .LBB61_925
; CHECK-RV64-NEXT: .LBB61_423: # %else1638
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bgez a2, .LBB61_424
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bgez a1, .LBB61_424
; CHECK-RV64-NEXT: j .LBB61_926
; CHECK-RV64-NEXT: .LBB61_424: # %else1642
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bgez a2, .LBB61_425
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bgez a1, .LBB61_425
; CHECK-RV64-NEXT: j .LBB61_927
; CHECK-RV64-NEXT: .LBB61_425: # %else1646
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bgez a2, .LBB61_426
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bgez a1, .LBB61_426
; CHECK-RV64-NEXT: j .LBB61_928
; CHECK-RV64-NEXT: .LBB61_426: # %else1650
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bgez a2, .LBB61_427
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bgez a1, .LBB61_427
; CHECK-RV64-NEXT: j .LBB61_929
; CHECK-RV64-NEXT: .LBB61_427: # %else1654
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bgez a2, .LBB61_428
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bgez a1, .LBB61_428
; CHECK-RV64-NEXT: j .LBB61_930
; CHECK-RV64-NEXT: .LBB61_428: # %else1658
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bgez a2, .LBB61_429
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bgez a1, .LBB61_429
; CHECK-RV64-NEXT: j .LBB61_931
; CHECK-RV64-NEXT: .LBB61_429: # %else1662
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bgez a2, .LBB61_430
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bgez a1, .LBB61_430
; CHECK-RV64-NEXT: j .LBB61_932
; CHECK-RV64-NEXT: .LBB61_430: # %else1666
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bgez a2, .LBB61_431
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bgez a1, .LBB61_431
; CHECK-RV64-NEXT: j .LBB61_933
; CHECK-RV64-NEXT: .LBB61_431: # %else1670
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bgez a2, .LBB61_432
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bgez a1, .LBB61_432
; CHECK-RV64-NEXT: j .LBB61_934
; CHECK-RV64-NEXT: .LBB61_432: # %else1674
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bgez a2, .LBB61_433
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bgez a1, .LBB61_433
; CHECK-RV64-NEXT: j .LBB61_935
; CHECK-RV64-NEXT: .LBB61_433: # %else1678
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bgez a2, .LBB61_434
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bgez a1, .LBB61_434
; CHECK-RV64-NEXT: j .LBB61_936
; CHECK-RV64-NEXT: .LBB61_434: # %else1682
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bgez a2, .LBB61_435
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bgez a1, .LBB61_435
; CHECK-RV64-NEXT: j .LBB61_937
; CHECK-RV64-NEXT: .LBB61_435: # %else1686
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bgez a2, .LBB61_436
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bgez a1, .LBB61_436
; CHECK-RV64-NEXT: j .LBB61_938
; CHECK-RV64-NEXT: .LBB61_436: # %else1690
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bgez a2, .LBB61_437
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bgez a1, .LBB61_437
; CHECK-RV64-NEXT: j .LBB61_939
; CHECK-RV64-NEXT: .LBB61_437: # %else1694
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bgez a2, .LBB61_438
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bgez a1, .LBB61_438
; CHECK-RV64-NEXT: j .LBB61_940
; CHECK-RV64-NEXT: .LBB61_438: # %else1698
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bgez a2, .LBB61_439
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bgez a1, .LBB61_439
; CHECK-RV64-NEXT: j .LBB61_941
; CHECK-RV64-NEXT: .LBB61_439: # %else1702
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bgez a2, .LBB61_440
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bgez a1, .LBB61_440
; CHECK-RV64-NEXT: j .LBB61_942
; CHECK-RV64-NEXT: .LBB61_440: # %else1706
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bgez a2, .LBB61_441
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bgez a1, .LBB61_441
; CHECK-RV64-NEXT: j .LBB61_943
; CHECK-RV64-NEXT: .LBB61_441: # %else1710
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bgez a2, .LBB61_442
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bgez a1, .LBB61_442
; CHECK-RV64-NEXT: j .LBB61_944
; CHECK-RV64-NEXT: .LBB61_442: # %else1714
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bgez a2, .LBB61_443
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bgez a1, .LBB61_443
; CHECK-RV64-NEXT: j .LBB61_945
; CHECK-RV64-NEXT: .LBB61_443: # %else1718
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bgez a2, .LBB61_444
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bgez a1, .LBB61_444
; CHECK-RV64-NEXT: j .LBB61_946
; CHECK-RV64-NEXT: .LBB61_444: # %else1722
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bgez a2, .LBB61_445
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bgez a1, .LBB61_445
; CHECK-RV64-NEXT: j .LBB61_947
; CHECK-RV64-NEXT: .LBB61_445: # %else1726
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bgez a2, .LBB61_446
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bgez a1, .LBB61_446
; CHECK-RV64-NEXT: j .LBB61_948
; CHECK-RV64-NEXT: .LBB61_446: # %else1730
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bgez a2, .LBB61_447
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bgez a1, .LBB61_447
; CHECK-RV64-NEXT: j .LBB61_949
; CHECK-RV64-NEXT: .LBB61_447: # %else1734
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bgez a2, .LBB61_448
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bgez a1, .LBB61_448
; CHECK-RV64-NEXT: j .LBB61_950
; CHECK-RV64-NEXT: .LBB61_448: # %else1738
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bgez a2, .LBB61_449
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bgez a1, .LBB61_449
; CHECK-RV64-NEXT: j .LBB61_951
; CHECK-RV64-NEXT: .LBB61_449: # %else1742
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bgez a2, .LBB61_450
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bgez a1, .LBB61_450
; CHECK-RV64-NEXT: j .LBB61_952
; CHECK-RV64-NEXT: .LBB61_450: # %else1746
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bgez a2, .LBB61_451
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bgez a1, .LBB61_451
; CHECK-RV64-NEXT: j .LBB61_953
; CHECK-RV64-NEXT: .LBB61_451: # %else1750
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bgez a2, .LBB61_452
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bgez a1, .LBB61_452
; CHECK-RV64-NEXT: j .LBB61_954
; CHECK-RV64-NEXT: .LBB61_452: # %else1754
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bgez a2, .LBB61_453
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bgez a1, .LBB61_453
; CHECK-RV64-NEXT: j .LBB61_955
; CHECK-RV64-NEXT: .LBB61_453: # %else1758
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bgez a2, .LBB61_454
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bgez a1, .LBB61_454
; CHECK-RV64-NEXT: j .LBB61_956
; CHECK-RV64-NEXT: .LBB61_454: # %else1762
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bgez a2, .LBB61_455
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bgez a1, .LBB61_455
; CHECK-RV64-NEXT: j .LBB61_957
; CHECK-RV64-NEXT: .LBB61_455: # %else1766
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bgez a2, .LBB61_456
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bgez a1, .LBB61_456
; CHECK-RV64-NEXT: j .LBB61_958
; CHECK-RV64-NEXT: .LBB61_456: # %else1770
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bgez a2, .LBB61_457
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bgez a1, .LBB61_457
; CHECK-RV64-NEXT: j .LBB61_959
; CHECK-RV64-NEXT: .LBB61_457: # %else1774
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_459
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_459
; CHECK-RV64-NEXT: .LBB61_458: # %cond.load1777
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 446
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 445
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 445
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_459: # %else1778
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v16, v0, 7
-; CHECK-RV64-NEXT: slli a2, a1, 1
-; CHECK-RV64-NEXT: bgez a2, .LBB61_461
+; CHECK-RV64-NEXT: slli a1, a2, 1
+; CHECK-RV64-NEXT: bgez a1, .LBB61_461
; CHECK-RV64-NEXT: # %bb.460: # %cond.load1781
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v24, a2
-; CHECK-RV64-NEXT: li a2, 447
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v24, a1
+; CHECK-RV64-NEXT: li a1, 447
; CHECK-RV64-NEXT: li a3, 446
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v24, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_461: # %else1782
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a2, v16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_462
+; CHECK-RV64-NEXT: vmv.x.s a1, v16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_462
; CHECK-RV64-NEXT: j .LBB61_960
; CHECK-RV64-NEXT: .LBB61_462: # %else1786
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: beqz a1, .LBB61_463
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: beqz a2, .LBB61_463
; CHECK-RV64-NEXT: j .LBB61_961
; CHECK-RV64-NEXT: .LBB61_463: # %else1790
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: beqz a1, .LBB61_464
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: beqz a2, .LBB61_464
; CHECK-RV64-NEXT: j .LBB61_962
; CHECK-RV64-NEXT: .LBB61_464: # %else1794
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: beqz a1, .LBB61_465
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: beqz a2, .LBB61_465
; CHECK-RV64-NEXT: j .LBB61_963
; CHECK-RV64-NEXT: .LBB61_465: # %else1798
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: beqz a1, .LBB61_466
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: beqz a2, .LBB61_466
; CHECK-RV64-NEXT: j .LBB61_964
; CHECK-RV64-NEXT: .LBB61_466: # %else1802
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: beqz a1, .LBB61_467
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: beqz a2, .LBB61_467
; CHECK-RV64-NEXT: j .LBB61_965
; CHECK-RV64-NEXT: .LBB61_467: # %else1806
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: beqz a1, .LBB61_468
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: beqz a2, .LBB61_468
; CHECK-RV64-NEXT: j .LBB61_966
; CHECK-RV64-NEXT: .LBB61_468: # %else1810
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: beqz a1, .LBB61_469
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: beqz a2, .LBB61_469
; CHECK-RV64-NEXT: j .LBB61_967
; CHECK-RV64-NEXT: .LBB61_469: # %else1814
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: beqz a1, .LBB61_470
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: beqz a2, .LBB61_470
; CHECK-RV64-NEXT: j .LBB61_968
; CHECK-RV64-NEXT: .LBB61_470: # %else1818
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: beqz a1, .LBB61_471
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: beqz a2, .LBB61_471
; CHECK-RV64-NEXT: j .LBB61_969
; CHECK-RV64-NEXT: .LBB61_471: # %else1822
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: beqz a1, .LBB61_472
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: beqz a2, .LBB61_472
; CHECK-RV64-NEXT: j .LBB61_970
; CHECK-RV64-NEXT: .LBB61_472: # %else1826
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: beqz a1, .LBB61_473
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: beqz a2, .LBB61_473
; CHECK-RV64-NEXT: j .LBB61_971
; CHECK-RV64-NEXT: .LBB61_473: # %else1830
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bgez a1, .LBB61_474
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bgez a2, .LBB61_474
; CHECK-RV64-NEXT: j .LBB61_972
; CHECK-RV64-NEXT: .LBB61_474: # %else1834
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bgez a1, .LBB61_475
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bgez a2, .LBB61_475
; CHECK-RV64-NEXT: j .LBB61_973
; CHECK-RV64-NEXT: .LBB61_475: # %else1838
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bgez a1, .LBB61_476
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bgez a2, .LBB61_476
; CHECK-RV64-NEXT: j .LBB61_974
; CHECK-RV64-NEXT: .LBB61_476: # %else1842
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bgez a1, .LBB61_477
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bgez a2, .LBB61_477
; CHECK-RV64-NEXT: j .LBB61_975
; CHECK-RV64-NEXT: .LBB61_477: # %else1846
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bgez a1, .LBB61_478
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bgez a2, .LBB61_478
; CHECK-RV64-NEXT: j .LBB61_976
; CHECK-RV64-NEXT: .LBB61_478: # %else1850
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bgez a1, .LBB61_479
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bgez a2, .LBB61_479
; CHECK-RV64-NEXT: j .LBB61_977
; CHECK-RV64-NEXT: .LBB61_479: # %else1854
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bgez a1, .LBB61_480
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bgez a2, .LBB61_480
; CHECK-RV64-NEXT: j .LBB61_978
; CHECK-RV64-NEXT: .LBB61_480: # %else1858
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bgez a1, .LBB61_481
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bgez a2, .LBB61_481
; CHECK-RV64-NEXT: j .LBB61_979
; CHECK-RV64-NEXT: .LBB61_481: # %else1862
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bgez a1, .LBB61_482
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bgez a2, .LBB61_482
; CHECK-RV64-NEXT: j .LBB61_980
; CHECK-RV64-NEXT: .LBB61_482: # %else1866
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bgez a1, .LBB61_483
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bgez a2, .LBB61_483
; CHECK-RV64-NEXT: j .LBB61_981
; CHECK-RV64-NEXT: .LBB61_483: # %else1870
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bgez a1, .LBB61_484
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bgez a2, .LBB61_484
; CHECK-RV64-NEXT: j .LBB61_982
; CHECK-RV64-NEXT: .LBB61_484: # %else1874
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bgez a1, .LBB61_485
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bgez a2, .LBB61_485
; CHECK-RV64-NEXT: j .LBB61_983
; CHECK-RV64-NEXT: .LBB61_485: # %else1878
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bgez a1, .LBB61_486
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bgez a2, .LBB61_486
; CHECK-RV64-NEXT: j .LBB61_984
; CHECK-RV64-NEXT: .LBB61_486: # %else1882
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bgez a1, .LBB61_487
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bgez a2, .LBB61_487
; CHECK-RV64-NEXT: j .LBB61_985
; CHECK-RV64-NEXT: .LBB61_487: # %else1886
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bgez a1, .LBB61_488
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bgez a2, .LBB61_488
; CHECK-RV64-NEXT: j .LBB61_986
; CHECK-RV64-NEXT: .LBB61_488: # %else1890
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bgez a1, .LBB61_489
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bgez a2, .LBB61_489
; CHECK-RV64-NEXT: j .LBB61_987
; CHECK-RV64-NEXT: .LBB61_489: # %else1894
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bgez a1, .LBB61_490
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bgez a2, .LBB61_490
; CHECK-RV64-NEXT: j .LBB61_988
; CHECK-RV64-NEXT: .LBB61_490: # %else1898
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bgez a1, .LBB61_491
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bgez a2, .LBB61_491
; CHECK-RV64-NEXT: j .LBB61_989
; CHECK-RV64-NEXT: .LBB61_491: # %else1902
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bgez a1, .LBB61_492
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bgez a2, .LBB61_492
; CHECK-RV64-NEXT: j .LBB61_990
; CHECK-RV64-NEXT: .LBB61_492: # %else1906
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bgez a1, .LBB61_493
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bgez a2, .LBB61_493
; CHECK-RV64-NEXT: j .LBB61_991
; CHECK-RV64-NEXT: .LBB61_493: # %else1910
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bgez a1, .LBB61_494
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bgez a2, .LBB61_494
; CHECK-RV64-NEXT: j .LBB61_992
; CHECK-RV64-NEXT: .LBB61_494: # %else1914
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bgez a1, .LBB61_495
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bgez a2, .LBB61_495
; CHECK-RV64-NEXT: j .LBB61_993
; CHECK-RV64-NEXT: .LBB61_495: # %else1918
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bgez a1, .LBB61_496
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bgez a2, .LBB61_496
; CHECK-RV64-NEXT: j .LBB61_994
; CHECK-RV64-NEXT: .LBB61_496: # %else1922
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bgez a1, .LBB61_497
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bgez a2, .LBB61_497
; CHECK-RV64-NEXT: j .LBB61_995
; CHECK-RV64-NEXT: .LBB61_497: # %else1926
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bgez a1, .LBB61_498
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bgez a2, .LBB61_498
; CHECK-RV64-NEXT: j .LBB61_996
; CHECK-RV64-NEXT: .LBB61_498: # %else1930
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bgez a1, .LBB61_499
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bgez a2, .LBB61_499
; CHECK-RV64-NEXT: j .LBB61_997
; CHECK-RV64-NEXT: .LBB61_499: # %else1934
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bgez a1, .LBB61_500
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bgez a2, .LBB61_500
; CHECK-RV64-NEXT: j .LBB61_998
; CHECK-RV64-NEXT: .LBB61_500: # %else1938
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bgez a1, .LBB61_501
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bgez a2, .LBB61_501
; CHECK-RV64-NEXT: j .LBB61_999
; CHECK-RV64-NEXT: .LBB61_501: # %else1942
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bgez a1, .LBB61_502
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bgez a2, .LBB61_502
; CHECK-RV64-NEXT: j .LBB61_1000
; CHECK-RV64-NEXT: .LBB61_502: # %else1946
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bgez a1, .LBB61_503
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bgez a2, .LBB61_503
; CHECK-RV64-NEXT: j .LBB61_1001
; CHECK-RV64-NEXT: .LBB61_503: # %else1950
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bgez a1, .LBB61_504
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bgez a2, .LBB61_504
; CHECK-RV64-NEXT: j .LBB61_1002
; CHECK-RV64-NEXT: .LBB61_504: # %else1954
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bgez a1, .LBB61_505
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bgez a2, .LBB61_505
; CHECK-RV64-NEXT: j .LBB61_1003
; CHECK-RV64-NEXT: .LBB61_505: # %else1958
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bgez a1, .LBB61_506
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bgez a2, .LBB61_506
; CHECK-RV64-NEXT: j .LBB61_1004
; CHECK-RV64-NEXT: .LBB61_506: # %else1962
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bgez a1, .LBB61_507
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bgez a2, .LBB61_507
; CHECK-RV64-NEXT: j .LBB61_1005
; CHECK-RV64-NEXT: .LBB61_507: # %else1966
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bgez a1, .LBB61_508
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bgez a2, .LBB61_508
; CHECK-RV64-NEXT: j .LBB61_1006
; CHECK-RV64-NEXT: .LBB61_508: # %else1970
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bgez a1, .LBB61_509
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bgez a2, .LBB61_509
; CHECK-RV64-NEXT: j .LBB61_1007
; CHECK-RV64-NEXT: .LBB61_509: # %else1974
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bgez a1, .LBB61_510
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bgez a2, .LBB61_510
; CHECK-RV64-NEXT: j .LBB61_1008
; CHECK-RV64-NEXT: .LBB61_510: # %else1978
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bgez a1, .LBB61_511
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bgez a2, .LBB61_511
; CHECK-RV64-NEXT: j .LBB61_1009
; CHECK-RV64-NEXT: .LBB61_511: # %else1982
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bgez a1, .LBB61_512
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bgez a2, .LBB61_512
; CHECK-RV64-NEXT: j .LBB61_1010
; CHECK-RV64-NEXT: .LBB61_512: # %else1986
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bgez a1, .LBB61_513
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bgez a2, .LBB61_513
; CHECK-RV64-NEXT: j .LBB61_1011
; CHECK-RV64-NEXT: .LBB61_513: # %else1990
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bgez a1, .LBB61_514
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bgez a2, .LBB61_514
; CHECK-RV64-NEXT: j .LBB61_1012
; CHECK-RV64-NEXT: .LBB61_514: # %else1994
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bgez a1, .LBB61_515
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bgez a2, .LBB61_515
; CHECK-RV64-NEXT: j .LBB61_1013
; CHECK-RV64-NEXT: .LBB61_515: # %else1998
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bgez a1, .LBB61_516
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bgez a2, .LBB61_516
; CHECK-RV64-NEXT: j .LBB61_1014
; CHECK-RV64-NEXT: .LBB61_516: # %else2002
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bgez a1, .LBB61_517
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bgez a2, .LBB61_517
; CHECK-RV64-NEXT: j .LBB61_1015
; CHECK-RV64-NEXT: .LBB61_517: # %else2006
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bgez a1, .LBB61_518
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bgez a2, .LBB61_518
; CHECK-RV64-NEXT: j .LBB61_1016
; CHECK-RV64-NEXT: .LBB61_518: # %else2010
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bgez a1, .LBB61_519
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bgez a2, .LBB61_519
; CHECK-RV64-NEXT: j .LBB61_1017
; CHECK-RV64-NEXT: .LBB61_519: # %else2014
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bgez a1, .LBB61_520
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bgez a2, .LBB61_520
; CHECK-RV64-NEXT: j .LBB61_1018
; CHECK-RV64-NEXT: .LBB61_520: # %else2018
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bgez a1, .LBB61_521
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bgez a2, .LBB61_521
; CHECK-RV64-NEXT: j .LBB61_1019
; CHECK-RV64-NEXT: .LBB61_521: # %else2022
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bgez a1, .LBB61_522
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bgez a2, .LBB61_522
; CHECK-RV64-NEXT: j .LBB61_1020
; CHECK-RV64-NEXT: .LBB61_522: # %else2026
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bgez a1, .LBB61_523
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bgez a2, .LBB61_523
; CHECK-RV64-NEXT: j .LBB61_1021
; CHECK-RV64-NEXT: .LBB61_523: # %else2030
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_524
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_524
; CHECK-RV64-NEXT: j .LBB61_1022
; CHECK-RV64-NEXT: .LBB61_524: # %else2034
-; CHECK-RV64-NEXT: slli a1, a2, 1
-; CHECK-RV64-NEXT: bgez a1, .LBB61_525
+; CHECK-RV64-NEXT: slli a2, a1, 1
+; CHECK-RV64-NEXT: bgez a2, .LBB61_525
; CHECK-RV64-NEXT: j .LBB61_1023
; CHECK-RV64-NEXT: .LBB61_525: # %else2038
-; CHECK-RV64-NEXT: bgez a2, .LBB61_526
+; CHECK-RV64-NEXT: bgez a1, .LBB61_526
; CHECK-RV64-NEXT: j .LBB61_1024
; CHECK-RV64-NEXT: .LBB61_526: # %else2042
; CHECK-RV64-NEXT: ret
; CHECK-RV64-NEXT: .LBB61_527: # %cond.load
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vmv1r.v v16, v8
; CHECK-RV64-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: bnez a2, .LBB61_528
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: bnez a1, .LBB61_528
; CHECK-RV64-NEXT: j .LBB61_2
; CHECK-RV64-NEXT: .LBB61_528: # %cond.load1
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vsetivli zero, 2, e8, m1, tu, ma
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: bnez a2, .LBB61_529
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: bnez a1, .LBB61_529
; CHECK-RV64-NEXT: j .LBB61_3
; CHECK-RV64-NEXT: .LBB61_529: # %cond.load5
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 2
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: bnez a2, .LBB61_530
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: bnez a1, .LBB61_530
; CHECK-RV64-NEXT: j .LBB61_4
; CHECK-RV64-NEXT: .LBB61_530: # %cond.load9
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 3
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: bnez a2, .LBB61_531
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: bnez a1, .LBB61_531
; CHECK-RV64-NEXT: j .LBB61_5
; CHECK-RV64-NEXT: .LBB61_531: # %cond.load13
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 5, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 4
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: bnez a2, .LBB61_532
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: bnez a1, .LBB61_532
; CHECK-RV64-NEXT: j .LBB61_6
; CHECK-RV64-NEXT: .LBB61_532: # %cond.load17
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 6, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 5
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: bnez a2, .LBB61_533
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: bnez a1, .LBB61_533
; CHECK-RV64-NEXT: j .LBB61_7
; CHECK-RV64-NEXT: .LBB61_533: # %cond.load21
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 7, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 6
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: bnez a2, .LBB61_534
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: bnez a1, .LBB61_534
; CHECK-RV64-NEXT: j .LBB61_8
; CHECK-RV64-NEXT: .LBB61_534: # %cond.load25
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 7
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: bnez a2, .LBB61_535
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: bnez a1, .LBB61_535
; CHECK-RV64-NEXT: j .LBB61_9
; CHECK-RV64-NEXT: .LBB61_535: # %cond.load29
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 9, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 8
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: bnez a2, .LBB61_536
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: bnez a1, .LBB61_536
; CHECK-RV64-NEXT: j .LBB61_10
; CHECK-RV64-NEXT: .LBB61_536: # %cond.load33
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 10, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 9
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: bnez a2, .LBB61_537
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: bnez a1, .LBB61_537
; CHECK-RV64-NEXT: j .LBB61_11
; CHECK-RV64-NEXT: .LBB61_537: # %cond.load37
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 11, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 10
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bltz a2, .LBB61_538
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bltz a1, .LBB61_538
; CHECK-RV64-NEXT: j .LBB61_12
; CHECK-RV64-NEXT: .LBB61_538: # %cond.load41
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 12, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 11
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bltz a2, .LBB61_539
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bltz a1, .LBB61_539
; CHECK-RV64-NEXT: j .LBB61_13
; CHECK-RV64-NEXT: .LBB61_539: # %cond.load45
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 13, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 12
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bltz a2, .LBB61_540
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bltz a1, .LBB61_540
; CHECK-RV64-NEXT: j .LBB61_14
; CHECK-RV64-NEXT: .LBB61_540: # %cond.load49
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 14, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 13
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bltz a2, .LBB61_541
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bltz a1, .LBB61_541
; CHECK-RV64-NEXT: j .LBB61_15
; CHECK-RV64-NEXT: .LBB61_541: # %cond.load53
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 15, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 14
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bltz a2, .LBB61_542
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bltz a1, .LBB61_542
; CHECK-RV64-NEXT: j .LBB61_16
; CHECK-RV64-NEXT: .LBB61_542: # %cond.load57
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 16, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 15
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bltz a2, .LBB61_543
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bltz a1, .LBB61_543
; CHECK-RV64-NEXT: j .LBB61_17
; CHECK-RV64-NEXT: .LBB61_543: # %cond.load61
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 17, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 16
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bltz a2, .LBB61_544
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bltz a1, .LBB61_544
; CHECK-RV64-NEXT: j .LBB61_18
; CHECK-RV64-NEXT: .LBB61_544: # %cond.load65
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 18, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 17
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bltz a2, .LBB61_545
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bltz a1, .LBB61_545
; CHECK-RV64-NEXT: j .LBB61_19
; CHECK-RV64-NEXT: .LBB61_545: # %cond.load69
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 19, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 18
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bltz a2, .LBB61_546
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bltz a1, .LBB61_546
; CHECK-RV64-NEXT: j .LBB61_20
; CHECK-RV64-NEXT: .LBB61_546: # %cond.load73
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 20, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 19
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bltz a2, .LBB61_547
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bltz a1, .LBB61_547
; CHECK-RV64-NEXT: j .LBB61_21
; CHECK-RV64-NEXT: .LBB61_547: # %cond.load77
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 21, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 20
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bltz a2, .LBB61_548
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bltz a1, .LBB61_548
; CHECK-RV64-NEXT: j .LBB61_22
; CHECK-RV64-NEXT: .LBB61_548: # %cond.load81
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 22, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 21
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bltz a2, .LBB61_549
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bltz a1, .LBB61_549
; CHECK-RV64-NEXT: j .LBB61_23
; CHECK-RV64-NEXT: .LBB61_549: # %cond.load85
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 23, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 22
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bltz a2, .LBB61_550
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bltz a1, .LBB61_550
; CHECK-RV64-NEXT: j .LBB61_24
; CHECK-RV64-NEXT: .LBB61_550: # %cond.load89
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 24, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 23
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bltz a2, .LBB61_551
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bltz a1, .LBB61_551
; CHECK-RV64-NEXT: j .LBB61_25
; CHECK-RV64-NEXT: .LBB61_551: # %cond.load93
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 25, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 24
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bltz a2, .LBB61_552
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bltz a1, .LBB61_552
; CHECK-RV64-NEXT: j .LBB61_26
; CHECK-RV64-NEXT: .LBB61_552: # %cond.load97
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 26, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 25
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bltz a2, .LBB61_553
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bltz a1, .LBB61_553
; CHECK-RV64-NEXT: j .LBB61_27
; CHECK-RV64-NEXT: .LBB61_553: # %cond.load101
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 27, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 26
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bltz a2, .LBB61_554
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bltz a1, .LBB61_554
; CHECK-RV64-NEXT: j .LBB61_28
; CHECK-RV64-NEXT: .LBB61_554: # %cond.load105
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 28, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 27
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bltz a2, .LBB61_555
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bltz a1, .LBB61_555
; CHECK-RV64-NEXT: j .LBB61_29
; CHECK-RV64-NEXT: .LBB61_555: # %cond.load109
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 29, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 28
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bltz a2, .LBB61_556
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bltz a1, .LBB61_556
; CHECK-RV64-NEXT: j .LBB61_30
; CHECK-RV64-NEXT: .LBB61_556: # %cond.load113
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 30, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 29
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bltz a2, .LBB61_557
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bltz a1, .LBB61_557
; CHECK-RV64-NEXT: j .LBB61_31
; CHECK-RV64-NEXT: .LBB61_557: # %cond.load117
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vsetivli zero, 31, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 30
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bltz a2, .LBB61_558
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bltz a1, .LBB61_558
; CHECK-RV64-NEXT: j .LBB61_32
; CHECK-RV64-NEXT: .LBB61_558: # %cond.load121
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 32
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
; CHECK-RV64-NEXT: vslideup.vi v17, v16, 31
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bltz a2, .LBB61_559
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bltz a1, .LBB61_559
; CHECK-RV64-NEXT: j .LBB61_33
; CHECK-RV64-NEXT: .LBB61_559: # %cond.load125
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 33
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 32
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 32
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bltz a2, .LBB61_560
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bltz a1, .LBB61_560
; CHECK-RV64-NEXT: j .LBB61_34
; CHECK-RV64-NEXT: .LBB61_560: # %cond.load129
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 34
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 33
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 33
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bltz a2, .LBB61_561
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bltz a1, .LBB61_561
; CHECK-RV64-NEXT: j .LBB61_35
; CHECK-RV64-NEXT: .LBB61_561: # %cond.load133
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 35
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 34
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 34
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bltz a2, .LBB61_562
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bltz a1, .LBB61_562
; CHECK-RV64-NEXT: j .LBB61_36
; CHECK-RV64-NEXT: .LBB61_562: # %cond.load137
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 36
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 35
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 35
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bltz a2, .LBB61_563
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bltz a1, .LBB61_563
; CHECK-RV64-NEXT: j .LBB61_37
; CHECK-RV64-NEXT: .LBB61_563: # %cond.load141
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 37
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 36
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 36
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bltz a2, .LBB61_564
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bltz a1, .LBB61_564
; CHECK-RV64-NEXT: j .LBB61_38
; CHECK-RV64-NEXT: .LBB61_564: # %cond.load145
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 38
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 37
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 37
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bltz a2, .LBB61_565
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bltz a1, .LBB61_565
; CHECK-RV64-NEXT: j .LBB61_39
; CHECK-RV64-NEXT: .LBB61_565: # %cond.load149
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 39
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 38
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 38
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bltz a2, .LBB61_566
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bltz a1, .LBB61_566
; CHECK-RV64-NEXT: j .LBB61_40
; CHECK-RV64-NEXT: .LBB61_566: # %cond.load153
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 40
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 39
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 39
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bltz a2, .LBB61_567
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bltz a1, .LBB61_567
; CHECK-RV64-NEXT: j .LBB61_41
; CHECK-RV64-NEXT: .LBB61_567: # %cond.load157
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 41
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 40
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 40
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bltz a2, .LBB61_568
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bltz a1, .LBB61_568
; CHECK-RV64-NEXT: j .LBB61_42
; CHECK-RV64-NEXT: .LBB61_568: # %cond.load161
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 42
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 41
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 41
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bltz a2, .LBB61_569
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bltz a1, .LBB61_569
; CHECK-RV64-NEXT: j .LBB61_43
; CHECK-RV64-NEXT: .LBB61_569: # %cond.load165
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 43
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 42
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 42
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bltz a2, .LBB61_570
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bltz a1, .LBB61_570
; CHECK-RV64-NEXT: j .LBB61_44
; CHECK-RV64-NEXT: .LBB61_570: # %cond.load169
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 44
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 43
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 43
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bltz a2, .LBB61_571
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bltz a1, .LBB61_571
; CHECK-RV64-NEXT: j .LBB61_45
; CHECK-RV64-NEXT: .LBB61_571: # %cond.load173
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 45
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 44
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 44
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bltz a2, .LBB61_572
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bltz a1, .LBB61_572
; CHECK-RV64-NEXT: j .LBB61_46
; CHECK-RV64-NEXT: .LBB61_572: # %cond.load177
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 46
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 45
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 45
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bltz a2, .LBB61_573
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bltz a1, .LBB61_573
; CHECK-RV64-NEXT: j .LBB61_47
; CHECK-RV64-NEXT: .LBB61_573: # %cond.load181
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 47
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 46
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 46
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bltz a2, .LBB61_574
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bltz a1, .LBB61_574
; CHECK-RV64-NEXT: j .LBB61_48
; CHECK-RV64-NEXT: .LBB61_574: # %cond.load185
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 48
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 47
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 47
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bltz a2, .LBB61_575
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bltz a1, .LBB61_575
; CHECK-RV64-NEXT: j .LBB61_49
; CHECK-RV64-NEXT: .LBB61_575: # %cond.load189
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 49
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 48
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 48
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bltz a2, .LBB61_576
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bltz a1, .LBB61_576
; CHECK-RV64-NEXT: j .LBB61_50
; CHECK-RV64-NEXT: .LBB61_576: # %cond.load193
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 50
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 49
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 49
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bltz a2, .LBB61_577
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bltz a1, .LBB61_577
; CHECK-RV64-NEXT: j .LBB61_51
; CHECK-RV64-NEXT: .LBB61_577: # %cond.load197
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 51
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 50
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 50
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bltz a2, .LBB61_578
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bltz a1, .LBB61_578
; CHECK-RV64-NEXT: j .LBB61_52
; CHECK-RV64-NEXT: .LBB61_578: # %cond.load201
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 52
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 51
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 51
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bltz a2, .LBB61_579
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bltz a1, .LBB61_579
; CHECK-RV64-NEXT: j .LBB61_53
; CHECK-RV64-NEXT: .LBB61_579: # %cond.load205
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 53
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 52
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 52
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bltz a2, .LBB61_580
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bltz a1, .LBB61_580
; CHECK-RV64-NEXT: j .LBB61_54
; CHECK-RV64-NEXT: .LBB61_580: # %cond.load209
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 54
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 53
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 53
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bltz a2, .LBB61_581
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bltz a1, .LBB61_581
; CHECK-RV64-NEXT: j .LBB61_55
; CHECK-RV64-NEXT: .LBB61_581: # %cond.load213
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 55
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 54
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 54
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bltz a2, .LBB61_582
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bltz a1, .LBB61_582
; CHECK-RV64-NEXT: j .LBB61_56
; CHECK-RV64-NEXT: .LBB61_582: # %cond.load217
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 56
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 55
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 55
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bltz a2, .LBB61_583
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bltz a1, .LBB61_583
; CHECK-RV64-NEXT: j .LBB61_57
; CHECK-RV64-NEXT: .LBB61_583: # %cond.load221
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 57
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 56
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 56
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bltz a2, .LBB61_584
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bltz a1, .LBB61_584
; CHECK-RV64-NEXT: j .LBB61_58
; CHECK-RV64-NEXT: .LBB61_584: # %cond.load225
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 58
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 57
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 57
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bltz a2, .LBB61_585
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bltz a1, .LBB61_585
; CHECK-RV64-NEXT: j .LBB61_59
; CHECK-RV64-NEXT: .LBB61_585: # %cond.load229
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 59
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 58
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 58
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bltz a2, .LBB61_586
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bltz a1, .LBB61_586
; CHECK-RV64-NEXT: j .LBB61_60
; CHECK-RV64-NEXT: .LBB61_586: # %cond.load233
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 60
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 59
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 59
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bltz a2, .LBB61_587
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bltz a1, .LBB61_587
; CHECK-RV64-NEXT: j .LBB61_61
; CHECK-RV64-NEXT: .LBB61_587: # %cond.load237
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 61
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a2, 60
-; CHECK-RV64-NEXT: vslideup.vx v17, v16, a2
+; CHECK-RV64-NEXT: li a1, 60
+; CHECK-RV64-NEXT: vslideup.vx v17, v16, a1
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_1025
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_1025
; CHECK-RV64-NEXT: j .LBB61_62
; CHECK-RV64-NEXT: .LBB61_1025: # %cond.load237
; CHECK-RV64-NEXT: j .LBB61_63
; CHECK-RV64-NEXT: .LBB61_588: # %cond.load249
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: vmv1r.v v17, v8
-; CHECK-RV64-NEXT: li a1, 64
+; CHECK-RV64-NEXT: li a2, 64
; CHECK-RV64-NEXT: li a3, 63
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m1, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v17, v16, a3
; CHECK-RV64-NEXT: vmv1r.v v8, v17
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: bnez a1, .LBB61_589
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: bnez a2, .LBB61_589
; CHECK-RV64-NEXT: j .LBB61_67
; CHECK-RV64-NEXT: .LBB61_589: # %cond.load253
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 65
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 64
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 64
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: bnez a1, .LBB61_590
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: bnez a2, .LBB61_590
; CHECK-RV64-NEXT: j .LBB61_68
; CHECK-RV64-NEXT: .LBB61_590: # %cond.load257
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 66
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 65
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 65
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: bnez a1, .LBB61_591
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: bnez a2, .LBB61_591
; CHECK-RV64-NEXT: j .LBB61_69
; CHECK-RV64-NEXT: .LBB61_591: # %cond.load261
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 67
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 66
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 66
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: bnez a1, .LBB61_592
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: bnez a2, .LBB61_592
; CHECK-RV64-NEXT: j .LBB61_70
; CHECK-RV64-NEXT: .LBB61_592: # %cond.load265
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 68
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 67
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 67
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: bnez a1, .LBB61_593
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: bnez a2, .LBB61_593
; CHECK-RV64-NEXT: j .LBB61_71
; CHECK-RV64-NEXT: .LBB61_593: # %cond.load269
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 69
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 68
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 68
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: bnez a1, .LBB61_594
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: bnez a2, .LBB61_594
; CHECK-RV64-NEXT: j .LBB61_72
; CHECK-RV64-NEXT: .LBB61_594: # %cond.load273
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 70
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 69
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 69
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: bnez a1, .LBB61_595
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: bnez a2, .LBB61_595
; CHECK-RV64-NEXT: j .LBB61_73
; CHECK-RV64-NEXT: .LBB61_595: # %cond.load277
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 71
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 70
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 70
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: bnez a1, .LBB61_596
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: bnez a2, .LBB61_596
; CHECK-RV64-NEXT: j .LBB61_74
; CHECK-RV64-NEXT: .LBB61_596: # %cond.load281
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 72
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 71
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 71
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: bnez a1, .LBB61_597
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: bnez a2, .LBB61_597
; CHECK-RV64-NEXT: j .LBB61_75
; CHECK-RV64-NEXT: .LBB61_597: # %cond.load285
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 73
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 72
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 72
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: bnez a1, .LBB61_598
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: bnez a2, .LBB61_598
; CHECK-RV64-NEXT: j .LBB61_76
; CHECK-RV64-NEXT: .LBB61_598: # %cond.load289
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 74
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 73
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 73
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: bnez a1, .LBB61_599
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: bnez a2, .LBB61_599
; CHECK-RV64-NEXT: j .LBB61_77
; CHECK-RV64-NEXT: .LBB61_599: # %cond.load293
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 75
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 74
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 74
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bltz a1, .LBB61_600
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bltz a2, .LBB61_600
; CHECK-RV64-NEXT: j .LBB61_78
; CHECK-RV64-NEXT: .LBB61_600: # %cond.load297
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 76
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 75
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 75
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bltz a1, .LBB61_601
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bltz a2, .LBB61_601
; CHECK-RV64-NEXT: j .LBB61_79
; CHECK-RV64-NEXT: .LBB61_601: # %cond.load301
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 77
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 76
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 76
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bltz a1, .LBB61_602
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bltz a2, .LBB61_602
; CHECK-RV64-NEXT: j .LBB61_80
; CHECK-RV64-NEXT: .LBB61_602: # %cond.load305
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 78
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 77
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 77
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bltz a1, .LBB61_603
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bltz a2, .LBB61_603
; CHECK-RV64-NEXT: j .LBB61_81
; CHECK-RV64-NEXT: .LBB61_603: # %cond.load309
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 79
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 78
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 78
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bltz a1, .LBB61_604
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bltz a2, .LBB61_604
; CHECK-RV64-NEXT: j .LBB61_82
; CHECK-RV64-NEXT: .LBB61_604: # %cond.load313
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 80
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 79
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 79
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bltz a1, .LBB61_605
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bltz a2, .LBB61_605
; CHECK-RV64-NEXT: j .LBB61_83
; CHECK-RV64-NEXT: .LBB61_605: # %cond.load317
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 81
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 80
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 80
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bltz a1, .LBB61_606
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bltz a2, .LBB61_606
; CHECK-RV64-NEXT: j .LBB61_84
; CHECK-RV64-NEXT: .LBB61_606: # %cond.load321
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 82
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 81
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 81
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bltz a1, .LBB61_607
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bltz a2, .LBB61_607
; CHECK-RV64-NEXT: j .LBB61_85
; CHECK-RV64-NEXT: .LBB61_607: # %cond.load325
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 83
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 82
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 82
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bltz a1, .LBB61_608
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bltz a2, .LBB61_608
; CHECK-RV64-NEXT: j .LBB61_86
; CHECK-RV64-NEXT: .LBB61_608: # %cond.load329
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 84
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 83
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 83
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bltz a1, .LBB61_609
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bltz a2, .LBB61_609
; CHECK-RV64-NEXT: j .LBB61_87
; CHECK-RV64-NEXT: .LBB61_609: # %cond.load333
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 85
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 84
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 84
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bltz a1, .LBB61_610
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bltz a2, .LBB61_610
; CHECK-RV64-NEXT: j .LBB61_88
; CHECK-RV64-NEXT: .LBB61_610: # %cond.load337
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 86
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 85
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 85
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bltz a1, .LBB61_611
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bltz a2, .LBB61_611
; CHECK-RV64-NEXT: j .LBB61_89
; CHECK-RV64-NEXT: .LBB61_611: # %cond.load341
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 87
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 86
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 86
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bltz a1, .LBB61_612
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bltz a2, .LBB61_612
; CHECK-RV64-NEXT: j .LBB61_90
; CHECK-RV64-NEXT: .LBB61_612: # %cond.load345
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 88
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 87
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 87
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bltz a1, .LBB61_613
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bltz a2, .LBB61_613
; CHECK-RV64-NEXT: j .LBB61_91
; CHECK-RV64-NEXT: .LBB61_613: # %cond.load349
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 89
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 88
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 88
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bltz a1, .LBB61_614
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bltz a2, .LBB61_614
; CHECK-RV64-NEXT: j .LBB61_92
; CHECK-RV64-NEXT: .LBB61_614: # %cond.load353
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 90
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 89
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 89
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bltz a1, .LBB61_615
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bltz a2, .LBB61_615
; CHECK-RV64-NEXT: j .LBB61_93
; CHECK-RV64-NEXT: .LBB61_615: # %cond.load357
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 91
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 90
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 90
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bltz a1, .LBB61_616
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bltz a2, .LBB61_616
; CHECK-RV64-NEXT: j .LBB61_94
; CHECK-RV64-NEXT: .LBB61_616: # %cond.load361
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 92
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 91
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 91
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bltz a1, .LBB61_617
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bltz a2, .LBB61_617
; CHECK-RV64-NEXT: j .LBB61_95
; CHECK-RV64-NEXT: .LBB61_617: # %cond.load365
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 93
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 92
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 92
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bltz a1, .LBB61_618
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bltz a2, .LBB61_618
; CHECK-RV64-NEXT: j .LBB61_96
; CHECK-RV64-NEXT: .LBB61_618: # %cond.load369
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 94
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 93
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 93
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bltz a1, .LBB61_619
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bltz a2, .LBB61_619
; CHECK-RV64-NEXT: j .LBB61_97
; CHECK-RV64-NEXT: .LBB61_619: # %cond.load373
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 95
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 94
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 94
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bltz a1, .LBB61_620
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bltz a2, .LBB61_620
; CHECK-RV64-NEXT: j .LBB61_98
; CHECK-RV64-NEXT: .LBB61_620: # %cond.load377
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 96
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 95
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 95
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bltz a1, .LBB61_621
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bltz a2, .LBB61_621
; CHECK-RV64-NEXT: j .LBB61_99
; CHECK-RV64-NEXT: .LBB61_621: # %cond.load381
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 97
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 96
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 96
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bltz a1, .LBB61_622
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bltz a2, .LBB61_622
; CHECK-RV64-NEXT: j .LBB61_100
; CHECK-RV64-NEXT: .LBB61_622: # %cond.load385
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 98
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 97
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 97
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bltz a1, .LBB61_623
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bltz a2, .LBB61_623
; CHECK-RV64-NEXT: j .LBB61_101
; CHECK-RV64-NEXT: .LBB61_623: # %cond.load389
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 99
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 98
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 98
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bltz a1, .LBB61_624
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bltz a2, .LBB61_624
; CHECK-RV64-NEXT: j .LBB61_102
; CHECK-RV64-NEXT: .LBB61_624: # %cond.load393
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 100
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 99
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 99
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bltz a1, .LBB61_625
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bltz a2, .LBB61_625
; CHECK-RV64-NEXT: j .LBB61_103
; CHECK-RV64-NEXT: .LBB61_625: # %cond.load397
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 101
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 100
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 100
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bltz a1, .LBB61_626
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bltz a2, .LBB61_626
; CHECK-RV64-NEXT: j .LBB61_104
; CHECK-RV64-NEXT: .LBB61_626: # %cond.load401
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 102
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 101
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 101
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bltz a1, .LBB61_627
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bltz a2, .LBB61_627
; CHECK-RV64-NEXT: j .LBB61_105
; CHECK-RV64-NEXT: .LBB61_627: # %cond.load405
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 103
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 102
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 102
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bltz a1, .LBB61_628
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bltz a2, .LBB61_628
; CHECK-RV64-NEXT: j .LBB61_106
; CHECK-RV64-NEXT: .LBB61_628: # %cond.load409
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 104
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 103
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 103
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bltz a1, .LBB61_629
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bltz a2, .LBB61_629
; CHECK-RV64-NEXT: j .LBB61_107
; CHECK-RV64-NEXT: .LBB61_629: # %cond.load413
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 105
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 104
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 104
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bltz a1, .LBB61_630
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bltz a2, .LBB61_630
; CHECK-RV64-NEXT: j .LBB61_108
; CHECK-RV64-NEXT: .LBB61_630: # %cond.load417
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 106
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 105
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 105
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bltz a1, .LBB61_631
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bltz a2, .LBB61_631
; CHECK-RV64-NEXT: j .LBB61_109
; CHECK-RV64-NEXT: .LBB61_631: # %cond.load421
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 107
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 106
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 106
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bltz a1, .LBB61_632
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bltz a2, .LBB61_632
; CHECK-RV64-NEXT: j .LBB61_110
; CHECK-RV64-NEXT: .LBB61_632: # %cond.load425
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 108
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 107
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 107
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bltz a1, .LBB61_633
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bltz a2, .LBB61_633
; CHECK-RV64-NEXT: j .LBB61_111
; CHECK-RV64-NEXT: .LBB61_633: # %cond.load429
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 109
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 108
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 108
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bltz a1, .LBB61_634
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bltz a2, .LBB61_634
; CHECK-RV64-NEXT: j .LBB61_112
; CHECK-RV64-NEXT: .LBB61_634: # %cond.load433
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 110
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 109
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 109
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bltz a1, .LBB61_635
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bltz a2, .LBB61_635
; CHECK-RV64-NEXT: j .LBB61_113
; CHECK-RV64-NEXT: .LBB61_635: # %cond.load437
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 111
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 110
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 110
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bltz a1, .LBB61_636
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bltz a2, .LBB61_636
; CHECK-RV64-NEXT: j .LBB61_114
; CHECK-RV64-NEXT: .LBB61_636: # %cond.load441
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 112
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 111
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 111
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bltz a1, .LBB61_637
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bltz a2, .LBB61_637
; CHECK-RV64-NEXT: j .LBB61_115
; CHECK-RV64-NEXT: .LBB61_637: # %cond.load445
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 113
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 112
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 112
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bltz a1, .LBB61_638
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bltz a2, .LBB61_638
; CHECK-RV64-NEXT: j .LBB61_116
; CHECK-RV64-NEXT: .LBB61_638: # %cond.load449
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 114
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 113
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 113
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bltz a1, .LBB61_639
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bltz a2, .LBB61_639
; CHECK-RV64-NEXT: j .LBB61_117
; CHECK-RV64-NEXT: .LBB61_639: # %cond.load453
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 115
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 114
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 114
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bltz a1, .LBB61_640
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bltz a2, .LBB61_640
; CHECK-RV64-NEXT: j .LBB61_118
; CHECK-RV64-NEXT: .LBB61_640: # %cond.load457
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 116
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 115
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 115
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bltz a1, .LBB61_641
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bltz a2, .LBB61_641
; CHECK-RV64-NEXT: j .LBB61_119
; CHECK-RV64-NEXT: .LBB61_641: # %cond.load461
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 117
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 116
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 116
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bltz a1, .LBB61_642
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bltz a2, .LBB61_642
; CHECK-RV64-NEXT: j .LBB61_120
; CHECK-RV64-NEXT: .LBB61_642: # %cond.load465
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 118
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 117
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 117
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bltz a1, .LBB61_643
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bltz a2, .LBB61_643
; CHECK-RV64-NEXT: j .LBB61_121
; CHECK-RV64-NEXT: .LBB61_643: # %cond.load469
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 119
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 118
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 118
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bltz a1, .LBB61_644
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bltz a2, .LBB61_644
; CHECK-RV64-NEXT: j .LBB61_122
; CHECK-RV64-NEXT: .LBB61_644: # %cond.load473
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 120
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 119
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 119
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bltz a1, .LBB61_645
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bltz a2, .LBB61_645
; CHECK-RV64-NEXT: j .LBB61_123
; CHECK-RV64-NEXT: .LBB61_645: # %cond.load477
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 121
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 120
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 120
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bltz a1, .LBB61_646
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bltz a2, .LBB61_646
; CHECK-RV64-NEXT: j .LBB61_124
; CHECK-RV64-NEXT: .LBB61_646: # %cond.load481
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 122
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 121
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 121
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bltz a1, .LBB61_647
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bltz a2, .LBB61_647
; CHECK-RV64-NEXT: j .LBB61_125
; CHECK-RV64-NEXT: .LBB61_647: # %cond.load485
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 123
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 122
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 122
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bltz a1, .LBB61_648
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bltz a2, .LBB61_648
; CHECK-RV64-NEXT: j .LBB61_126
; CHECK-RV64-NEXT: .LBB61_648: # %cond.load489
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 124
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 123
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 123
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bltz a1, .LBB61_649
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bltz a2, .LBB61_649
; CHECK-RV64-NEXT: j .LBB61_127
; CHECK-RV64-NEXT: .LBB61_649: # %cond.load493
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 125
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m2, tu, ma
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a1
-; CHECK-RV64-NEXT: li a1, 124
-; CHECK-RV64-NEXT: vslideup.vx v16, v18, a1
+; CHECK-RV64-NEXT: vmv.s.x v18, a2
+; CHECK-RV64-NEXT: li a2, 124
+; CHECK-RV64-NEXT: vslideup.vx v16, v18, a2
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_1026
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_1026
; CHECK-RV64-NEXT: j .LBB61_128
; CHECK-RV64-NEXT: .LBB61_1026: # %cond.load493
; CHECK-RV64-NEXT: j .LBB61_129
; CHECK-RV64-NEXT: .LBB61_650: # %cond.load505
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vmv2r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v18, a2
-; CHECK-RV64-NEXT: li a2, 128
+; CHECK-RV64-NEXT: vmv.s.x v18, a1
+; CHECK-RV64-NEXT: li a1, 128
; CHECK-RV64-NEXT: li a3, 127
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m2, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v18, a3
; CHECK-RV64-NEXT: vmv2r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: bnez a2, .LBB61_651
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: bnez a1, .LBB61_651
; CHECK-RV64-NEXT: j .LBB61_133
; CHECK-RV64-NEXT: .LBB61_651: # %cond.load509
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 129
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 128
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 128
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: bnez a2, .LBB61_652
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: bnez a1, .LBB61_652
; CHECK-RV64-NEXT: j .LBB61_134
; CHECK-RV64-NEXT: .LBB61_652: # %cond.load513
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 130
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 129
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 129
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: bnez a2, .LBB61_653
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: bnez a1, .LBB61_653
; CHECK-RV64-NEXT: j .LBB61_135
; CHECK-RV64-NEXT: .LBB61_653: # %cond.load517
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 131
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 130
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 130
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: bnez a2, .LBB61_654
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: bnez a1, .LBB61_654
; CHECK-RV64-NEXT: j .LBB61_136
; CHECK-RV64-NEXT: .LBB61_654: # %cond.load521
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 132
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 131
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 131
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: bnez a2, .LBB61_655
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: bnez a1, .LBB61_655
; CHECK-RV64-NEXT: j .LBB61_137
; CHECK-RV64-NEXT: .LBB61_655: # %cond.load525
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 133
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 132
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 132
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: bnez a2, .LBB61_656
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: bnez a1, .LBB61_656
; CHECK-RV64-NEXT: j .LBB61_138
; CHECK-RV64-NEXT: .LBB61_656: # %cond.load529
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 134
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 133
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 133
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: bnez a2, .LBB61_657
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: bnez a1, .LBB61_657
; CHECK-RV64-NEXT: j .LBB61_139
; CHECK-RV64-NEXT: .LBB61_657: # %cond.load533
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 135
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 134
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 134
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: bnez a2, .LBB61_658
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: bnez a1, .LBB61_658
; CHECK-RV64-NEXT: j .LBB61_140
; CHECK-RV64-NEXT: .LBB61_658: # %cond.load537
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 136
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 135
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 135
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: bnez a2, .LBB61_659
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: bnez a1, .LBB61_659
; CHECK-RV64-NEXT: j .LBB61_141
; CHECK-RV64-NEXT: .LBB61_659: # %cond.load541
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 137
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 136
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 136
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: bnez a2, .LBB61_660
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: bnez a1, .LBB61_660
; CHECK-RV64-NEXT: j .LBB61_142
; CHECK-RV64-NEXT: .LBB61_660: # %cond.load545
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 138
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 137
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 137
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: bnez a2, .LBB61_661
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: bnez a1, .LBB61_661
; CHECK-RV64-NEXT: j .LBB61_143
; CHECK-RV64-NEXT: .LBB61_661: # %cond.load549
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 139
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 138
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 138
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bltz a2, .LBB61_662
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bltz a1, .LBB61_662
; CHECK-RV64-NEXT: j .LBB61_144
; CHECK-RV64-NEXT: .LBB61_662: # %cond.load553
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 140
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 139
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 139
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bltz a2, .LBB61_663
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bltz a1, .LBB61_663
; CHECK-RV64-NEXT: j .LBB61_145
; CHECK-RV64-NEXT: .LBB61_663: # %cond.load557
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 141
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 140
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 140
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bltz a2, .LBB61_664
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bltz a1, .LBB61_664
; CHECK-RV64-NEXT: j .LBB61_146
; CHECK-RV64-NEXT: .LBB61_664: # %cond.load561
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 142
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 141
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 141
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bltz a2, .LBB61_665
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bltz a1, .LBB61_665
; CHECK-RV64-NEXT: j .LBB61_147
; CHECK-RV64-NEXT: .LBB61_665: # %cond.load565
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 143
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 142
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 142
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bltz a2, .LBB61_666
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bltz a1, .LBB61_666
; CHECK-RV64-NEXT: j .LBB61_148
; CHECK-RV64-NEXT: .LBB61_666: # %cond.load569
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 144
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 143
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 143
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bltz a2, .LBB61_667
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bltz a1, .LBB61_667
; CHECK-RV64-NEXT: j .LBB61_149
; CHECK-RV64-NEXT: .LBB61_667: # %cond.load573
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 145
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 144
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 144
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bltz a2, .LBB61_668
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bltz a1, .LBB61_668
; CHECK-RV64-NEXT: j .LBB61_150
; CHECK-RV64-NEXT: .LBB61_668: # %cond.load577
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 146
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 145
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 145
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bltz a2, .LBB61_669
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bltz a1, .LBB61_669
; CHECK-RV64-NEXT: j .LBB61_151
; CHECK-RV64-NEXT: .LBB61_669: # %cond.load581
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 147
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 146
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 146
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bltz a2, .LBB61_670
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bltz a1, .LBB61_670
; CHECK-RV64-NEXT: j .LBB61_152
; CHECK-RV64-NEXT: .LBB61_670: # %cond.load585
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 148
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 147
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 147
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bltz a2, .LBB61_671
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bltz a1, .LBB61_671
; CHECK-RV64-NEXT: j .LBB61_153
; CHECK-RV64-NEXT: .LBB61_671: # %cond.load589
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 149
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 148
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 148
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bltz a2, .LBB61_672
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bltz a1, .LBB61_672
; CHECK-RV64-NEXT: j .LBB61_154
; CHECK-RV64-NEXT: .LBB61_672: # %cond.load593
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 150
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 149
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 149
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bltz a2, .LBB61_673
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bltz a1, .LBB61_673
; CHECK-RV64-NEXT: j .LBB61_155
; CHECK-RV64-NEXT: .LBB61_673: # %cond.load597
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 151
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 150
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 150
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bltz a2, .LBB61_674
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bltz a1, .LBB61_674
; CHECK-RV64-NEXT: j .LBB61_156
; CHECK-RV64-NEXT: .LBB61_674: # %cond.load601
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 152
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 151
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 151
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bltz a2, .LBB61_675
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bltz a1, .LBB61_675
; CHECK-RV64-NEXT: j .LBB61_157
; CHECK-RV64-NEXT: .LBB61_675: # %cond.load605
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 153
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 152
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 152
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bltz a2, .LBB61_676
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bltz a1, .LBB61_676
; CHECK-RV64-NEXT: j .LBB61_158
; CHECK-RV64-NEXT: .LBB61_676: # %cond.load609
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 154
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 153
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 153
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bltz a2, .LBB61_677
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bltz a1, .LBB61_677
; CHECK-RV64-NEXT: j .LBB61_159
; CHECK-RV64-NEXT: .LBB61_677: # %cond.load613
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 155
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 154
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 154
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bltz a2, .LBB61_678
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bltz a1, .LBB61_678
; CHECK-RV64-NEXT: j .LBB61_160
; CHECK-RV64-NEXT: .LBB61_678: # %cond.load617
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 156
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 155
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 155
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bltz a2, .LBB61_679
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bltz a1, .LBB61_679
; CHECK-RV64-NEXT: j .LBB61_161
; CHECK-RV64-NEXT: .LBB61_679: # %cond.load621
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 157
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 156
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 156
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bltz a2, .LBB61_680
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bltz a1, .LBB61_680
; CHECK-RV64-NEXT: j .LBB61_162
; CHECK-RV64-NEXT: .LBB61_680: # %cond.load625
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 158
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 157
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 157
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bltz a2, .LBB61_681
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bltz a1, .LBB61_681
; CHECK-RV64-NEXT: j .LBB61_163
; CHECK-RV64-NEXT: .LBB61_681: # %cond.load629
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 159
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 158
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 158
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bltz a2, .LBB61_682
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bltz a1, .LBB61_682
; CHECK-RV64-NEXT: j .LBB61_164
; CHECK-RV64-NEXT: .LBB61_682: # %cond.load633
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 160
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 159
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 159
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bltz a2, .LBB61_683
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bltz a1, .LBB61_683
; CHECK-RV64-NEXT: j .LBB61_165
; CHECK-RV64-NEXT: .LBB61_683: # %cond.load637
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 161
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 160
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 160
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bltz a2, .LBB61_684
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bltz a1, .LBB61_684
; CHECK-RV64-NEXT: j .LBB61_166
; CHECK-RV64-NEXT: .LBB61_684: # %cond.load641
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 162
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 161
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 161
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bltz a2, .LBB61_685
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bltz a1, .LBB61_685
; CHECK-RV64-NEXT: j .LBB61_167
; CHECK-RV64-NEXT: .LBB61_685: # %cond.load645
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 163
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 162
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 162
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bltz a2, .LBB61_686
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bltz a1, .LBB61_686
; CHECK-RV64-NEXT: j .LBB61_168
; CHECK-RV64-NEXT: .LBB61_686: # %cond.load649
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 164
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 163
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 163
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bltz a2, .LBB61_687
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bltz a1, .LBB61_687
; CHECK-RV64-NEXT: j .LBB61_169
; CHECK-RV64-NEXT: .LBB61_687: # %cond.load653
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 165
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 164
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 164
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bltz a2, .LBB61_688
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bltz a1, .LBB61_688
; CHECK-RV64-NEXT: j .LBB61_170
; CHECK-RV64-NEXT: .LBB61_688: # %cond.load657
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 166
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 165
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 165
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bltz a2, .LBB61_689
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bltz a1, .LBB61_689
; CHECK-RV64-NEXT: j .LBB61_171
; CHECK-RV64-NEXT: .LBB61_689: # %cond.load661
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 167
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 166
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 166
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bltz a2, .LBB61_690
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bltz a1, .LBB61_690
; CHECK-RV64-NEXT: j .LBB61_172
; CHECK-RV64-NEXT: .LBB61_690: # %cond.load665
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 168
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 167
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 167
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bltz a2, .LBB61_691
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bltz a1, .LBB61_691
; CHECK-RV64-NEXT: j .LBB61_173
; CHECK-RV64-NEXT: .LBB61_691: # %cond.load669
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 169
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 168
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 168
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bltz a2, .LBB61_692
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bltz a1, .LBB61_692
; CHECK-RV64-NEXT: j .LBB61_174
; CHECK-RV64-NEXT: .LBB61_692: # %cond.load673
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 170
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 169
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 169
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bltz a2, .LBB61_693
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bltz a1, .LBB61_693
; CHECK-RV64-NEXT: j .LBB61_175
; CHECK-RV64-NEXT: .LBB61_693: # %cond.load677
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 171
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 170
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 170
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bltz a2, .LBB61_694
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bltz a1, .LBB61_694
; CHECK-RV64-NEXT: j .LBB61_176
; CHECK-RV64-NEXT: .LBB61_694: # %cond.load681
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 172
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 171
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 171
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bltz a2, .LBB61_695
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bltz a1, .LBB61_695
; CHECK-RV64-NEXT: j .LBB61_177
; CHECK-RV64-NEXT: .LBB61_695: # %cond.load685
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 173
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 172
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 172
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bltz a2, .LBB61_696
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bltz a1, .LBB61_696
; CHECK-RV64-NEXT: j .LBB61_178
; CHECK-RV64-NEXT: .LBB61_696: # %cond.load689
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 174
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 173
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 173
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bltz a2, .LBB61_697
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bltz a1, .LBB61_697
; CHECK-RV64-NEXT: j .LBB61_179
; CHECK-RV64-NEXT: .LBB61_697: # %cond.load693
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 175
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 174
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 174
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bltz a2, .LBB61_698
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bltz a1, .LBB61_698
; CHECK-RV64-NEXT: j .LBB61_180
; CHECK-RV64-NEXT: .LBB61_698: # %cond.load697
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 176
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 175
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 175
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bltz a2, .LBB61_699
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bltz a1, .LBB61_699
; CHECK-RV64-NEXT: j .LBB61_181
; CHECK-RV64-NEXT: .LBB61_699: # %cond.load701
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 177
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 176
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 176
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bltz a2, .LBB61_700
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bltz a1, .LBB61_700
; CHECK-RV64-NEXT: j .LBB61_182
; CHECK-RV64-NEXT: .LBB61_700: # %cond.load705
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 178
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 177
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 177
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bltz a2, .LBB61_701
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bltz a1, .LBB61_701
; CHECK-RV64-NEXT: j .LBB61_183
; CHECK-RV64-NEXT: .LBB61_701: # %cond.load709
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 179
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 178
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 178
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bltz a2, .LBB61_702
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bltz a1, .LBB61_702
; CHECK-RV64-NEXT: j .LBB61_184
; CHECK-RV64-NEXT: .LBB61_702: # %cond.load713
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 180
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 179
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 179
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bltz a2, .LBB61_703
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bltz a1, .LBB61_703
; CHECK-RV64-NEXT: j .LBB61_185
; CHECK-RV64-NEXT: .LBB61_703: # %cond.load717
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 181
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 180
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 180
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bltz a2, .LBB61_704
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bltz a1, .LBB61_704
; CHECK-RV64-NEXT: j .LBB61_186
; CHECK-RV64-NEXT: .LBB61_704: # %cond.load721
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 182
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 181
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 181
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bltz a2, .LBB61_705
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bltz a1, .LBB61_705
; CHECK-RV64-NEXT: j .LBB61_187
; CHECK-RV64-NEXT: .LBB61_705: # %cond.load725
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 183
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 182
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 182
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bltz a2, .LBB61_706
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bltz a1, .LBB61_706
; CHECK-RV64-NEXT: j .LBB61_188
; CHECK-RV64-NEXT: .LBB61_706: # %cond.load729
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 184
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 183
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 183
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bltz a2, .LBB61_707
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bltz a1, .LBB61_707
; CHECK-RV64-NEXT: j .LBB61_189
; CHECK-RV64-NEXT: .LBB61_707: # %cond.load733
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 185
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 184
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 184
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bltz a2, .LBB61_708
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bltz a1, .LBB61_708
; CHECK-RV64-NEXT: j .LBB61_190
; CHECK-RV64-NEXT: .LBB61_708: # %cond.load737
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 186
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 185
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 185
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bltz a2, .LBB61_709
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bltz a1, .LBB61_709
; CHECK-RV64-NEXT: j .LBB61_191
; CHECK-RV64-NEXT: .LBB61_709: # %cond.load741
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 187
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 186
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 186
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bltz a2, .LBB61_710
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bltz a1, .LBB61_710
; CHECK-RV64-NEXT: j .LBB61_192
; CHECK-RV64-NEXT: .LBB61_710: # %cond.load745
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 188
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 187
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 187
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bltz a2, .LBB61_711
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bltz a1, .LBB61_711
; CHECK-RV64-NEXT: j .LBB61_193
; CHECK-RV64-NEXT: .LBB61_711: # %cond.load749
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 189
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 188
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 188
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_1027
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_1027
; CHECK-RV64-NEXT: j .LBB61_194
; CHECK-RV64-NEXT: .LBB61_1027: # %cond.load749
; CHECK-RV64-NEXT: j .LBB61_195
; CHECK-RV64-NEXT: .LBB61_712: # %cond.load761
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 192
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 192
; CHECK-RV64-NEXT: li a3, 191
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: bnez a1, .LBB61_713
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: bnez a2, .LBB61_713
; CHECK-RV64-NEXT: j .LBB61_199
; CHECK-RV64-NEXT: .LBB61_713: # %cond.load765
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 193
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 192
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 192
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: bnez a1, .LBB61_714
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: bnez a2, .LBB61_714
; CHECK-RV64-NEXT: j .LBB61_200
; CHECK-RV64-NEXT: .LBB61_714: # %cond.load769
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 194
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 193
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 193
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: bnez a1, .LBB61_715
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: bnez a2, .LBB61_715
; CHECK-RV64-NEXT: j .LBB61_201
; CHECK-RV64-NEXT: .LBB61_715: # %cond.load773
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 195
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 194
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 194
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: bnez a1, .LBB61_716
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: bnez a2, .LBB61_716
; CHECK-RV64-NEXT: j .LBB61_202
; CHECK-RV64-NEXT: .LBB61_716: # %cond.load777
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 196
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 195
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 195
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: bnez a1, .LBB61_717
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: bnez a2, .LBB61_717
; CHECK-RV64-NEXT: j .LBB61_203
; CHECK-RV64-NEXT: .LBB61_717: # %cond.load781
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 197
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 196
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 196
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: bnez a1, .LBB61_718
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: bnez a2, .LBB61_718
; CHECK-RV64-NEXT: j .LBB61_204
; CHECK-RV64-NEXT: .LBB61_718: # %cond.load785
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 198
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 197
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 197
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: bnez a1, .LBB61_719
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: bnez a2, .LBB61_719
; CHECK-RV64-NEXT: j .LBB61_205
; CHECK-RV64-NEXT: .LBB61_719: # %cond.load789
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 199
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 198
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 198
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: bnez a1, .LBB61_720
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: bnez a2, .LBB61_720
; CHECK-RV64-NEXT: j .LBB61_206
; CHECK-RV64-NEXT: .LBB61_720: # %cond.load793
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 200
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 199
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 199
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: bnez a1, .LBB61_721
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: bnez a2, .LBB61_721
; CHECK-RV64-NEXT: j .LBB61_207
; CHECK-RV64-NEXT: .LBB61_721: # %cond.load797
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 201
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 200
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 200
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: bnez a1, .LBB61_722
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: bnez a2, .LBB61_722
; CHECK-RV64-NEXT: j .LBB61_208
; CHECK-RV64-NEXT: .LBB61_722: # %cond.load801
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 202
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 201
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 201
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: bnez a1, .LBB61_723
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: bnez a2, .LBB61_723
; CHECK-RV64-NEXT: j .LBB61_209
; CHECK-RV64-NEXT: .LBB61_723: # %cond.load805
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 203
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 202
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 202
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bltz a1, .LBB61_724
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bltz a2, .LBB61_724
; CHECK-RV64-NEXT: j .LBB61_210
; CHECK-RV64-NEXT: .LBB61_724: # %cond.load809
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 204
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 203
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 203
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bltz a1, .LBB61_725
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bltz a2, .LBB61_725
; CHECK-RV64-NEXT: j .LBB61_211
; CHECK-RV64-NEXT: .LBB61_725: # %cond.load813
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 205
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 204
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 204
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bltz a1, .LBB61_726
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bltz a2, .LBB61_726
; CHECK-RV64-NEXT: j .LBB61_212
; CHECK-RV64-NEXT: .LBB61_726: # %cond.load817
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 206
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 205
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 205
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bltz a1, .LBB61_727
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bltz a2, .LBB61_727
; CHECK-RV64-NEXT: j .LBB61_213
; CHECK-RV64-NEXT: .LBB61_727: # %cond.load821
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 207
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 206
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 206
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bltz a1, .LBB61_728
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bltz a2, .LBB61_728
; CHECK-RV64-NEXT: j .LBB61_214
; CHECK-RV64-NEXT: .LBB61_728: # %cond.load825
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 208
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 207
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 207
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bltz a1, .LBB61_729
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bltz a2, .LBB61_729
; CHECK-RV64-NEXT: j .LBB61_215
; CHECK-RV64-NEXT: .LBB61_729: # %cond.load829
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 209
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 208
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 208
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bltz a1, .LBB61_730
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bltz a2, .LBB61_730
; CHECK-RV64-NEXT: j .LBB61_216
; CHECK-RV64-NEXT: .LBB61_730: # %cond.load833
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 210
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 209
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 209
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bltz a1, .LBB61_731
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bltz a2, .LBB61_731
; CHECK-RV64-NEXT: j .LBB61_217
; CHECK-RV64-NEXT: .LBB61_731: # %cond.load837
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 211
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 210
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 210
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bltz a1, .LBB61_732
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bltz a2, .LBB61_732
; CHECK-RV64-NEXT: j .LBB61_218
; CHECK-RV64-NEXT: .LBB61_732: # %cond.load841
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 212
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 211
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 211
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bltz a1, .LBB61_733
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bltz a2, .LBB61_733
; CHECK-RV64-NEXT: j .LBB61_219
; CHECK-RV64-NEXT: .LBB61_733: # %cond.load845
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 213
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 212
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 212
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bltz a1, .LBB61_734
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bltz a2, .LBB61_734
; CHECK-RV64-NEXT: j .LBB61_220
; CHECK-RV64-NEXT: .LBB61_734: # %cond.load849
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 214
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 213
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 213
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bltz a1, .LBB61_735
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bltz a2, .LBB61_735
; CHECK-RV64-NEXT: j .LBB61_221
; CHECK-RV64-NEXT: .LBB61_735: # %cond.load853
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 215
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 214
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 214
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bltz a1, .LBB61_736
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bltz a2, .LBB61_736
; CHECK-RV64-NEXT: j .LBB61_222
; CHECK-RV64-NEXT: .LBB61_736: # %cond.load857
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 216
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 215
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 215
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bltz a1, .LBB61_737
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bltz a2, .LBB61_737
; CHECK-RV64-NEXT: j .LBB61_223
; CHECK-RV64-NEXT: .LBB61_737: # %cond.load861
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 217
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 216
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 216
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bltz a1, .LBB61_738
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bltz a2, .LBB61_738
; CHECK-RV64-NEXT: j .LBB61_224
; CHECK-RV64-NEXT: .LBB61_738: # %cond.load865
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 218
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 217
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 217
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bltz a1, .LBB61_739
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bltz a2, .LBB61_739
; CHECK-RV64-NEXT: j .LBB61_225
; CHECK-RV64-NEXT: .LBB61_739: # %cond.load869
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 219
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 218
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 218
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bltz a1, .LBB61_740
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bltz a2, .LBB61_740
; CHECK-RV64-NEXT: j .LBB61_226
; CHECK-RV64-NEXT: .LBB61_740: # %cond.load873
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 220
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 219
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 219
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bltz a1, .LBB61_741
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bltz a2, .LBB61_741
; CHECK-RV64-NEXT: j .LBB61_227
; CHECK-RV64-NEXT: .LBB61_741: # %cond.load877
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 221
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 220
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 220
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bltz a1, .LBB61_742
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bltz a2, .LBB61_742
; CHECK-RV64-NEXT: j .LBB61_228
; CHECK-RV64-NEXT: .LBB61_742: # %cond.load881
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 222
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 221
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 221
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bltz a1, .LBB61_743
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bltz a2, .LBB61_743
; CHECK-RV64-NEXT: j .LBB61_229
; CHECK-RV64-NEXT: .LBB61_743: # %cond.load885
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 223
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 222
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 222
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bltz a1, .LBB61_744
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bltz a2, .LBB61_744
; CHECK-RV64-NEXT: j .LBB61_230
; CHECK-RV64-NEXT: .LBB61_744: # %cond.load889
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 224
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 223
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 223
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bltz a1, .LBB61_745
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bltz a2, .LBB61_745
; CHECK-RV64-NEXT: j .LBB61_231
; CHECK-RV64-NEXT: .LBB61_745: # %cond.load893
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 225
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 224
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 224
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bltz a1, .LBB61_746
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bltz a2, .LBB61_746
; CHECK-RV64-NEXT: j .LBB61_232
; CHECK-RV64-NEXT: .LBB61_746: # %cond.load897
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 226
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 225
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 225
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bltz a1, .LBB61_747
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bltz a2, .LBB61_747
; CHECK-RV64-NEXT: j .LBB61_233
; CHECK-RV64-NEXT: .LBB61_747: # %cond.load901
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 227
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 226
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 226
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bltz a1, .LBB61_748
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bltz a2, .LBB61_748
; CHECK-RV64-NEXT: j .LBB61_234
; CHECK-RV64-NEXT: .LBB61_748: # %cond.load905
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 228
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 227
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 227
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bltz a1, .LBB61_749
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bltz a2, .LBB61_749
; CHECK-RV64-NEXT: j .LBB61_235
; CHECK-RV64-NEXT: .LBB61_749: # %cond.load909
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 229
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 228
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 228
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bltz a1, .LBB61_750
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bltz a2, .LBB61_750
; CHECK-RV64-NEXT: j .LBB61_236
; CHECK-RV64-NEXT: .LBB61_750: # %cond.load913
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 230
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 229
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 229
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bltz a1, .LBB61_751
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bltz a2, .LBB61_751
; CHECK-RV64-NEXT: j .LBB61_237
; CHECK-RV64-NEXT: .LBB61_751: # %cond.load917
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 231
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 230
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 230
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bltz a1, .LBB61_752
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bltz a2, .LBB61_752
; CHECK-RV64-NEXT: j .LBB61_238
; CHECK-RV64-NEXT: .LBB61_752: # %cond.load921
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 232
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 231
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 231
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bltz a1, .LBB61_753
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bltz a2, .LBB61_753
; CHECK-RV64-NEXT: j .LBB61_239
; CHECK-RV64-NEXT: .LBB61_753: # %cond.load925
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 233
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 232
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 232
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bltz a1, .LBB61_754
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bltz a2, .LBB61_754
; CHECK-RV64-NEXT: j .LBB61_240
; CHECK-RV64-NEXT: .LBB61_754: # %cond.load929
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 234
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 233
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 233
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bltz a1, .LBB61_755
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bltz a2, .LBB61_755
; CHECK-RV64-NEXT: j .LBB61_241
; CHECK-RV64-NEXT: .LBB61_755: # %cond.load933
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 235
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 234
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 234
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bltz a1, .LBB61_756
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bltz a2, .LBB61_756
; CHECK-RV64-NEXT: j .LBB61_242
; CHECK-RV64-NEXT: .LBB61_756: # %cond.load937
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 236
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 235
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 235
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bltz a1, .LBB61_757
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bltz a2, .LBB61_757
; CHECK-RV64-NEXT: j .LBB61_243
; CHECK-RV64-NEXT: .LBB61_757: # %cond.load941
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 237
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 236
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 236
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bltz a1, .LBB61_758
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bltz a2, .LBB61_758
; CHECK-RV64-NEXT: j .LBB61_244
; CHECK-RV64-NEXT: .LBB61_758: # %cond.load945
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 238
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 237
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 237
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bltz a1, .LBB61_759
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bltz a2, .LBB61_759
; CHECK-RV64-NEXT: j .LBB61_245
; CHECK-RV64-NEXT: .LBB61_759: # %cond.load949
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 239
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 238
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 238
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bltz a1, .LBB61_760
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bltz a2, .LBB61_760
; CHECK-RV64-NEXT: j .LBB61_246
; CHECK-RV64-NEXT: .LBB61_760: # %cond.load953
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 240
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 239
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 239
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bltz a1, .LBB61_761
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bltz a2, .LBB61_761
; CHECK-RV64-NEXT: j .LBB61_247
; CHECK-RV64-NEXT: .LBB61_761: # %cond.load957
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 241
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 240
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 240
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bltz a1, .LBB61_762
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bltz a2, .LBB61_762
; CHECK-RV64-NEXT: j .LBB61_248
; CHECK-RV64-NEXT: .LBB61_762: # %cond.load961
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 242
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 241
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 241
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bltz a1, .LBB61_763
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bltz a2, .LBB61_763
; CHECK-RV64-NEXT: j .LBB61_249
; CHECK-RV64-NEXT: .LBB61_763: # %cond.load965
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 243
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 242
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 242
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bltz a1, .LBB61_764
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bltz a2, .LBB61_764
; CHECK-RV64-NEXT: j .LBB61_250
; CHECK-RV64-NEXT: .LBB61_764: # %cond.load969
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 244
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 243
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 243
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bltz a1, .LBB61_765
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bltz a2, .LBB61_765
; CHECK-RV64-NEXT: j .LBB61_251
; CHECK-RV64-NEXT: .LBB61_765: # %cond.load973
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 245
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 244
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 244
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bltz a1, .LBB61_766
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bltz a2, .LBB61_766
; CHECK-RV64-NEXT: j .LBB61_252
; CHECK-RV64-NEXT: .LBB61_766: # %cond.load977
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 246
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 245
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 245
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bltz a1, .LBB61_767
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bltz a2, .LBB61_767
; CHECK-RV64-NEXT: j .LBB61_253
; CHECK-RV64-NEXT: .LBB61_767: # %cond.load981
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 247
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 246
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 246
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bltz a1, .LBB61_768
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bltz a2, .LBB61_768
; CHECK-RV64-NEXT: j .LBB61_254
; CHECK-RV64-NEXT: .LBB61_768: # %cond.load985
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 248
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 247
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 247
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bltz a1, .LBB61_769
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bltz a2, .LBB61_769
; CHECK-RV64-NEXT: j .LBB61_255
; CHECK-RV64-NEXT: .LBB61_769: # %cond.load989
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 249
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 248
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 248
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bltz a1, .LBB61_770
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bltz a2, .LBB61_770
; CHECK-RV64-NEXT: j .LBB61_256
; CHECK-RV64-NEXT: .LBB61_770: # %cond.load993
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 250
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 249
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 249
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bltz a1, .LBB61_771
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bltz a2, .LBB61_771
; CHECK-RV64-NEXT: j .LBB61_257
; CHECK-RV64-NEXT: .LBB61_771: # %cond.load997
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 251
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 250
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 250
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bltz a1, .LBB61_772
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bltz a2, .LBB61_772
; CHECK-RV64-NEXT: j .LBB61_258
; CHECK-RV64-NEXT: .LBB61_772: # %cond.load1001
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 252
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 251
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 251
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bltz a1, .LBB61_773
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bltz a2, .LBB61_773
; CHECK-RV64-NEXT: j .LBB61_259
; CHECK-RV64-NEXT: .LBB61_773: # %cond.load1005
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 253
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
-; CHECK-RV64-NEXT: li a1, 252
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: li a2, 252
+; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_1028
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_1028
; CHECK-RV64-NEXT: j .LBB61_260
; CHECK-RV64-NEXT: .LBB61_1028: # %cond.load1005
; CHECK-RV64-NEXT: j .LBB61_261
; CHECK-RV64-NEXT: .LBB61_774: # %cond.load1017
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
-; CHECK-RV64-NEXT: li a2, 256
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: li a1, 256
; CHECK-RV64-NEXT: li a3, 255
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v20, a3
; CHECK-RV64-NEXT: vmv4r.v v8, v16
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: bnez a2, .LBB61_775
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: bnez a1, .LBB61_775
; CHECK-RV64-NEXT: j .LBB61_265
; CHECK-RV64-NEXT: .LBB61_775: # %cond.load1021
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 257
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 256
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 256
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: bnez a2, .LBB61_776
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: bnez a1, .LBB61_776
; CHECK-RV64-NEXT: j .LBB61_266
; CHECK-RV64-NEXT: .LBB61_776: # %cond.load1025
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 258
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 257
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 257
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: bnez a2, .LBB61_777
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: bnez a1, .LBB61_777
; CHECK-RV64-NEXT: j .LBB61_267
; CHECK-RV64-NEXT: .LBB61_777: # %cond.load1029
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 259
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 258
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 258
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: bnez a2, .LBB61_778
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: bnez a1, .LBB61_778
; CHECK-RV64-NEXT: j .LBB61_268
; CHECK-RV64-NEXT: .LBB61_778: # %cond.load1033
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 260
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 259
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 259
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: bnez a2, .LBB61_779
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: bnez a1, .LBB61_779
; CHECK-RV64-NEXT: j .LBB61_269
; CHECK-RV64-NEXT: .LBB61_779: # %cond.load1037
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 261
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 260
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 260
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: bnez a2, .LBB61_780
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: bnez a1, .LBB61_780
; CHECK-RV64-NEXT: j .LBB61_270
; CHECK-RV64-NEXT: .LBB61_780: # %cond.load1041
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 262
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 261
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 261
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: bnez a2, .LBB61_781
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: bnez a1, .LBB61_781
; CHECK-RV64-NEXT: j .LBB61_271
; CHECK-RV64-NEXT: .LBB61_781: # %cond.load1045
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 263
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 262
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 262
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: bnez a2, .LBB61_782
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: bnez a1, .LBB61_782
; CHECK-RV64-NEXT: j .LBB61_272
; CHECK-RV64-NEXT: .LBB61_782: # %cond.load1049
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 264
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 263
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 263
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: bnez a2, .LBB61_783
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: bnez a1, .LBB61_783
; CHECK-RV64-NEXT: j .LBB61_273
; CHECK-RV64-NEXT: .LBB61_783: # %cond.load1053
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 265
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 264
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 264
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: bnez a2, .LBB61_784
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: bnez a1, .LBB61_784
; CHECK-RV64-NEXT: j .LBB61_274
; CHECK-RV64-NEXT: .LBB61_784: # %cond.load1057
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 266
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 265
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 265
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: bnez a2, .LBB61_785
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: bnez a1, .LBB61_785
; CHECK-RV64-NEXT: j .LBB61_275
; CHECK-RV64-NEXT: .LBB61_785: # %cond.load1061
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 267
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 266
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 266
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bltz a2, .LBB61_786
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bltz a1, .LBB61_786
; CHECK-RV64-NEXT: j .LBB61_276
; CHECK-RV64-NEXT: .LBB61_786: # %cond.load1065
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 268
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 267
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 267
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bltz a2, .LBB61_787
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bltz a1, .LBB61_787
; CHECK-RV64-NEXT: j .LBB61_277
; CHECK-RV64-NEXT: .LBB61_787: # %cond.load1069
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 269
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 268
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 268
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bltz a2, .LBB61_788
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bltz a1, .LBB61_788
; CHECK-RV64-NEXT: j .LBB61_278
; CHECK-RV64-NEXT: .LBB61_788: # %cond.load1073
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 270
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 269
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 269
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bltz a2, .LBB61_789
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bltz a1, .LBB61_789
; CHECK-RV64-NEXT: j .LBB61_279
; CHECK-RV64-NEXT: .LBB61_789: # %cond.load1077
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 271
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 270
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 270
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bltz a2, .LBB61_790
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bltz a1, .LBB61_790
; CHECK-RV64-NEXT: j .LBB61_280
; CHECK-RV64-NEXT: .LBB61_790: # %cond.load1081
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 272
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 271
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 271
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bltz a2, .LBB61_791
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bltz a1, .LBB61_791
; CHECK-RV64-NEXT: j .LBB61_281
; CHECK-RV64-NEXT: .LBB61_791: # %cond.load1085
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 273
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 272
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 272
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bltz a2, .LBB61_792
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bltz a1, .LBB61_792
; CHECK-RV64-NEXT: j .LBB61_282
; CHECK-RV64-NEXT: .LBB61_792: # %cond.load1089
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 274
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 273
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 273
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bltz a2, .LBB61_793
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bltz a1, .LBB61_793
; CHECK-RV64-NEXT: j .LBB61_283
; CHECK-RV64-NEXT: .LBB61_793: # %cond.load1093
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 275
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 274
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 274
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bltz a2, .LBB61_794
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bltz a1, .LBB61_794
; CHECK-RV64-NEXT: j .LBB61_284
; CHECK-RV64-NEXT: .LBB61_794: # %cond.load1097
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 276
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 275
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 275
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bltz a2, .LBB61_795
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bltz a1, .LBB61_795
; CHECK-RV64-NEXT: j .LBB61_285
; CHECK-RV64-NEXT: .LBB61_795: # %cond.load1101
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 277
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 276
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 276
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bltz a2, .LBB61_796
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bltz a1, .LBB61_796
; CHECK-RV64-NEXT: j .LBB61_286
; CHECK-RV64-NEXT: .LBB61_796: # %cond.load1105
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 278
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 277
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 277
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bltz a2, .LBB61_797
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bltz a1, .LBB61_797
; CHECK-RV64-NEXT: j .LBB61_287
; CHECK-RV64-NEXT: .LBB61_797: # %cond.load1109
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 279
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 278
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 278
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bltz a2, .LBB61_798
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bltz a1, .LBB61_798
; CHECK-RV64-NEXT: j .LBB61_288
; CHECK-RV64-NEXT: .LBB61_798: # %cond.load1113
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 280
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 279
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 279
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bltz a2, .LBB61_799
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bltz a1, .LBB61_799
; CHECK-RV64-NEXT: j .LBB61_289
; CHECK-RV64-NEXT: .LBB61_799: # %cond.load1117
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 281
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 280
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 280
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bltz a2, .LBB61_800
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bltz a1, .LBB61_800
; CHECK-RV64-NEXT: j .LBB61_290
; CHECK-RV64-NEXT: .LBB61_800: # %cond.load1121
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 282
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 281
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 281
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bltz a2, .LBB61_801
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bltz a1, .LBB61_801
; CHECK-RV64-NEXT: j .LBB61_291
; CHECK-RV64-NEXT: .LBB61_801: # %cond.load1125
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 283
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 282
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 282
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bltz a2, .LBB61_802
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bltz a1, .LBB61_802
; CHECK-RV64-NEXT: j .LBB61_292
; CHECK-RV64-NEXT: .LBB61_802: # %cond.load1129
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 284
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 283
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 283
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bltz a2, .LBB61_803
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bltz a1, .LBB61_803
; CHECK-RV64-NEXT: j .LBB61_293
; CHECK-RV64-NEXT: .LBB61_803: # %cond.load1133
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 285
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 284
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 284
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bltz a2, .LBB61_804
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bltz a1, .LBB61_804
; CHECK-RV64-NEXT: j .LBB61_294
; CHECK-RV64-NEXT: .LBB61_804: # %cond.load1137
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 286
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 285
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 285
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bltz a2, .LBB61_805
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bltz a1, .LBB61_805
; CHECK-RV64-NEXT: j .LBB61_295
; CHECK-RV64-NEXT: .LBB61_805: # %cond.load1141
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 287
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 286
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 286
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bltz a2, .LBB61_806
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bltz a1, .LBB61_806
; CHECK-RV64-NEXT: j .LBB61_296
; CHECK-RV64-NEXT: .LBB61_806: # %cond.load1145
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 288
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 287
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 287
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bltz a2, .LBB61_807
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bltz a1, .LBB61_807
; CHECK-RV64-NEXT: j .LBB61_297
; CHECK-RV64-NEXT: .LBB61_807: # %cond.load1149
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 289
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 288
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 288
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bltz a2, .LBB61_808
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bltz a1, .LBB61_808
; CHECK-RV64-NEXT: j .LBB61_298
; CHECK-RV64-NEXT: .LBB61_808: # %cond.load1153
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 290
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 289
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 289
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bltz a2, .LBB61_809
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bltz a1, .LBB61_809
; CHECK-RV64-NEXT: j .LBB61_299
; CHECK-RV64-NEXT: .LBB61_809: # %cond.load1157
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 291
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 290
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 290
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bltz a2, .LBB61_810
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bltz a1, .LBB61_810
; CHECK-RV64-NEXT: j .LBB61_300
; CHECK-RV64-NEXT: .LBB61_810: # %cond.load1161
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 292
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 291
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 291
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bltz a2, .LBB61_811
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bltz a1, .LBB61_811
; CHECK-RV64-NEXT: j .LBB61_301
; CHECK-RV64-NEXT: .LBB61_811: # %cond.load1165
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 293
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 292
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 292
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bltz a2, .LBB61_812
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bltz a1, .LBB61_812
; CHECK-RV64-NEXT: j .LBB61_302
; CHECK-RV64-NEXT: .LBB61_812: # %cond.load1169
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 294
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 293
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 293
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bltz a2, .LBB61_813
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bltz a1, .LBB61_813
; CHECK-RV64-NEXT: j .LBB61_303
; CHECK-RV64-NEXT: .LBB61_813: # %cond.load1173
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 295
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 294
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 294
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bltz a2, .LBB61_814
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bltz a1, .LBB61_814
; CHECK-RV64-NEXT: j .LBB61_304
; CHECK-RV64-NEXT: .LBB61_814: # %cond.load1177
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 296
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 295
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 295
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bltz a2, .LBB61_815
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bltz a1, .LBB61_815
; CHECK-RV64-NEXT: j .LBB61_305
; CHECK-RV64-NEXT: .LBB61_815: # %cond.load1181
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 297
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 296
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 296
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bltz a2, .LBB61_816
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bltz a1, .LBB61_816
; CHECK-RV64-NEXT: j .LBB61_306
; CHECK-RV64-NEXT: .LBB61_816: # %cond.load1185
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 298
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 297
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 297
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bltz a2, .LBB61_817
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bltz a1, .LBB61_817
; CHECK-RV64-NEXT: j .LBB61_307
; CHECK-RV64-NEXT: .LBB61_817: # %cond.load1189
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 299
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 298
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 298
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bltz a2, .LBB61_818
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bltz a1, .LBB61_818
; CHECK-RV64-NEXT: j .LBB61_308
; CHECK-RV64-NEXT: .LBB61_818: # %cond.load1193
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 300
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 299
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 299
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bltz a2, .LBB61_819
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bltz a1, .LBB61_819
; CHECK-RV64-NEXT: j .LBB61_309
; CHECK-RV64-NEXT: .LBB61_819: # %cond.load1197
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 301
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 300
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 300
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bltz a2, .LBB61_820
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bltz a1, .LBB61_820
; CHECK-RV64-NEXT: j .LBB61_310
; CHECK-RV64-NEXT: .LBB61_820: # %cond.load1201
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 302
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 301
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 301
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bltz a2, .LBB61_821
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bltz a1, .LBB61_821
; CHECK-RV64-NEXT: j .LBB61_311
; CHECK-RV64-NEXT: .LBB61_821: # %cond.load1205
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 303
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 302
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 302
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bltz a2, .LBB61_822
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bltz a1, .LBB61_822
; CHECK-RV64-NEXT: j .LBB61_312
; CHECK-RV64-NEXT: .LBB61_822: # %cond.load1209
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 304
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 303
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 303
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bltz a2, .LBB61_823
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bltz a1, .LBB61_823
; CHECK-RV64-NEXT: j .LBB61_313
; CHECK-RV64-NEXT: .LBB61_823: # %cond.load1213
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 305
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 304
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 304
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bltz a2, .LBB61_824
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bltz a1, .LBB61_824
; CHECK-RV64-NEXT: j .LBB61_314
; CHECK-RV64-NEXT: .LBB61_824: # %cond.load1217
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 306
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 305
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 305
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bltz a2, .LBB61_825
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bltz a1, .LBB61_825
; CHECK-RV64-NEXT: j .LBB61_315
; CHECK-RV64-NEXT: .LBB61_825: # %cond.load1221
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 307
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 306
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 306
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bltz a2, .LBB61_826
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bltz a1, .LBB61_826
; CHECK-RV64-NEXT: j .LBB61_316
; CHECK-RV64-NEXT: .LBB61_826: # %cond.load1225
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 308
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 307
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 307
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bltz a2, .LBB61_827
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bltz a1, .LBB61_827
; CHECK-RV64-NEXT: j .LBB61_317
; CHECK-RV64-NEXT: .LBB61_827: # %cond.load1229
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 309
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 308
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 308
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bltz a2, .LBB61_828
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bltz a1, .LBB61_828
; CHECK-RV64-NEXT: j .LBB61_318
; CHECK-RV64-NEXT: .LBB61_828: # %cond.load1233
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 310
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 309
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 309
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bltz a2, .LBB61_829
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bltz a1, .LBB61_829
; CHECK-RV64-NEXT: j .LBB61_319
; CHECK-RV64-NEXT: .LBB61_829: # %cond.load1237
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 311
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 310
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 310
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bltz a2, .LBB61_830
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bltz a1, .LBB61_830
; CHECK-RV64-NEXT: j .LBB61_320
; CHECK-RV64-NEXT: .LBB61_830: # %cond.load1241
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 312
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 311
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 311
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bltz a2, .LBB61_831
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bltz a1, .LBB61_831
; CHECK-RV64-NEXT: j .LBB61_321
; CHECK-RV64-NEXT: .LBB61_831: # %cond.load1245
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 313
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 312
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 312
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bltz a2, .LBB61_832
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bltz a1, .LBB61_832
; CHECK-RV64-NEXT: j .LBB61_322
; CHECK-RV64-NEXT: .LBB61_832: # %cond.load1249
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 314
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 313
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 313
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bltz a2, .LBB61_833
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bltz a1, .LBB61_833
; CHECK-RV64-NEXT: j .LBB61_323
; CHECK-RV64-NEXT: .LBB61_833: # %cond.load1253
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 315
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 314
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 314
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bltz a2, .LBB61_834
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bltz a1, .LBB61_834
; CHECK-RV64-NEXT: j .LBB61_324
; CHECK-RV64-NEXT: .LBB61_834: # %cond.load1257
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 316
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 315
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 315
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bltz a2, .LBB61_835
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bltz a1, .LBB61_835
; CHECK-RV64-NEXT: j .LBB61_325
; CHECK-RV64-NEXT: .LBB61_835: # %cond.load1261
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 317
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 316
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 316
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_1029
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_1029
; CHECK-RV64-NEXT: j .LBB61_326
; CHECK-RV64-NEXT: .LBB61_1029: # %cond.load1261
; CHECK-RV64-NEXT: j .LBB61_327
; CHECK-RV64-NEXT: .LBB61_836: # %cond.load1273
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 320
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 320
; CHECK-RV64-NEXT: li a3, 319
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: bnez a1, .LBB61_837
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: bnez a2, .LBB61_837
; CHECK-RV64-NEXT: j .LBB61_331
; CHECK-RV64-NEXT: .LBB61_837: # %cond.load1277
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 321
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 320
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 320
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: bnez a1, .LBB61_838
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: bnez a2, .LBB61_838
; CHECK-RV64-NEXT: j .LBB61_332
; CHECK-RV64-NEXT: .LBB61_838: # %cond.load1281
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 322
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 321
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 321
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: bnez a1, .LBB61_839
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: bnez a2, .LBB61_839
; CHECK-RV64-NEXT: j .LBB61_333
; CHECK-RV64-NEXT: .LBB61_839: # %cond.load1285
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 323
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 322
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 322
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: bnez a1, .LBB61_840
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: bnez a2, .LBB61_840
; CHECK-RV64-NEXT: j .LBB61_334
; CHECK-RV64-NEXT: .LBB61_840: # %cond.load1289
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 324
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 323
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 323
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: bnez a1, .LBB61_841
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: bnez a2, .LBB61_841
; CHECK-RV64-NEXT: j .LBB61_335
; CHECK-RV64-NEXT: .LBB61_841: # %cond.load1293
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 325
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 324
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 324
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: bnez a1, .LBB61_842
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: bnez a2, .LBB61_842
; CHECK-RV64-NEXT: j .LBB61_336
; CHECK-RV64-NEXT: .LBB61_842: # %cond.load1297
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 326
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 325
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 325
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: bnez a1, .LBB61_843
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: bnez a2, .LBB61_843
; CHECK-RV64-NEXT: j .LBB61_337
; CHECK-RV64-NEXT: .LBB61_843: # %cond.load1301
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 327
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 326
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 326
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: bnez a1, .LBB61_844
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: bnez a2, .LBB61_844
; CHECK-RV64-NEXT: j .LBB61_338
; CHECK-RV64-NEXT: .LBB61_844: # %cond.load1305
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 328
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 327
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 327
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: bnez a1, .LBB61_845
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: bnez a2, .LBB61_845
; CHECK-RV64-NEXT: j .LBB61_339
; CHECK-RV64-NEXT: .LBB61_845: # %cond.load1309
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 329
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 328
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 328
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: bnez a1, .LBB61_846
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: bnez a2, .LBB61_846
; CHECK-RV64-NEXT: j .LBB61_340
; CHECK-RV64-NEXT: .LBB61_846: # %cond.load1313
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 330
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 329
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 329
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: bnez a1, .LBB61_847
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: bnez a2, .LBB61_847
; CHECK-RV64-NEXT: j .LBB61_341
; CHECK-RV64-NEXT: .LBB61_847: # %cond.load1317
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 331
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 330
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 330
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bltz a1, .LBB61_848
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bltz a2, .LBB61_848
; CHECK-RV64-NEXT: j .LBB61_342
; CHECK-RV64-NEXT: .LBB61_848: # %cond.load1321
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 332
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 331
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 331
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bltz a1, .LBB61_849
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bltz a2, .LBB61_849
; CHECK-RV64-NEXT: j .LBB61_343
; CHECK-RV64-NEXT: .LBB61_849: # %cond.load1325
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 333
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 332
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 332
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bltz a1, .LBB61_850
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bltz a2, .LBB61_850
; CHECK-RV64-NEXT: j .LBB61_344
; CHECK-RV64-NEXT: .LBB61_850: # %cond.load1329
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 334
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 333
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 333
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bltz a1, .LBB61_851
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bltz a2, .LBB61_851
; CHECK-RV64-NEXT: j .LBB61_345
; CHECK-RV64-NEXT: .LBB61_851: # %cond.load1333
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 335
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 334
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 334
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bltz a1, .LBB61_852
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bltz a2, .LBB61_852
; CHECK-RV64-NEXT: j .LBB61_346
; CHECK-RV64-NEXT: .LBB61_852: # %cond.load1337
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 336
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 335
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 335
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bltz a1, .LBB61_853
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bltz a2, .LBB61_853
; CHECK-RV64-NEXT: j .LBB61_347
; CHECK-RV64-NEXT: .LBB61_853: # %cond.load1341
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 337
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 336
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 336
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bltz a1, .LBB61_854
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bltz a2, .LBB61_854
; CHECK-RV64-NEXT: j .LBB61_348
; CHECK-RV64-NEXT: .LBB61_854: # %cond.load1345
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 338
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 337
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 337
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bltz a1, .LBB61_855
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bltz a2, .LBB61_855
; CHECK-RV64-NEXT: j .LBB61_349
; CHECK-RV64-NEXT: .LBB61_855: # %cond.load1349
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 339
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 338
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 338
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bltz a1, .LBB61_856
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bltz a2, .LBB61_856
; CHECK-RV64-NEXT: j .LBB61_350
; CHECK-RV64-NEXT: .LBB61_856: # %cond.load1353
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 340
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 339
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 339
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bltz a1, .LBB61_857
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bltz a2, .LBB61_857
; CHECK-RV64-NEXT: j .LBB61_351
; CHECK-RV64-NEXT: .LBB61_857: # %cond.load1357
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 341
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 340
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 340
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bltz a1, .LBB61_858
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bltz a2, .LBB61_858
; CHECK-RV64-NEXT: j .LBB61_352
; CHECK-RV64-NEXT: .LBB61_858: # %cond.load1361
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 342
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 341
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 341
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bltz a1, .LBB61_859
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bltz a2, .LBB61_859
; CHECK-RV64-NEXT: j .LBB61_353
; CHECK-RV64-NEXT: .LBB61_859: # %cond.load1365
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 343
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 342
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 342
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bltz a1, .LBB61_860
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bltz a2, .LBB61_860
; CHECK-RV64-NEXT: j .LBB61_354
; CHECK-RV64-NEXT: .LBB61_860: # %cond.load1369
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 344
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 343
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 343
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bltz a1, .LBB61_861
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bltz a2, .LBB61_861
; CHECK-RV64-NEXT: j .LBB61_355
; CHECK-RV64-NEXT: .LBB61_861: # %cond.load1373
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 345
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 344
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 344
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bltz a1, .LBB61_862
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bltz a2, .LBB61_862
; CHECK-RV64-NEXT: j .LBB61_356
; CHECK-RV64-NEXT: .LBB61_862: # %cond.load1377
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 346
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 345
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 345
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bltz a1, .LBB61_863
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bltz a2, .LBB61_863
; CHECK-RV64-NEXT: j .LBB61_357
; CHECK-RV64-NEXT: .LBB61_863: # %cond.load1381
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 347
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 346
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 346
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bltz a1, .LBB61_864
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bltz a2, .LBB61_864
; CHECK-RV64-NEXT: j .LBB61_358
; CHECK-RV64-NEXT: .LBB61_864: # %cond.load1385
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 348
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 347
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 347
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bltz a1, .LBB61_865
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bltz a2, .LBB61_865
; CHECK-RV64-NEXT: j .LBB61_359
; CHECK-RV64-NEXT: .LBB61_865: # %cond.load1389
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 349
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 348
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 348
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bltz a1, .LBB61_866
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bltz a2, .LBB61_866
; CHECK-RV64-NEXT: j .LBB61_360
; CHECK-RV64-NEXT: .LBB61_866: # %cond.load1393
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 350
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 349
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 349
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bltz a1, .LBB61_867
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bltz a2, .LBB61_867
; CHECK-RV64-NEXT: j .LBB61_361
; CHECK-RV64-NEXT: .LBB61_867: # %cond.load1397
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 351
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 350
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 350
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bltz a1, .LBB61_868
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bltz a2, .LBB61_868
; CHECK-RV64-NEXT: j .LBB61_362
; CHECK-RV64-NEXT: .LBB61_868: # %cond.load1401
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 352
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 351
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 351
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bltz a1, .LBB61_869
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bltz a2, .LBB61_869
; CHECK-RV64-NEXT: j .LBB61_363
; CHECK-RV64-NEXT: .LBB61_869: # %cond.load1405
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 353
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 352
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 352
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bltz a1, .LBB61_870
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bltz a2, .LBB61_870
; CHECK-RV64-NEXT: j .LBB61_364
; CHECK-RV64-NEXT: .LBB61_870: # %cond.load1409
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 354
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 353
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 353
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bltz a1, .LBB61_871
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bltz a2, .LBB61_871
; CHECK-RV64-NEXT: j .LBB61_365
; CHECK-RV64-NEXT: .LBB61_871: # %cond.load1413
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 355
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 354
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 354
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bltz a1, .LBB61_872
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bltz a2, .LBB61_872
; CHECK-RV64-NEXT: j .LBB61_366
; CHECK-RV64-NEXT: .LBB61_872: # %cond.load1417
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 356
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 355
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 355
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bltz a1, .LBB61_873
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bltz a2, .LBB61_873
; CHECK-RV64-NEXT: j .LBB61_367
; CHECK-RV64-NEXT: .LBB61_873: # %cond.load1421
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 357
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 356
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 356
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bltz a1, .LBB61_874
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bltz a2, .LBB61_874
; CHECK-RV64-NEXT: j .LBB61_368
; CHECK-RV64-NEXT: .LBB61_874: # %cond.load1425
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 358
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 357
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 357
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bltz a1, .LBB61_875
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bltz a2, .LBB61_875
; CHECK-RV64-NEXT: j .LBB61_369
; CHECK-RV64-NEXT: .LBB61_875: # %cond.load1429
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 359
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 358
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 358
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bltz a1, .LBB61_876
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bltz a2, .LBB61_876
; CHECK-RV64-NEXT: j .LBB61_370
; CHECK-RV64-NEXT: .LBB61_876: # %cond.load1433
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 360
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 359
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 359
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bltz a1, .LBB61_877
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bltz a2, .LBB61_877
; CHECK-RV64-NEXT: j .LBB61_371
; CHECK-RV64-NEXT: .LBB61_877: # %cond.load1437
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 361
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 360
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 360
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bltz a1, .LBB61_878
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bltz a2, .LBB61_878
; CHECK-RV64-NEXT: j .LBB61_372
; CHECK-RV64-NEXT: .LBB61_878: # %cond.load1441
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 362
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 361
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 361
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bltz a1, .LBB61_879
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bltz a2, .LBB61_879
; CHECK-RV64-NEXT: j .LBB61_373
; CHECK-RV64-NEXT: .LBB61_879: # %cond.load1445
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 363
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 362
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 362
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bltz a1, .LBB61_880
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bltz a2, .LBB61_880
; CHECK-RV64-NEXT: j .LBB61_374
; CHECK-RV64-NEXT: .LBB61_880: # %cond.load1449
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 364
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 363
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 363
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bltz a1, .LBB61_881
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bltz a2, .LBB61_881
; CHECK-RV64-NEXT: j .LBB61_375
; CHECK-RV64-NEXT: .LBB61_881: # %cond.load1453
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 365
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 364
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 364
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bltz a1, .LBB61_882
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bltz a2, .LBB61_882
; CHECK-RV64-NEXT: j .LBB61_376
; CHECK-RV64-NEXT: .LBB61_882: # %cond.load1457
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 366
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 365
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 365
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bltz a1, .LBB61_883
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bltz a2, .LBB61_883
; CHECK-RV64-NEXT: j .LBB61_377
; CHECK-RV64-NEXT: .LBB61_883: # %cond.load1461
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 367
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 366
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 366
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bltz a1, .LBB61_884
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bltz a2, .LBB61_884
; CHECK-RV64-NEXT: j .LBB61_378
; CHECK-RV64-NEXT: .LBB61_884: # %cond.load1465
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 368
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 367
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 367
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bltz a1, .LBB61_885
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bltz a2, .LBB61_885
; CHECK-RV64-NEXT: j .LBB61_379
; CHECK-RV64-NEXT: .LBB61_885: # %cond.load1469
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 369
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 368
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 368
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bltz a1, .LBB61_886
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bltz a2, .LBB61_886
; CHECK-RV64-NEXT: j .LBB61_380
; CHECK-RV64-NEXT: .LBB61_886: # %cond.load1473
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 370
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 369
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 369
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bltz a1, .LBB61_887
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bltz a2, .LBB61_887
; CHECK-RV64-NEXT: j .LBB61_381
; CHECK-RV64-NEXT: .LBB61_887: # %cond.load1477
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 371
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 370
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 370
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bltz a1, .LBB61_888
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bltz a2, .LBB61_888
; CHECK-RV64-NEXT: j .LBB61_382
; CHECK-RV64-NEXT: .LBB61_888: # %cond.load1481
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 372
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 371
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 371
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bltz a1, .LBB61_889
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bltz a2, .LBB61_889
; CHECK-RV64-NEXT: j .LBB61_383
; CHECK-RV64-NEXT: .LBB61_889: # %cond.load1485
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 373
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 372
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 372
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bltz a1, .LBB61_890
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bltz a2, .LBB61_890
; CHECK-RV64-NEXT: j .LBB61_384
; CHECK-RV64-NEXT: .LBB61_890: # %cond.load1489
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 374
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 373
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 373
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bltz a1, .LBB61_891
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bltz a2, .LBB61_891
; CHECK-RV64-NEXT: j .LBB61_385
; CHECK-RV64-NEXT: .LBB61_891: # %cond.load1493
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 375
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 374
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 374
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bltz a1, .LBB61_892
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bltz a2, .LBB61_892
; CHECK-RV64-NEXT: j .LBB61_386
; CHECK-RV64-NEXT: .LBB61_892: # %cond.load1497
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 376
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 375
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 375
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bltz a1, .LBB61_893
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bltz a2, .LBB61_893
; CHECK-RV64-NEXT: j .LBB61_387
; CHECK-RV64-NEXT: .LBB61_893: # %cond.load1501
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 377
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 376
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 376
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bltz a1, .LBB61_894
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bltz a2, .LBB61_894
; CHECK-RV64-NEXT: j .LBB61_388
; CHECK-RV64-NEXT: .LBB61_894: # %cond.load1505
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 378
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 377
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 377
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bltz a1, .LBB61_895
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bltz a2, .LBB61_895
; CHECK-RV64-NEXT: j .LBB61_389
; CHECK-RV64-NEXT: .LBB61_895: # %cond.load1509
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 379
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 378
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 378
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bltz a1, .LBB61_896
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bltz a2, .LBB61_896
; CHECK-RV64-NEXT: j .LBB61_390
; CHECK-RV64-NEXT: .LBB61_896: # %cond.load1513
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 380
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 379
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 379
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bltz a1, .LBB61_897
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bltz a2, .LBB61_897
; CHECK-RV64-NEXT: j .LBB61_391
; CHECK-RV64-NEXT: .LBB61_897: # %cond.load1517
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 381
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 380
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 380
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bgez a1, .LBB61_1030
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bgez a2, .LBB61_1030
; CHECK-RV64-NEXT: j .LBB61_392
; CHECK-RV64-NEXT: .LBB61_1030: # %cond.load1517
; CHECK-RV64-NEXT: j .LBB61_393
; CHECK-RV64-NEXT: .LBB61_898: # %cond.load1529
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 384
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 384
; CHECK-RV64-NEXT: li a3, 383
-; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1
-; CHECK-RV64-NEXT: bnez a2, .LBB61_899
+; CHECK-RV64-NEXT: andi a1, a2, 1
+; CHECK-RV64-NEXT: bnez a1, .LBB61_899
; CHECK-RV64-NEXT: j .LBB61_397
; CHECK-RV64-NEXT: .LBB61_899: # %cond.load1533
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 385
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 384
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 384
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 2
-; CHECK-RV64-NEXT: bnez a2, .LBB61_900
+; CHECK-RV64-NEXT: andi a1, a2, 2
+; CHECK-RV64-NEXT: bnez a1, .LBB61_900
; CHECK-RV64-NEXT: j .LBB61_398
; CHECK-RV64-NEXT: .LBB61_900: # %cond.load1537
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 386
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 385
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 385
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 4
-; CHECK-RV64-NEXT: bnez a2, .LBB61_901
+; CHECK-RV64-NEXT: andi a1, a2, 4
+; CHECK-RV64-NEXT: bnez a1, .LBB61_901
; CHECK-RV64-NEXT: j .LBB61_399
; CHECK-RV64-NEXT: .LBB61_901: # %cond.load1541
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 387
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 386
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 386
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 8
-; CHECK-RV64-NEXT: bnez a2, .LBB61_902
+; CHECK-RV64-NEXT: andi a1, a2, 8
+; CHECK-RV64-NEXT: bnez a1, .LBB61_902
; CHECK-RV64-NEXT: j .LBB61_400
; CHECK-RV64-NEXT: .LBB61_902: # %cond.load1545
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 388
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 387
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 387
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 16
-; CHECK-RV64-NEXT: bnez a2, .LBB61_903
+; CHECK-RV64-NEXT: andi a1, a2, 16
+; CHECK-RV64-NEXT: bnez a1, .LBB61_903
; CHECK-RV64-NEXT: j .LBB61_401
; CHECK-RV64-NEXT: .LBB61_903: # %cond.load1549
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 389
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 388
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 388
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 32
-; CHECK-RV64-NEXT: bnez a2, .LBB61_904
+; CHECK-RV64-NEXT: andi a1, a2, 32
+; CHECK-RV64-NEXT: bnez a1, .LBB61_904
; CHECK-RV64-NEXT: j .LBB61_402
; CHECK-RV64-NEXT: .LBB61_904: # %cond.load1553
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 390
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 389
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 389
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 64
-; CHECK-RV64-NEXT: bnez a2, .LBB61_905
+; CHECK-RV64-NEXT: andi a1, a2, 64
+; CHECK-RV64-NEXT: bnez a1, .LBB61_905
; CHECK-RV64-NEXT: j .LBB61_403
; CHECK-RV64-NEXT: .LBB61_905: # %cond.load1557
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 391
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 390
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 390
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 128
-; CHECK-RV64-NEXT: bnez a2, .LBB61_906
+; CHECK-RV64-NEXT: andi a1, a2, 128
+; CHECK-RV64-NEXT: bnez a1, .LBB61_906
; CHECK-RV64-NEXT: j .LBB61_404
; CHECK-RV64-NEXT: .LBB61_906: # %cond.load1561
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 392
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 391
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 391
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 256
-; CHECK-RV64-NEXT: bnez a2, .LBB61_907
+; CHECK-RV64-NEXT: andi a1, a2, 256
+; CHECK-RV64-NEXT: bnez a1, .LBB61_907
; CHECK-RV64-NEXT: j .LBB61_405
; CHECK-RV64-NEXT: .LBB61_907: # %cond.load1565
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 393
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 392
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 392
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 512
-; CHECK-RV64-NEXT: bnez a2, .LBB61_908
+; CHECK-RV64-NEXT: andi a1, a2, 512
+; CHECK-RV64-NEXT: bnez a1, .LBB61_908
; CHECK-RV64-NEXT: j .LBB61_406
; CHECK-RV64-NEXT: .LBB61_908: # %cond.load1569
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 394
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 393
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 393
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a2, a1, 1024
-; CHECK-RV64-NEXT: bnez a2, .LBB61_909
+; CHECK-RV64-NEXT: andi a1, a2, 1024
+; CHECK-RV64-NEXT: bnez a1, .LBB61_909
; CHECK-RV64-NEXT: j .LBB61_407
; CHECK-RV64-NEXT: .LBB61_909: # %cond.load1573
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 395
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 394
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 394
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 52
-; CHECK-RV64-NEXT: bltz a2, .LBB61_910
+; CHECK-RV64-NEXT: slli a1, a2, 52
+; CHECK-RV64-NEXT: bltz a1, .LBB61_910
; CHECK-RV64-NEXT: j .LBB61_408
; CHECK-RV64-NEXT: .LBB61_910: # %cond.load1577
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 396
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 395
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 395
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 51
-; CHECK-RV64-NEXT: bltz a2, .LBB61_911
+; CHECK-RV64-NEXT: slli a1, a2, 51
+; CHECK-RV64-NEXT: bltz a1, .LBB61_911
; CHECK-RV64-NEXT: j .LBB61_409
; CHECK-RV64-NEXT: .LBB61_911: # %cond.load1581
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 397
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 396
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 396
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 50
-; CHECK-RV64-NEXT: bltz a2, .LBB61_912
+; CHECK-RV64-NEXT: slli a1, a2, 50
+; CHECK-RV64-NEXT: bltz a1, .LBB61_912
; CHECK-RV64-NEXT: j .LBB61_410
; CHECK-RV64-NEXT: .LBB61_912: # %cond.load1585
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 398
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 397
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 397
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 49
-; CHECK-RV64-NEXT: bltz a2, .LBB61_913
+; CHECK-RV64-NEXT: slli a1, a2, 49
+; CHECK-RV64-NEXT: bltz a1, .LBB61_913
; CHECK-RV64-NEXT: j .LBB61_411
; CHECK-RV64-NEXT: .LBB61_913: # %cond.load1589
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 399
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 398
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 398
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 48
-; CHECK-RV64-NEXT: bltz a2, .LBB61_914
+; CHECK-RV64-NEXT: slli a1, a2, 48
+; CHECK-RV64-NEXT: bltz a1, .LBB61_914
; CHECK-RV64-NEXT: j .LBB61_412
; CHECK-RV64-NEXT: .LBB61_914: # %cond.load1593
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 400
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 399
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 399
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 47
-; CHECK-RV64-NEXT: bltz a2, .LBB61_915
+; CHECK-RV64-NEXT: slli a1, a2, 47
+; CHECK-RV64-NEXT: bltz a1, .LBB61_915
; CHECK-RV64-NEXT: j .LBB61_413
; CHECK-RV64-NEXT: .LBB61_915: # %cond.load1597
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 401
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 400
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 400
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 46
-; CHECK-RV64-NEXT: bltz a2, .LBB61_916
+; CHECK-RV64-NEXT: slli a1, a2, 46
+; CHECK-RV64-NEXT: bltz a1, .LBB61_916
; CHECK-RV64-NEXT: j .LBB61_414
; CHECK-RV64-NEXT: .LBB61_916: # %cond.load1601
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 402
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 401
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 401
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 45
-; CHECK-RV64-NEXT: bltz a2, .LBB61_917
+; CHECK-RV64-NEXT: slli a1, a2, 45
+; CHECK-RV64-NEXT: bltz a1, .LBB61_917
; CHECK-RV64-NEXT: j .LBB61_415
; CHECK-RV64-NEXT: .LBB61_917: # %cond.load1605
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 403
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 402
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 402
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 44
-; CHECK-RV64-NEXT: bltz a2, .LBB61_918
+; CHECK-RV64-NEXT: slli a1, a2, 44
+; CHECK-RV64-NEXT: bltz a1, .LBB61_918
; CHECK-RV64-NEXT: j .LBB61_416
; CHECK-RV64-NEXT: .LBB61_918: # %cond.load1609
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 404
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 403
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 403
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 43
-; CHECK-RV64-NEXT: bltz a2, .LBB61_919
+; CHECK-RV64-NEXT: slli a1, a2, 43
+; CHECK-RV64-NEXT: bltz a1, .LBB61_919
; CHECK-RV64-NEXT: j .LBB61_417
; CHECK-RV64-NEXT: .LBB61_919: # %cond.load1613
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 405
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 404
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 404
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 42
-; CHECK-RV64-NEXT: bltz a2, .LBB61_920
+; CHECK-RV64-NEXT: slli a1, a2, 42
+; CHECK-RV64-NEXT: bltz a1, .LBB61_920
; CHECK-RV64-NEXT: j .LBB61_418
; CHECK-RV64-NEXT: .LBB61_920: # %cond.load1617
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 406
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 405
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 405
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 41
-; CHECK-RV64-NEXT: bltz a2, .LBB61_921
+; CHECK-RV64-NEXT: slli a1, a2, 41
+; CHECK-RV64-NEXT: bltz a1, .LBB61_921
; CHECK-RV64-NEXT: j .LBB61_419
; CHECK-RV64-NEXT: .LBB61_921: # %cond.load1621
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 407
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 406
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 406
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 40
-; CHECK-RV64-NEXT: bltz a2, .LBB61_922
+; CHECK-RV64-NEXT: slli a1, a2, 40
+; CHECK-RV64-NEXT: bltz a1, .LBB61_922
; CHECK-RV64-NEXT: j .LBB61_420
; CHECK-RV64-NEXT: .LBB61_922: # %cond.load1625
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 408
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 407
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 407
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 39
-; CHECK-RV64-NEXT: bltz a2, .LBB61_923
+; CHECK-RV64-NEXT: slli a1, a2, 39
+; CHECK-RV64-NEXT: bltz a1, .LBB61_923
; CHECK-RV64-NEXT: j .LBB61_421
; CHECK-RV64-NEXT: .LBB61_923: # %cond.load1629
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 409
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 408
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 408
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 38
-; CHECK-RV64-NEXT: bltz a2, .LBB61_924
+; CHECK-RV64-NEXT: slli a1, a2, 38
+; CHECK-RV64-NEXT: bltz a1, .LBB61_924
; CHECK-RV64-NEXT: j .LBB61_422
; CHECK-RV64-NEXT: .LBB61_924: # %cond.load1633
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 410
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 409
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 409
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 37
-; CHECK-RV64-NEXT: bltz a2, .LBB61_925
+; CHECK-RV64-NEXT: slli a1, a2, 37
+; CHECK-RV64-NEXT: bltz a1, .LBB61_925
; CHECK-RV64-NEXT: j .LBB61_423
; CHECK-RV64-NEXT: .LBB61_925: # %cond.load1637
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 411
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 410
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 410
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 36
-; CHECK-RV64-NEXT: bltz a2, .LBB61_926
+; CHECK-RV64-NEXT: slli a1, a2, 36
+; CHECK-RV64-NEXT: bltz a1, .LBB61_926
; CHECK-RV64-NEXT: j .LBB61_424
; CHECK-RV64-NEXT: .LBB61_926: # %cond.load1641
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 412
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 411
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 411
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 35
-; CHECK-RV64-NEXT: bltz a2, .LBB61_927
+; CHECK-RV64-NEXT: slli a1, a2, 35
+; CHECK-RV64-NEXT: bltz a1, .LBB61_927
; CHECK-RV64-NEXT: j .LBB61_425
; CHECK-RV64-NEXT: .LBB61_927: # %cond.load1645
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 413
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 412
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 412
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 34
-; CHECK-RV64-NEXT: bltz a2, .LBB61_928
+; CHECK-RV64-NEXT: slli a1, a2, 34
+; CHECK-RV64-NEXT: bltz a1, .LBB61_928
; CHECK-RV64-NEXT: j .LBB61_426
; CHECK-RV64-NEXT: .LBB61_928: # %cond.load1649
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 414
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 413
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 413
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 33
-; CHECK-RV64-NEXT: bltz a2, .LBB61_929
+; CHECK-RV64-NEXT: slli a1, a2, 33
+; CHECK-RV64-NEXT: bltz a1, .LBB61_929
; CHECK-RV64-NEXT: j .LBB61_427
; CHECK-RV64-NEXT: .LBB61_929: # %cond.load1653
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 415
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 414
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 414
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 32
-; CHECK-RV64-NEXT: bltz a2, .LBB61_930
+; CHECK-RV64-NEXT: slli a1, a2, 32
+; CHECK-RV64-NEXT: bltz a1, .LBB61_930
; CHECK-RV64-NEXT: j .LBB61_428
; CHECK-RV64-NEXT: .LBB61_930: # %cond.load1657
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 416
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 415
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 415
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 31
-; CHECK-RV64-NEXT: bltz a2, .LBB61_931
+; CHECK-RV64-NEXT: slli a1, a2, 31
+; CHECK-RV64-NEXT: bltz a1, .LBB61_931
; CHECK-RV64-NEXT: j .LBB61_429
; CHECK-RV64-NEXT: .LBB61_931: # %cond.load1661
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 417
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 416
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 416
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 30
-; CHECK-RV64-NEXT: bltz a2, .LBB61_932
+; CHECK-RV64-NEXT: slli a1, a2, 30
+; CHECK-RV64-NEXT: bltz a1, .LBB61_932
; CHECK-RV64-NEXT: j .LBB61_430
; CHECK-RV64-NEXT: .LBB61_932: # %cond.load1665
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 418
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 417
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 417
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 29
-; CHECK-RV64-NEXT: bltz a2, .LBB61_933
+; CHECK-RV64-NEXT: slli a1, a2, 29
+; CHECK-RV64-NEXT: bltz a1, .LBB61_933
; CHECK-RV64-NEXT: j .LBB61_431
; CHECK-RV64-NEXT: .LBB61_933: # %cond.load1669
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 419
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 418
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 418
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 28
-; CHECK-RV64-NEXT: bltz a2, .LBB61_934
+; CHECK-RV64-NEXT: slli a1, a2, 28
+; CHECK-RV64-NEXT: bltz a1, .LBB61_934
; CHECK-RV64-NEXT: j .LBB61_432
; CHECK-RV64-NEXT: .LBB61_934: # %cond.load1673
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 420
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 419
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 419
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 27
-; CHECK-RV64-NEXT: bltz a2, .LBB61_935
+; CHECK-RV64-NEXT: slli a1, a2, 27
+; CHECK-RV64-NEXT: bltz a1, .LBB61_935
; CHECK-RV64-NEXT: j .LBB61_433
; CHECK-RV64-NEXT: .LBB61_935: # %cond.load1677
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 421
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 420
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 420
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 26
-; CHECK-RV64-NEXT: bltz a2, .LBB61_936
+; CHECK-RV64-NEXT: slli a1, a2, 26
+; CHECK-RV64-NEXT: bltz a1, .LBB61_936
; CHECK-RV64-NEXT: j .LBB61_434
; CHECK-RV64-NEXT: .LBB61_936: # %cond.load1681
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 422
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 421
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 421
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 25
-; CHECK-RV64-NEXT: bltz a2, .LBB61_937
+; CHECK-RV64-NEXT: slli a1, a2, 25
+; CHECK-RV64-NEXT: bltz a1, .LBB61_937
; CHECK-RV64-NEXT: j .LBB61_435
; CHECK-RV64-NEXT: .LBB61_937: # %cond.load1685
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 423
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 422
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 422
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 24
-; CHECK-RV64-NEXT: bltz a2, .LBB61_938
+; CHECK-RV64-NEXT: slli a1, a2, 24
+; CHECK-RV64-NEXT: bltz a1, .LBB61_938
; CHECK-RV64-NEXT: j .LBB61_436
; CHECK-RV64-NEXT: .LBB61_938: # %cond.load1689
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 424
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 423
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 423
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 23
-; CHECK-RV64-NEXT: bltz a2, .LBB61_939
+; CHECK-RV64-NEXT: slli a1, a2, 23
+; CHECK-RV64-NEXT: bltz a1, .LBB61_939
; CHECK-RV64-NEXT: j .LBB61_437
; CHECK-RV64-NEXT: .LBB61_939: # %cond.load1693
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 425
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 424
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 424
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 22
-; CHECK-RV64-NEXT: bltz a2, .LBB61_940
+; CHECK-RV64-NEXT: slli a1, a2, 22
+; CHECK-RV64-NEXT: bltz a1, .LBB61_940
; CHECK-RV64-NEXT: j .LBB61_438
; CHECK-RV64-NEXT: .LBB61_940: # %cond.load1697
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 426
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 425
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 425
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 21
-; CHECK-RV64-NEXT: bltz a2, .LBB61_941
+; CHECK-RV64-NEXT: slli a1, a2, 21
+; CHECK-RV64-NEXT: bltz a1, .LBB61_941
; CHECK-RV64-NEXT: j .LBB61_439
; CHECK-RV64-NEXT: .LBB61_941: # %cond.load1701
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 427
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 426
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 426
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 20
-; CHECK-RV64-NEXT: bltz a2, .LBB61_942
+; CHECK-RV64-NEXT: slli a1, a2, 20
+; CHECK-RV64-NEXT: bltz a1, .LBB61_942
; CHECK-RV64-NEXT: j .LBB61_440
; CHECK-RV64-NEXT: .LBB61_942: # %cond.load1705
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 428
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 427
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 427
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 19
-; CHECK-RV64-NEXT: bltz a2, .LBB61_943
+; CHECK-RV64-NEXT: slli a1, a2, 19
+; CHECK-RV64-NEXT: bltz a1, .LBB61_943
; CHECK-RV64-NEXT: j .LBB61_441
; CHECK-RV64-NEXT: .LBB61_943: # %cond.load1709
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 429
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 428
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 428
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 18
-; CHECK-RV64-NEXT: bltz a2, .LBB61_944
+; CHECK-RV64-NEXT: slli a1, a2, 18
+; CHECK-RV64-NEXT: bltz a1, .LBB61_944
; CHECK-RV64-NEXT: j .LBB61_442
; CHECK-RV64-NEXT: .LBB61_944: # %cond.load1713
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 430
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 429
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 429
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 17
-; CHECK-RV64-NEXT: bltz a2, .LBB61_945
+; CHECK-RV64-NEXT: slli a1, a2, 17
+; CHECK-RV64-NEXT: bltz a1, .LBB61_945
; CHECK-RV64-NEXT: j .LBB61_443
; CHECK-RV64-NEXT: .LBB61_945: # %cond.load1717
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 431
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 430
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 430
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 16
-; CHECK-RV64-NEXT: bltz a2, .LBB61_946
+; CHECK-RV64-NEXT: slli a1, a2, 16
+; CHECK-RV64-NEXT: bltz a1, .LBB61_946
; CHECK-RV64-NEXT: j .LBB61_444
; CHECK-RV64-NEXT: .LBB61_946: # %cond.load1721
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 432
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 431
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 431
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 15
-; CHECK-RV64-NEXT: bltz a2, .LBB61_947
+; CHECK-RV64-NEXT: slli a1, a2, 15
+; CHECK-RV64-NEXT: bltz a1, .LBB61_947
; CHECK-RV64-NEXT: j .LBB61_445
; CHECK-RV64-NEXT: .LBB61_947: # %cond.load1725
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 433
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 432
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 432
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 14
-; CHECK-RV64-NEXT: bltz a2, .LBB61_948
+; CHECK-RV64-NEXT: slli a1, a2, 14
+; CHECK-RV64-NEXT: bltz a1, .LBB61_948
; CHECK-RV64-NEXT: j .LBB61_446
; CHECK-RV64-NEXT: .LBB61_948: # %cond.load1729
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 434
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 433
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 433
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 13
-; CHECK-RV64-NEXT: bltz a2, .LBB61_949
+; CHECK-RV64-NEXT: slli a1, a2, 13
+; CHECK-RV64-NEXT: bltz a1, .LBB61_949
; CHECK-RV64-NEXT: j .LBB61_447
; CHECK-RV64-NEXT: .LBB61_949: # %cond.load1733
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 435
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 434
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 434
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 12
-; CHECK-RV64-NEXT: bltz a2, .LBB61_950
+; CHECK-RV64-NEXT: slli a1, a2, 12
+; CHECK-RV64-NEXT: bltz a1, .LBB61_950
; CHECK-RV64-NEXT: j .LBB61_448
; CHECK-RV64-NEXT: .LBB61_950: # %cond.load1737
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 436
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 435
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 435
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 11
-; CHECK-RV64-NEXT: bltz a2, .LBB61_951
+; CHECK-RV64-NEXT: slli a1, a2, 11
+; CHECK-RV64-NEXT: bltz a1, .LBB61_951
; CHECK-RV64-NEXT: j .LBB61_449
; CHECK-RV64-NEXT: .LBB61_951: # %cond.load1741
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 437
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 436
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 436
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 10
-; CHECK-RV64-NEXT: bltz a2, .LBB61_952
+; CHECK-RV64-NEXT: slli a1, a2, 10
+; CHECK-RV64-NEXT: bltz a1, .LBB61_952
; CHECK-RV64-NEXT: j .LBB61_450
; CHECK-RV64-NEXT: .LBB61_952: # %cond.load1745
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 438
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 437
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 437
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 9
-; CHECK-RV64-NEXT: bltz a2, .LBB61_953
+; CHECK-RV64-NEXT: slli a1, a2, 9
+; CHECK-RV64-NEXT: bltz a1, .LBB61_953
; CHECK-RV64-NEXT: j .LBB61_451
; CHECK-RV64-NEXT: .LBB61_953: # %cond.load1749
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 439
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 438
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 438
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 8
-; CHECK-RV64-NEXT: bltz a2, .LBB61_954
+; CHECK-RV64-NEXT: slli a1, a2, 8
+; CHECK-RV64-NEXT: bltz a1, .LBB61_954
; CHECK-RV64-NEXT: j .LBB61_452
; CHECK-RV64-NEXT: .LBB61_954: # %cond.load1753
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 440
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 439
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 439
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 7
-; CHECK-RV64-NEXT: bltz a2, .LBB61_955
+; CHECK-RV64-NEXT: slli a1, a2, 7
+; CHECK-RV64-NEXT: bltz a1, .LBB61_955
; CHECK-RV64-NEXT: j .LBB61_453
; CHECK-RV64-NEXT: .LBB61_955: # %cond.load1757
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 441
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 440
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 440
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 6
-; CHECK-RV64-NEXT: bltz a2, .LBB61_956
+; CHECK-RV64-NEXT: slli a1, a2, 6
+; CHECK-RV64-NEXT: bltz a1, .LBB61_956
; CHECK-RV64-NEXT: j .LBB61_454
; CHECK-RV64-NEXT: .LBB61_956: # %cond.load1761
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 442
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 441
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 441
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: bltz a2, .LBB61_957
+; CHECK-RV64-NEXT: slli a1, a2, 5
+; CHECK-RV64-NEXT: bltz a1, .LBB61_957
; CHECK-RV64-NEXT: j .LBB61_455
; CHECK-RV64-NEXT: .LBB61_957: # %cond.load1765
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 443
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 442
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 442
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 4
-; CHECK-RV64-NEXT: bltz a2, .LBB61_958
+; CHECK-RV64-NEXT: slli a1, a2, 4
+; CHECK-RV64-NEXT: bltz a1, .LBB61_958
; CHECK-RV64-NEXT: j .LBB61_456
; CHECK-RV64-NEXT: .LBB61_958: # %cond.load1769
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 444
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 443
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 443
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 3
-; CHECK-RV64-NEXT: bltz a2, .LBB61_959
+; CHECK-RV64-NEXT: slli a1, a2, 3
+; CHECK-RV64-NEXT: bltz a1, .LBB61_959
; CHECK-RV64-NEXT: j .LBB61_457
; CHECK-RV64-NEXT: .LBB61_959: # %cond.load1773
-; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 445
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a2
-; CHECK-RV64-NEXT: li a2, 444
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
+; CHECK-RV64-NEXT: li a1, 444
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a2, a1, 2
-; CHECK-RV64-NEXT: bgez a2, .LBB61_1031
+; CHECK-RV64-NEXT: slli a1, a2, 2
+; CHECK-RV64-NEXT: bgez a1, .LBB61_1031
; CHECK-RV64-NEXT: j .LBB61_458
; CHECK-RV64-NEXT: .LBB61_1031: # %cond.load1773
; CHECK-RV64-NEXT: j .LBB61_459
; CHECK-RV64-NEXT: .LBB61_960: # %cond.load1785
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 448
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 448
; CHECK-RV64-NEXT: li a3, 447
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1
-; CHECK-RV64-NEXT: bnez a1, .LBB61_961
+; CHECK-RV64-NEXT: andi a2, a1, 1
+; CHECK-RV64-NEXT: bnez a2, .LBB61_961
; CHECK-RV64-NEXT: j .LBB61_463
; CHECK-RV64-NEXT: .LBB61_961: # %cond.load1789
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 449
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 448
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 448
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 2
-; CHECK-RV64-NEXT: bnez a1, .LBB61_962
+; CHECK-RV64-NEXT: andi a2, a1, 2
+; CHECK-RV64-NEXT: bnez a2, .LBB61_962
; CHECK-RV64-NEXT: j .LBB61_464
; CHECK-RV64-NEXT: .LBB61_962: # %cond.load1793
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 450
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 449
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 449
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 4
-; CHECK-RV64-NEXT: bnez a1, .LBB61_963
+; CHECK-RV64-NEXT: andi a2, a1, 4
+; CHECK-RV64-NEXT: bnez a2, .LBB61_963
; CHECK-RV64-NEXT: j .LBB61_465
; CHECK-RV64-NEXT: .LBB61_963: # %cond.load1797
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 451
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 450
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 450
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 8
-; CHECK-RV64-NEXT: bnez a1, .LBB61_964
+; CHECK-RV64-NEXT: andi a2, a1, 8
+; CHECK-RV64-NEXT: bnez a2, .LBB61_964
; CHECK-RV64-NEXT: j .LBB61_466
; CHECK-RV64-NEXT: .LBB61_964: # %cond.load1801
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 452
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 451
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 451
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 16
-; CHECK-RV64-NEXT: bnez a1, .LBB61_965
+; CHECK-RV64-NEXT: andi a2, a1, 16
+; CHECK-RV64-NEXT: bnez a2, .LBB61_965
; CHECK-RV64-NEXT: j .LBB61_467
; CHECK-RV64-NEXT: .LBB61_965: # %cond.load1805
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 453
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 452
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 452
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 32
-; CHECK-RV64-NEXT: bnez a1, .LBB61_966
+; CHECK-RV64-NEXT: andi a2, a1, 32
+; CHECK-RV64-NEXT: bnez a2, .LBB61_966
; CHECK-RV64-NEXT: j .LBB61_468
; CHECK-RV64-NEXT: .LBB61_966: # %cond.load1809
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 454
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 453
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 453
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 64
-; CHECK-RV64-NEXT: bnez a1, .LBB61_967
+; CHECK-RV64-NEXT: andi a2, a1, 64
+; CHECK-RV64-NEXT: bnez a2, .LBB61_967
; CHECK-RV64-NEXT: j .LBB61_469
; CHECK-RV64-NEXT: .LBB61_967: # %cond.load1813
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 455
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 454
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 454
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 128
-; CHECK-RV64-NEXT: bnez a1, .LBB61_968
+; CHECK-RV64-NEXT: andi a2, a1, 128
+; CHECK-RV64-NEXT: bnez a2, .LBB61_968
; CHECK-RV64-NEXT: j .LBB61_470
; CHECK-RV64-NEXT: .LBB61_968: # %cond.load1817
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 456
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 455
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 455
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 256
-; CHECK-RV64-NEXT: bnez a1, .LBB61_969
+; CHECK-RV64-NEXT: andi a2, a1, 256
+; CHECK-RV64-NEXT: bnez a2, .LBB61_969
; CHECK-RV64-NEXT: j .LBB61_471
; CHECK-RV64-NEXT: .LBB61_969: # %cond.load1821
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 457
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 456
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 456
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 512
-; CHECK-RV64-NEXT: bnez a1, .LBB61_970
+; CHECK-RV64-NEXT: andi a2, a1, 512
+; CHECK-RV64-NEXT: bnez a2, .LBB61_970
; CHECK-RV64-NEXT: j .LBB61_472
; CHECK-RV64-NEXT: .LBB61_970: # %cond.load1825
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 458
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 457
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 457
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: andi a1, a2, 1024
-; CHECK-RV64-NEXT: bnez a1, .LBB61_971
+; CHECK-RV64-NEXT: andi a2, a1, 1024
+; CHECK-RV64-NEXT: bnez a2, .LBB61_971
; CHECK-RV64-NEXT: j .LBB61_473
; CHECK-RV64-NEXT: .LBB61_971: # %cond.load1829
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 459
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 458
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 458
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 52
-; CHECK-RV64-NEXT: bltz a1, .LBB61_972
+; CHECK-RV64-NEXT: slli a2, a1, 52
+; CHECK-RV64-NEXT: bltz a2, .LBB61_972
; CHECK-RV64-NEXT: j .LBB61_474
; CHECK-RV64-NEXT: .LBB61_972: # %cond.load1833
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 460
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 459
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 459
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 51
-; CHECK-RV64-NEXT: bltz a1, .LBB61_973
+; CHECK-RV64-NEXT: slli a2, a1, 51
+; CHECK-RV64-NEXT: bltz a2, .LBB61_973
; CHECK-RV64-NEXT: j .LBB61_475
; CHECK-RV64-NEXT: .LBB61_973: # %cond.load1837
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 461
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 460
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 460
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 50
-; CHECK-RV64-NEXT: bltz a1, .LBB61_974
+; CHECK-RV64-NEXT: slli a2, a1, 50
+; CHECK-RV64-NEXT: bltz a2, .LBB61_974
; CHECK-RV64-NEXT: j .LBB61_476
; CHECK-RV64-NEXT: .LBB61_974: # %cond.load1841
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 462
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 461
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 461
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 49
-; CHECK-RV64-NEXT: bltz a1, .LBB61_975
+; CHECK-RV64-NEXT: slli a2, a1, 49
+; CHECK-RV64-NEXT: bltz a2, .LBB61_975
; CHECK-RV64-NEXT: j .LBB61_477
; CHECK-RV64-NEXT: .LBB61_975: # %cond.load1845
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 463
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 462
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 462
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 48
-; CHECK-RV64-NEXT: bltz a1, .LBB61_976
+; CHECK-RV64-NEXT: slli a2, a1, 48
+; CHECK-RV64-NEXT: bltz a2, .LBB61_976
; CHECK-RV64-NEXT: j .LBB61_478
; CHECK-RV64-NEXT: .LBB61_976: # %cond.load1849
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 464
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 463
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 463
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 47
-; CHECK-RV64-NEXT: bltz a1, .LBB61_977
+; CHECK-RV64-NEXT: slli a2, a1, 47
+; CHECK-RV64-NEXT: bltz a2, .LBB61_977
; CHECK-RV64-NEXT: j .LBB61_479
; CHECK-RV64-NEXT: .LBB61_977: # %cond.load1853
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 465
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 464
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 464
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 46
-; CHECK-RV64-NEXT: bltz a1, .LBB61_978
+; CHECK-RV64-NEXT: slli a2, a1, 46
+; CHECK-RV64-NEXT: bltz a2, .LBB61_978
; CHECK-RV64-NEXT: j .LBB61_480
; CHECK-RV64-NEXT: .LBB61_978: # %cond.load1857
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 466
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 465
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 465
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 45
-; CHECK-RV64-NEXT: bltz a1, .LBB61_979
+; CHECK-RV64-NEXT: slli a2, a1, 45
+; CHECK-RV64-NEXT: bltz a2, .LBB61_979
; CHECK-RV64-NEXT: j .LBB61_481
; CHECK-RV64-NEXT: .LBB61_979: # %cond.load1861
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 467
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 466
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 466
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 44
-; CHECK-RV64-NEXT: bltz a1, .LBB61_980
+; CHECK-RV64-NEXT: slli a2, a1, 44
+; CHECK-RV64-NEXT: bltz a2, .LBB61_980
; CHECK-RV64-NEXT: j .LBB61_482
; CHECK-RV64-NEXT: .LBB61_980: # %cond.load1865
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 468
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 467
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 467
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 43
-; CHECK-RV64-NEXT: bltz a1, .LBB61_981
+; CHECK-RV64-NEXT: slli a2, a1, 43
+; CHECK-RV64-NEXT: bltz a2, .LBB61_981
; CHECK-RV64-NEXT: j .LBB61_483
; CHECK-RV64-NEXT: .LBB61_981: # %cond.load1869
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 469
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 468
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 468
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 42
-; CHECK-RV64-NEXT: bltz a1, .LBB61_982
+; CHECK-RV64-NEXT: slli a2, a1, 42
+; CHECK-RV64-NEXT: bltz a2, .LBB61_982
; CHECK-RV64-NEXT: j .LBB61_484
; CHECK-RV64-NEXT: .LBB61_982: # %cond.load1873
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 470
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 469
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 469
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 41
-; CHECK-RV64-NEXT: bltz a1, .LBB61_983
+; CHECK-RV64-NEXT: slli a2, a1, 41
+; CHECK-RV64-NEXT: bltz a2, .LBB61_983
; CHECK-RV64-NEXT: j .LBB61_485
; CHECK-RV64-NEXT: .LBB61_983: # %cond.load1877
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 471
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 470
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 470
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 40
-; CHECK-RV64-NEXT: bltz a1, .LBB61_984
+; CHECK-RV64-NEXT: slli a2, a1, 40
+; CHECK-RV64-NEXT: bltz a2, .LBB61_984
; CHECK-RV64-NEXT: j .LBB61_486
; CHECK-RV64-NEXT: .LBB61_984: # %cond.load1881
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 472
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 471
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 471
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 39
-; CHECK-RV64-NEXT: bltz a1, .LBB61_985
+; CHECK-RV64-NEXT: slli a2, a1, 39
+; CHECK-RV64-NEXT: bltz a2, .LBB61_985
; CHECK-RV64-NEXT: j .LBB61_487
; CHECK-RV64-NEXT: .LBB61_985: # %cond.load1885
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 473
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 472
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 472
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 38
-; CHECK-RV64-NEXT: bltz a1, .LBB61_986
+; CHECK-RV64-NEXT: slli a2, a1, 38
+; CHECK-RV64-NEXT: bltz a2, .LBB61_986
; CHECK-RV64-NEXT: j .LBB61_488
; CHECK-RV64-NEXT: .LBB61_986: # %cond.load1889
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 474
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 473
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 473
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 37
-; CHECK-RV64-NEXT: bltz a1, .LBB61_987
+; CHECK-RV64-NEXT: slli a2, a1, 37
+; CHECK-RV64-NEXT: bltz a2, .LBB61_987
; CHECK-RV64-NEXT: j .LBB61_489
; CHECK-RV64-NEXT: .LBB61_987: # %cond.load1893
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 475
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 474
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 474
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 36
-; CHECK-RV64-NEXT: bltz a1, .LBB61_988
+; CHECK-RV64-NEXT: slli a2, a1, 36
+; CHECK-RV64-NEXT: bltz a2, .LBB61_988
; CHECK-RV64-NEXT: j .LBB61_490
; CHECK-RV64-NEXT: .LBB61_988: # %cond.load1897
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 476
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 475
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 475
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 35
-; CHECK-RV64-NEXT: bltz a1, .LBB61_989
+; CHECK-RV64-NEXT: slli a2, a1, 35
+; CHECK-RV64-NEXT: bltz a2, .LBB61_989
; CHECK-RV64-NEXT: j .LBB61_491
; CHECK-RV64-NEXT: .LBB61_989: # %cond.load1901
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 477
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 476
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 476
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 34
-; CHECK-RV64-NEXT: bltz a1, .LBB61_990
+; CHECK-RV64-NEXT: slli a2, a1, 34
+; CHECK-RV64-NEXT: bltz a2, .LBB61_990
; CHECK-RV64-NEXT: j .LBB61_492
; CHECK-RV64-NEXT: .LBB61_990: # %cond.load1905
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 478
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 477
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 477
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 33
-; CHECK-RV64-NEXT: bltz a1, .LBB61_991
+; CHECK-RV64-NEXT: slli a2, a1, 33
+; CHECK-RV64-NEXT: bltz a2, .LBB61_991
; CHECK-RV64-NEXT: j .LBB61_493
; CHECK-RV64-NEXT: .LBB61_991: # %cond.load1909
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 479
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 478
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 478
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 32
-; CHECK-RV64-NEXT: bltz a1, .LBB61_992
+; CHECK-RV64-NEXT: slli a2, a1, 32
+; CHECK-RV64-NEXT: bltz a2, .LBB61_992
; CHECK-RV64-NEXT: j .LBB61_494
; CHECK-RV64-NEXT: .LBB61_992: # %cond.load1913
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 480
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 479
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 479
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 31
-; CHECK-RV64-NEXT: bltz a1, .LBB61_993
+; CHECK-RV64-NEXT: slli a2, a1, 31
+; CHECK-RV64-NEXT: bltz a2, .LBB61_993
; CHECK-RV64-NEXT: j .LBB61_495
; CHECK-RV64-NEXT: .LBB61_993: # %cond.load1917
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 481
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 480
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 480
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 30
-; CHECK-RV64-NEXT: bltz a1, .LBB61_994
+; CHECK-RV64-NEXT: slli a2, a1, 30
+; CHECK-RV64-NEXT: bltz a2, .LBB61_994
; CHECK-RV64-NEXT: j .LBB61_496
; CHECK-RV64-NEXT: .LBB61_994: # %cond.load1921
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 482
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 481
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 481
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 29
-; CHECK-RV64-NEXT: bltz a1, .LBB61_995
+; CHECK-RV64-NEXT: slli a2, a1, 29
+; CHECK-RV64-NEXT: bltz a2, .LBB61_995
; CHECK-RV64-NEXT: j .LBB61_497
; CHECK-RV64-NEXT: .LBB61_995: # %cond.load1925
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 483
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 482
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 482
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 28
-; CHECK-RV64-NEXT: bltz a1, .LBB61_996
+; CHECK-RV64-NEXT: slli a2, a1, 28
+; CHECK-RV64-NEXT: bltz a2, .LBB61_996
; CHECK-RV64-NEXT: j .LBB61_498
; CHECK-RV64-NEXT: .LBB61_996: # %cond.load1929
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 484
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 483
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 483
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 27
-; CHECK-RV64-NEXT: bltz a1, .LBB61_997
+; CHECK-RV64-NEXT: slli a2, a1, 27
+; CHECK-RV64-NEXT: bltz a2, .LBB61_997
; CHECK-RV64-NEXT: j .LBB61_499
; CHECK-RV64-NEXT: .LBB61_997: # %cond.load1933
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 485
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 484
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 484
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 26
-; CHECK-RV64-NEXT: bltz a1, .LBB61_998
+; CHECK-RV64-NEXT: slli a2, a1, 26
+; CHECK-RV64-NEXT: bltz a2, .LBB61_998
; CHECK-RV64-NEXT: j .LBB61_500
; CHECK-RV64-NEXT: .LBB61_998: # %cond.load1937
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 486
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 485
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 485
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 25
-; CHECK-RV64-NEXT: bltz a1, .LBB61_999
+; CHECK-RV64-NEXT: slli a2, a1, 25
+; CHECK-RV64-NEXT: bltz a2, .LBB61_999
; CHECK-RV64-NEXT: j .LBB61_501
; CHECK-RV64-NEXT: .LBB61_999: # %cond.load1941
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 487
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 486
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 486
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 24
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1000
+; CHECK-RV64-NEXT: slli a2, a1, 24
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1000
; CHECK-RV64-NEXT: j .LBB61_502
; CHECK-RV64-NEXT: .LBB61_1000: # %cond.load1945
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 488
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 487
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 487
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 23
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1001
+; CHECK-RV64-NEXT: slli a2, a1, 23
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1001
; CHECK-RV64-NEXT: j .LBB61_503
; CHECK-RV64-NEXT: .LBB61_1001: # %cond.load1949
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 489
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 488
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 488
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 22
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1002
+; CHECK-RV64-NEXT: slli a2, a1, 22
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1002
; CHECK-RV64-NEXT: j .LBB61_504
; CHECK-RV64-NEXT: .LBB61_1002: # %cond.load1953
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 490
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 489
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 489
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 21
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1003
+; CHECK-RV64-NEXT: slli a2, a1, 21
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1003
; CHECK-RV64-NEXT: j .LBB61_505
; CHECK-RV64-NEXT: .LBB61_1003: # %cond.load1957
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 491
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 490
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 490
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 20
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1004
+; CHECK-RV64-NEXT: slli a2, a1, 20
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1004
; CHECK-RV64-NEXT: j .LBB61_506
; CHECK-RV64-NEXT: .LBB61_1004: # %cond.load1961
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 492
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 491
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 491
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 19
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1005
+; CHECK-RV64-NEXT: slli a2, a1, 19
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1005
; CHECK-RV64-NEXT: j .LBB61_507
; CHECK-RV64-NEXT: .LBB61_1005: # %cond.load1965
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 493
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 492
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 492
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 18
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1006
+; CHECK-RV64-NEXT: slli a2, a1, 18
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1006
; CHECK-RV64-NEXT: j .LBB61_508
; CHECK-RV64-NEXT: .LBB61_1006: # %cond.load1969
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 494
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 493
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 493
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 17
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1007
+; CHECK-RV64-NEXT: slli a2, a1, 17
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1007
; CHECK-RV64-NEXT: j .LBB61_509
; CHECK-RV64-NEXT: .LBB61_1007: # %cond.load1973
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 495
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 494
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 494
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 16
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1008
+; CHECK-RV64-NEXT: slli a2, a1, 16
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1008
; CHECK-RV64-NEXT: j .LBB61_510
; CHECK-RV64-NEXT: .LBB61_1008: # %cond.load1977
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 496
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 495
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 495
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 15
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1009
+; CHECK-RV64-NEXT: slli a2, a1, 15
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1009
; CHECK-RV64-NEXT: j .LBB61_511
; CHECK-RV64-NEXT: .LBB61_1009: # %cond.load1981
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 497
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 496
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 496
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 14
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1010
+; CHECK-RV64-NEXT: slli a2, a1, 14
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1010
; CHECK-RV64-NEXT: j .LBB61_512
; CHECK-RV64-NEXT: .LBB61_1010: # %cond.load1985
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 498
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 497
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 497
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 13
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1011
+; CHECK-RV64-NEXT: slli a2, a1, 13
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1011
; CHECK-RV64-NEXT: j .LBB61_513
; CHECK-RV64-NEXT: .LBB61_1011: # %cond.load1989
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 499
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 498
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 498
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 12
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1012
+; CHECK-RV64-NEXT: slli a2, a1, 12
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1012
; CHECK-RV64-NEXT: j .LBB61_514
; CHECK-RV64-NEXT: .LBB61_1012: # %cond.load1993
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 500
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 499
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 499
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 11
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1013
+; CHECK-RV64-NEXT: slli a2, a1, 11
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1013
; CHECK-RV64-NEXT: j .LBB61_515
; CHECK-RV64-NEXT: .LBB61_1013: # %cond.load1997
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 501
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 500
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 500
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 10
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1014
+; CHECK-RV64-NEXT: slli a2, a1, 10
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1014
; CHECK-RV64-NEXT: j .LBB61_516
; CHECK-RV64-NEXT: .LBB61_1014: # %cond.load2001
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 502
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 501
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 501
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 9
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1015
+; CHECK-RV64-NEXT: slli a2, a1, 9
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1015
; CHECK-RV64-NEXT: j .LBB61_517
; CHECK-RV64-NEXT: .LBB61_1015: # %cond.load2005
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 503
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 502
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 502
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 8
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1016
+; CHECK-RV64-NEXT: slli a2, a1, 8
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1016
; CHECK-RV64-NEXT: j .LBB61_518
; CHECK-RV64-NEXT: .LBB61_1016: # %cond.load2009
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 504
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 503
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 503
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 7
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1017
+; CHECK-RV64-NEXT: slli a2, a1, 7
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1017
; CHECK-RV64-NEXT: j .LBB61_519
; CHECK-RV64-NEXT: .LBB61_1017: # %cond.load2013
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 505
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 504
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 504
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 6
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1018
+; CHECK-RV64-NEXT: slli a2, a1, 6
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1018
; CHECK-RV64-NEXT: j .LBB61_520
; CHECK-RV64-NEXT: .LBB61_1018: # %cond.load2017
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 506
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 505
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 505
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 5
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1019
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1019
; CHECK-RV64-NEXT: j .LBB61_521
; CHECK-RV64-NEXT: .LBB61_1019: # %cond.load2021
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 507
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 506
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 506
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 4
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1020
+; CHECK-RV64-NEXT: slli a2, a1, 4
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1020
; CHECK-RV64-NEXT: j .LBB61_522
; CHECK-RV64-NEXT: .LBB61_1020: # %cond.load2025
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 508
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 507
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 507
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 3
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1021
+; CHECK-RV64-NEXT: slli a2, a1, 3
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1021
; CHECK-RV64-NEXT: j .LBB61_523
; CHECK-RV64-NEXT: .LBB61_1021: # %cond.load2029
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 509
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 508
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 508
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 2
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1022
+; CHECK-RV64-NEXT: slli a2, a1, 2
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1022
; CHECK-RV64-NEXT: j .LBB61_524
; CHECK-RV64-NEXT: .LBB61_1022: # %cond.load2033
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 510
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 509
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 509
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: slli a1, a2, 1
-; CHECK-RV64-NEXT: bltz a1, .LBB61_1023
+; CHECK-RV64-NEXT: slli a2, a1, 1
+; CHECK-RV64-NEXT: bltz a2, .LBB61_1023
; CHECK-RV64-NEXT: j .LBB61_525
; CHECK-RV64-NEXT: .LBB61_1023: # %cond.load2037
-; CHECK-RV64-NEXT: lbu a1, 0(a0)
+; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 511
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-RV64-NEXT: vmv.s.x v16, a1
-; CHECK-RV64-NEXT: li a1, 510
-; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
+; CHECK-RV64-NEXT: li a2, 510
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
-; CHECK-RV64-NEXT: bltz a2, .LBB61_1024
+; CHECK-RV64-NEXT: bltz a1, .LBB61_1024
; CHECK-RV64-NEXT: j .LBB61_526
; CHECK-RV64-NEXT: .LBB61_1024: # %cond.load2041
; CHECK-RV64-NEXT: lbu a0, 0(a0)
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