[llvm] [AMDGPU][GlobalISel] Reduce instruction count for store in global addrspace for non-powers-of-2 (PR #206043)

[Krzysztof Drewniak via llvm-commits]

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krzysz00 wrote:

You only need the alignment constraint if the triple requires aligned loads (AMDHSA doesn't)

https://github.com/llvm/llvm-project/pull/206043