[llvm] AMDGPU: Prefer getting the triple from the module over the TargetMachine (PR #206055)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 07:27:36 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/206055
>From e03fb67396b93952af668512facc6c106024b02b Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 26 Jun 2026 14:44:28 +0200
Subject: [PATCH] AMDGPU: Prefer getting the triple from the module over the
TargetMachine
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 6 ++--
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 21 ++++++++------
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp | 28 +++++++------------
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 ++--
llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp | 1 +
6 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index c6dd1dbb62449..e4367811f1ed4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -326,12 +326,10 @@ struct AMDGPULowerExecSyncPass
void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
extern char &AMDGPUSwLowerLDSLegacyPassID;
-ModulePass *
-createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
+ModulePass *createAMDGPUSwLowerLDSLegacyPass();
struct AMDGPUSwLowerLDSPass : OptionalPassInfoMixin<AMDGPUSwLowerLDSPass> {
- const AMDGPUTargetMachine &TM;
- AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
+ AMDGPUSwLowerLDSPass() = default;
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
};
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 3d191125aac47..53d45d97ab527 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -144,19 +144,19 @@ void AMDGPUAsmPrinter::initTargetStreamer(Module &M) {
if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
initializeTargetID(M);
- if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
- TM.getTargetTriple().getOS() != Triple::AMDPAL)
+ const Triple &TT = M.getTargetTriple();
+ if (TT.getOS() != Triple::AMDHSA && TT.getOS() != Triple::AMDPAL)
return;
getTargetStreamer()->EmitDirectiveAMDGCNTarget();
- if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
+ if (TT.getOS() == Triple::AMDHSA) {
getTargetStreamer()->EmitDirectiveAMDHSACodeObjectVersion(
CodeObjectVersion);
HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
}
- if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
+ if (TT.getOS() == Triple::AMDPAL)
getTargetStreamer()->getPALMetadata()->readFromIR(M);
}
@@ -165,12 +165,13 @@ void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
if (!IsTargetStreamerInitialized)
initTargetStreamer(M);
- if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
+ const Triple &TT = M.getTargetTriple();
+ if (TT.getOS() != Triple::AMDHSA)
getTargetStreamer()->EmitISAVersion();
// Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
// Emit HSA Metadata (NT_AMD_HSA_METADATA).
- if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
+ if (TT.getOS() == Triple::AMDHSA) {
HSAMetadataStream->end();
bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
(void)Success;
@@ -399,9 +400,10 @@ void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
}
bool AMDGPUAsmPrinter::doInitialization(Module &M) {
+ const llvm::Triple &TT = M.getTargetTriple();
CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(M);
- if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
+ if (TT.getOS() == Triple::AMDHSA) {
switch (CodeObjectVersion) {
case AMDGPU::AMDHSA_COV4:
HSAMetadataStream = std::make_unique<HSAMD::MetadataStreamerMsgPackV4>();
@@ -713,14 +715,15 @@ void AMDGPUAsmPrinter::emitAMDGPUInfo(Module &M) {
}
bool AMDGPUAsmPrinter::doFinalization(Module &M) {
+ const Triple &TT = M.getTargetTriple();
+
// Pad with s_code_end to help tools and guard against instruction prefetch
// causing stale data in caches. Arguably this should be done by the linker,
// which is why this isn't done for Mesa.
// Don't do it if there is no code.
const MCSubtargetInfo &STI = *getGlobalSTI();
if ((AMDGPU::isGFX10Plus(STI) || AMDGPU::isGFX90A(STI)) &&
- (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
- STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
+ (TT.getOS() == Triple::AMDHSA || TT.getOS() == Triple::AMDPAL)) {
MCSection *TextSect = getObjFileLowering().getTextSection();
if (TextSect->hasInstructions()) {
OutStreamer->switchSection(TextSect);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 2a6560b309e62..d052f3c73920c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -30,7 +30,7 @@ MODULE_PASS("amdgpu-preload-kernel-arguments", AMDGPUPreloadKernelArgumentsPass(
MODULE_PASS("amdgpu-printf-runtime-binding", AMDGPUPrintfRuntimeBindingPass())
MODULE_PASS("amdgpu-remove-incompatible-functions", AMDGPURemoveIncompatibleFunctionsPass(*this))
MODULE_PASS("amdgpu-lower-exec-sync", AMDGPULowerExecSyncPass())
-MODULE_PASS("amdgpu-sw-lower-lds", AMDGPUSwLowerLDSPass(*this))
+MODULE_PASS("amdgpu-sw-lower-lds", AMDGPUSwLowerLDSPass())
#undef MODULE_PASS
#ifndef MODULE_PASS_WITH_PARAMS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index ccd8066c63fd6..f410fa97f90ea 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -173,9 +173,8 @@ struct FunctionsAndLDSAccess {
class AMDGPUSwLowerLDS {
public:
- AMDGPUSwLowerLDS(Module &Mod, const AMDGPUTargetMachine &TM,
- DomTreeCallback Callback)
- : M(Mod), AMDGPUTM(TM), IRB(M.getContext()), DTCallback(Callback) {}
+ AMDGPUSwLowerLDS(Module &Mod, DomTreeCallback Callback)
+ : M(Mod), IRB(M.getContext()), DTCallback(Callback) {}
bool run();
void getUsesOfLDSByNonKernels();
void getNonKernelsWithLDSArguments(const CallGraph &CG);
@@ -213,7 +212,6 @@ class AMDGPUSwLowerLDS {
private:
Module &M;
- const AMDGPUTargetMachine &AMDGPUTM;
IRBuilder<> IRB;
DomTreeCallback DTCallback;
FunctionsAndLDSAccess FuncLDSAccessInfo;
@@ -1186,8 +1184,8 @@ void AMDGPUSwLowerLDS::initAsanInfo() {
uint64_t Offset;
int Scale;
bool OrShadowOffset;
- llvm::getAddressSanitizerParams(AMDGPUTM.getTargetTriple(), LongSize, false,
- &Offset, &Scale, &OrShadowOffset);
+ llvm::getAddressSanitizerParams(M.getTargetTriple(), LongSize, false, &Offset,
+ &Scale, &OrShadowOffset);
AsanInfo.Scale = Scale;
AsanInfo.Offset = Offset;
}
@@ -1358,10 +1356,8 @@ bool AMDGPUSwLowerLDS::run() {
class AMDGPUSwLowerLDSLegacy : public ModulePass {
public:
- const AMDGPUTargetMachine *AMDGPUTM;
static char ID;
- AMDGPUSwLowerLDSLegacy(const AMDGPUTargetMachine *TM)
- : ModulePass(ID), AMDGPUTM(TM) {}
+ AMDGPUSwLowerLDSLegacy() : ModulePass(ID) {}
bool runOnModule(Module &M) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addPreserved<DominatorTreeWrapperPass>();
@@ -1388,18 +1384,14 @@ bool AMDGPUSwLowerLDSLegacy::runOnModule(Module &M) {
auto DTCallback = [&DTW](Function &F) -> DominatorTree * {
return DTW ? &DTW->getDomTree() : nullptr;
};
- if (!AMDGPUTM) {
- auto &TPC = getAnalysis<TargetPassConfig>();
- AMDGPUTM = &TPC.getTM<AMDGPUTargetMachine>();
- }
- AMDGPUSwLowerLDS SwLowerLDSImpl(M, *AMDGPUTM, DTCallback);
+
+ AMDGPUSwLowerLDS SwLowerLDSImpl(M, DTCallback);
bool IsChanged = SwLowerLDSImpl.run();
return IsChanged;
}
-ModulePass *
-llvm::createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM) {
- return new AMDGPUSwLowerLDSLegacy(TM);
+ModulePass *llvm::createAMDGPUSwLowerLDSLegacyPass() {
+ return new AMDGPUSwLowerLDSLegacy();
}
PreservedAnalyses AMDGPUSwLowerLDSPass::run(Module &M,
@@ -1412,7 +1404,7 @@ PreservedAnalyses AMDGPUSwLowerLDSPass::run(Module &M,
auto DTCallback = [&FAM](Function &F) -> DominatorTree * {
return &FAM.getResult<DominatorTreeAnalysis>(F);
};
- AMDGPUSwLowerLDS SwLowerLDSImpl(M, TM, DTCallback);
+ AMDGPUSwLowerLDS SwLowerLDSImpl(M, DTCallback);
bool IsChanged = SwLowerLDSImpl.run();
if (!IsChanged)
return PreservedAnalyses::all();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index ae6e6d0bdcd1e..06bfc7e1a5162 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1090,7 +1090,7 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
if (EnableLowerExecSync)
PM.addPass(AMDGPULowerExecSyncPass());
if (EnableSwLowerLDS)
- PM.addPass(AMDGPUSwLowerLDSPass(*this));
+ PM.addPass(AMDGPUSwLowerLDSPass());
if (EnableLowerModuleLDS)
PM.addPass(AMDGPULowerModuleLDSPass(*this));
if (Level != OptimizationLevel::O0) {
@@ -1484,7 +1484,7 @@ void AMDGPUPassConfig::addIRPasses() {
// Lower LDS accesses to global memory pass if address sanitizer is enabled.
if (EnableSwLowerLDS)
- addPass(createAMDGPUSwLowerLDSLegacyPass(&TM));
+ addPass(createAMDGPUSwLowerLDSLegacyPass());
// Runs before PromoteAlloca so the latter can account for function uses
if (EnableLowerModuleLDS) {
@@ -2269,7 +2269,7 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(PassManagerWrapper &PMW) const {
addModulePass(AMDGPULowerExecSyncPass(), PMW);
if (EnableSwLowerLDS)
- addModulePass(AMDGPUSwLowerLDSPass(TM), PMW);
+ addModulePass(AMDGPUSwLowerLDSPass(), PMW);
// Runs before PromoteAlloca so the latter can account for function uses
if (EnableLowerModuleLDS)
diff --git a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
index 8165876e18a34..7f53f5322f548 100644
--- a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
+++ b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
@@ -65,6 +65,7 @@ class AMDGPUSelectionDAGTest : public testing::Test {
LLVMContext Context;
std::unique_ptr<Module> M(new Module("TestModule", Context));
+ M->setTargetTriple(TargetTriple);
M->setDataLayout(TM->createDataLayout());
legacy::PassManager PM;
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