[llvm] [AMDGPU][GlobalISel] Support lowering preloaded kernel arguments (PR #205049)

[Manuel Carrasco via llvm-commits]

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@@ -296,6 +297,203 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
     assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
   }
 };
+
+// Return the virtual register and type for a preloaded physical SGPR live-in.
+static std::pair<Register, LLT> getPreloadedLiveIn(MachineIRBuilder &B,
+                                                   MCRegister PhysReg,
+                                                   const SIRegisterInfo &TRI) {
+  MachineFunction &MF = B.getMF();
+  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
+  const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(PhysReg);
+  assert(RC && "expected a register class for preload SGPR");
+  LLT RegTy = LLT::scalar(TRI.getRegSizeInBits(*RC).getFixedValue());
+  return {getFunctionLiveInPhysReg(MF, *TII, PhysReg, *RC, B.getDL(), RegTy),
+          RegTy};
+}
+
+// Convert raw SGPR preload bits to the type expected by the formal argument.
+static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
+                                       LLT SrcTy, LLT DstTy) {
+  if (SrcTy == DstTy)
+    return Src;
+
+  LLT IntDstTy = (DstTy.isPointer() || DstTy.isVector())
+                     ? LLT::scalar(DstTy.getSizeInBits())
+                     : DstTy;
+  if (SrcTy.getSizeInBits() != IntDstTy.getSizeInBits())
+    Src = B.buildAnyExtOrTrunc(IntDstTy, Src).getReg(0);
+  else if (SrcTy != IntDstTy)
+    Src = B.buildBitcast(IntDstTy, Src).getReg(0);
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mgcarrasco wrote:

There is no test for this case. 

https://github.com/llvm/llvm-project/pull/205049