[llvm] [AMDGPU] Select uniform (shl, or) to a scalar S_LSHL_OR_B32 pseudo (PR #202585)

[Barbara Mitic via llvm-commits]

barbara-amd wrote:

> > In the pipeline I originally looked at, the missed v_lshlrev_b32 + v_or_b32 pairs are almost entirely the high-half 16-bit packing idiom, not a uniform/divergence problem - by ISel the shl is already a bitcast(BUILD_VECTOR <2 x i16>), so there's no (shl …) left for a pattern to match.
> 
> Do you have a solution for this case? It seems like you ought to be able to write an isel pattern that matches the build_vector.

Yes - I have a local patch that matches the build_vector directly and folds (or (bitcast (v2i16 build_vector (i16 0), hi)), z) into v_lshl_or_b32 (both operand orders, GFX9+). Tested against the AMDGPU codegen tests; the missed v_lshlrev_b32 + v_or_b32 pairs fuse.

Since it's a different mechanism, I'd prefer it as a separate PR. Do you still want this PR (the uniform S_LSHL_OR_B32 pseudo) as-is, and is a separate PR for the packing fix OK?

https://github.com/llvm/llvm-project/pull/202585