[llvm] [AMDGPU][AsmParser] Fix representing src2 op_sel for MAC instructions (PR #206033)

Fri Jun 26 04:09:44 PDT 2026

llvmorg-github-actions[bot] wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Ivan Kosarev (kosarev)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/206033.diff


5 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+5) 
- (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s (+3-3) 
- (modified) llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s (+5-7) 
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s (+3-3) 
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s (+1-1) 


``````````diff

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 161395fffca77..535ff8c0b2b71 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9964,6 +9964,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
     if (ModIdx == -1)
       continue;
 
+    // For MAC instructions, src2 is tied to vdst and its op_sel bit
+    // is not encoded.
+    if (AMDGPU::isMAC(Opc) && ModOps[J] == AMDGPU::OpName::src2_modifiers)
+      continue;
+
     uint32_t ModVal = 0;
 
     const MCOperand &SrcOp = Inst.getOperand(OpIdx);
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
index 8add60cac6d48..0bd9b102d507e 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
@@ -57,16 +57,16 @@ v_add_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
 // GFX11: v_add_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
 
 v_fmac_f16 v255.h, v1.h, v2.h
-// GFX11: v_fmac_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1,1] ; encoding: [0xff,0x58,0x36,0xd5,0x01,0x05,0x02,0x02]
+// GFX11: v_fmac_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,0,1] ; encoding: [0xff,0x58,0x36,0xd5,0x01,0x05,0x02,0x02]
 
 v_fmac_f16 v255.l, v1.l, v2.l
 // GFX11: v_fmac_f16_e64 v255.l, v1.l, v2.l       ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x02]
 
 v_fmac_f16 v5.h, v1.h, v255.h
-// GFX11: v_fmac_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1,1] ; encoding: [0x05,0x58,0x36,0xd5,0x01,0xff,0x03,0x02]
+// GFX11: v_fmac_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,0,1] ; encoding: [0x05,0x58,0x36,0xd5,0x01,0xff,0x03,0x02]
 
 v_fmac_f16 v5.h, v255.h, v2.h
-// GFX11: v_fmac_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1,1] ; encoding: [0x05,0x58,0x36,0xd5,0xff,0x05,0x02,0x02]
+// GFX11: v_fmac_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,0,1] ; encoding: [0x05,0x58,0x36,0xd5,0xff,0x05,0x02,0x02]
 
 v_fmac_f16 v5.l, v1.l, v255.l
 // GFX11: v_fmac_f16_e64 v5.l, v1.l, v255.l       ; encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
index 399913ed1ab1c..3e48289f991ff 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
@@ -1,8 +1,8 @@
 // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32,GFX11-ASM %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64,GFX11-ASM %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding | FileCheck --check-prefixes=GFX11,W32,GFX11-DIS %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding | FileCheck --check-prefixes=GFX11,W64,GFX11-DIS %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding | FileCheck --check-prefixes=GFX11,W64 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
 
@@ -640,10 +640,8 @@ v_fmac_f16_e64 v5.l, v1.h, v2.l
 v_fmac_f16_e64 v5.l, v255.l, v255.h
 // GFX11: v_fmac_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x36,0xd5,0xff,0xff,0x03,0x02]
 
-// TODO: When assembling, we print op_sel:[0,0,1,1], but encode op_sel:[0,0,0,1].
 v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2
-// GFX11-ASM: v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1,1] clamp div:2 ; encoding: [0xff,0xc3,0x36,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
-// GFX11-DIS: v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x36,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
+// GFX11: v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x36,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
 
 v_fmac_f32_e64 v5, v1, v2
 // GFX11: v_fmac_f32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
index 9f10a891eef6a..59075cbd368ab 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
@@ -56,16 +56,16 @@ v_add_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
 // GFX12: v_add_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
 
 v_fmac_f16 v255.h, v1.h, v2.h
-// GFX12: v_fmac_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1,1] ; encoding: [0xff,0x58,0x36,0xd5,0x01,0x05,0x02,0x02]
+// GFX12: v_fmac_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,0,1] ; encoding: [0xff,0x58,0x36,0xd5,0x01,0x05,0x02,0x02]
 
 v_fmac_f16 v255.l, v1.l, v2.l
 // GFX12: v_fmac_f16_e64 v255.l, v1.l, v2.l       ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x02]
 
 v_fmac_f16 v5.h, v1.h, v255.h
-// GFX12: v_fmac_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1,1] ; encoding: [0x05,0x58,0x36,0xd5,0x01,0xff,0x03,0x02]
+// GFX12: v_fmac_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,0,1] ; encoding: [0x05,0x58,0x36,0xd5,0x01,0xff,0x03,0x02]
 
 v_fmac_f16 v5.h, v255.h, v2.h
-// GFX12: v_fmac_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1,1] ; encoding: [0x05,0x58,0x36,0xd5,0xff,0x05,0x02,0x02]
+// GFX12: v_fmac_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,0,1] ; encoding: [0x05,0x58,0x36,0xd5,0xff,0x05,0x02,0x02]
 
 v_fmac_f16 v5.l, v1.l, v255.l
 // GFX12: v_fmac_f16_e64 v5.l, v1.l, v255.l       ; encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
index 52cdd11e3a788..0ecae65751447 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
@@ -630,7 +630,7 @@ v_fmac_f16_e64 v5.l, v255.l, v255.h
 // GFX12: v_fmac_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x36,0xd5,0xff,0xff,0x03,0x02]
 
 v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2
-// GFX12: v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1,1] clamp div:2 ; encoding: [0xff,0xc3,0x36,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
+// GFX12: v_fmac_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x36,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
 
 v_fmac_f32_e64 v5, v1, v2
 // GFX12: v_fmac_f32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x02]

``````````

</details>


https://github.com/llvm/llvm-project/pull/206033
