[llvm] [AMDGPU] Fix overlapping insert crash during rewrite-agpr-copy-mfma (PR #205962)
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Thu Jun 25 20:01:53 PDT 2026
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<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Dhruva Chakrabarti (dhruvachak)
<details>
<summary>Changes</summary>
Fixes https://github.com/llvm/llvm-project/issues/204224
Guard against a possibly wrong interference result for a discontiguous stack slot interval by using the entire range.
A spilled stack slot can have a discontiguous live interval, e.g. a single value live across several disjoint segments:
[a, b) [c, d) ........gap........ [e, f)
with gaps where the slot is dead. The interference check previously only considered the covered segments, so it could pick a PhysReg that is free within them but busy inside a gap. Unspilling replaces the slot with a vreg whose recomputed interval is continuous over [a, f) (it fills the gaps), so assigning that PhysReg could overlap the value live in the gap and trip the "Overlapping insert" assertion in LiveRegMatrix::assign. Checking interference over the whole [a, f) hull avoids this.
Assisted-by: Cursor/Claude Opus
---
Patch is 41.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/205962.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp (+14-1)
- (added) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir (+734)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index 1d39b4f1bc52d..31c41d5ed40eb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -536,8 +536,21 @@ void AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() const {
ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
+ // The stack slot's LiveInterval may be discontiguous: a slot can be live
+ // in memory around a spill store and around a much later reload. Once
+ // we unspill the slot into a register, however, the value must reside in
+ // that register continuously from its first reference to its last. Checking
+ // interference against the slot's discontiguous interval could let us pick
+ // a PhysReg that is busy inside a gap, corrupting it. Instead, check
+ // interference over the range the replacement register will occupy.
+ LiveInterval HullLI(LI->reg(), LI->weight());
+ VNInfo *HullVNI =
+ HullLI.getNextValue(LI->beginIndex(), LIS.getVNInfoAllocator());
+ HullLI.addSegment(
+ LiveInterval::Segment(LI->beginIndex(), LI->endIndex(), HullVNI));
+
for (MCPhysReg PhysReg : AllocOrder) {
- if (LRM.checkInterference(*LI, PhysReg) != LiveRegMatrix::IK_Free)
+ if (LRM.checkInterference(HullLI, PhysReg) != LiveRegMatrix::IK_Free)
continue;
LLVM_DEBUG(dbgs() << "Reassigning " << *LI << " to "
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir
new file mode 100644
index 0000000000000..59b50aab4846e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir
@@ -0,0 +1,734 @@
+# REQUIRES: asserts
+# RUN: llc -mtriple=amdgcn -mcpu=gfx950 \
+# RUN: -start-before=register-coalescer \
+# RUN: -stop-after=amdgpu-rewrite-agpr-copy-mfma \
+# RUN: -verify-machineinstrs -filetype=null %s
+
+# A spill slot is stored once and reloaded far away, so the slot's LiveStacks
+# interval is discontiguous, but the unspilled replacement vreg would have to
+# live continuously across the gap. The interference check accounts for that
+# whole span, so the slot cannot be reassigned to an interfering register and is
+# left spilled. Previously the check only considered the discontiguous slot
+# interval, picked an interfering register, and LiveRegMatrix::assign hit an
+# "Overlapping insert" assertion. This test just checks that we no longer crash.
+
+--- |
+ define amdgpu_kernel void @spill_slot_discontiguous_interval(i1 %0, <16 x float> %1, <16 x float> %2, <16 x float> %3, <8 x bfloat> %4) #0 {
+ ret void
+ }
+
+ attributes #0 = { "amdgpu-wave-limiter"="true" "target-cpu"="gfx950" }
+...
+---
+name: spill_slot_discontiguous_interval
+tracksRegLiveness: true
+noPhis: true
+isSSA: false
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.3(0x40000000)
+ liveins: $sgpr4_sgpr5
+
+ %0:sgpr_64 = COPY killed $sgpr4_sgpr5
+ %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 36, 0 :: (dereferenceable invariant load (s32))
+ S_BITCMP1_B32 killed %1, 0, implicit-def $scc
+ %2:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc
+ early-clobber %3:sgpr_512 = S_LOAD_DWORDX16_IMM_ec %0, 164, 0 :: (dereferenceable invariant load (s512))
+ %4:vgpr_32 = V_MBCNT_HI_U32_B32_e64 0, 0, implicit $exec
+ %5:sgpr_32 = S_MOV_B32 0
+ undef %6.sub0:sgpr_128 = COPY %5
+ %6.sub1:sgpr_128 = COPY %5
+ %6.sub2:sgpr_128 = COPY %5
+ %6.sub3:sgpr_128 = COPY killed %5
+ %7:av_128_align2 = COPY killed %6
+ early-clobber %8:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_vgprcd_e64 %7, %7, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %9:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
+ undef %10.sub0:vreg_512_align2 = COPY %9
+ %10.sub1:vreg_512_align2 = COPY %9
+ %10.sub2:vreg_512_align2 = COPY %9
+ %10.sub3:vreg_512_align2 = COPY %9
+ %10.sub4:vreg_512_align2 = COPY %9
+ %10.sub5:vreg_512_align2 = COPY %9
+ %10.sub6:vreg_512_align2 = COPY %9
+ %10.sub7:vreg_512_align2 = COPY %9
+ %10.sub8:vreg_512_align2 = COPY %9
+ %10.sub9:vreg_512_align2 = COPY %9
+ %10.sub10:vreg_512_align2 = COPY %9
+ %10.sub11:vreg_512_align2 = COPY %9
+ %10.sub12:vreg_512_align2 = COPY %9
+ %10.sub13:vreg_512_align2 = COPY %9
+ %10.sub14:vreg_512_align2 = COPY %9
+ %10.sub15:vreg_512_align2 = COPY killed %9
+ %11:vreg_512_align2 = COPY killed %10
+ %11:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64 killed %7, %7, %11, 0, 0, 0, implicit $mode, implicit $exec
+ %12:av_512_align2 = COPY %11
+ %13:vreg_64_align2 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
+ %14:vgpr_32 = FLAT_LOAD_DWORD killed %13, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from `ptr null`)
+ %15:sreg_64 = V_CMP_NE_U32_e64 0, %14, implicit $exec
+ %16:av_32 = IMPLICIT_DEF
+ %17:av_32 = IMPLICIT_DEF
+ %18:av_32 = IMPLICIT_DEF
+ %19:av_32 = IMPLICIT_DEF
+ %20:av_32 = IMPLICIT_DEF
+ %21:av_32 = IMPLICIT_DEF
+ %22:av_32 = IMPLICIT_DEF
+ %23:av_32 = IMPLICIT_DEF
+ %24:av_32 = IMPLICIT_DEF
+ %25:av_32 = IMPLICIT_DEF
+ %26:av_32 = IMPLICIT_DEF
+ %27:av_32 = IMPLICIT_DEF
+ %28:av_32 = IMPLICIT_DEF
+ %29:av_32 = IMPLICIT_DEF
+ %30:av_32 = IMPLICIT_DEF
+ %31:av_32 = IMPLICIT_DEF
+ %32:av_32 = IMPLICIT_DEF
+ %33:av_32 = IMPLICIT_DEF
+ %34:av_32 = IMPLICIT_DEF
+ %35:av_32 = IMPLICIT_DEF
+ %36:av_512_align2 = IMPLICIT_DEF
+ %37:vgpr_32 = COPY %4
+ %38:vreg_512_align2 = COPY %8
+ %39:sreg_64 = COPY $exec, implicit-def $exec
+ %40:sreg_64 = S_AND_B64 %39, killed %15, implicit-def dead $scc
+ %41:sreg_64 = S_XOR_B64 %40, %39, implicit-def dead $scc
+ $exec = S_MOV_B64_term killed %40
+ S_CBRANCH_EXECZ %bb.3, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x40000000), %bb.4(0x40000000)
+
+ %42:sreg_64 = V_CMP_EQ_U32_e64 0, killed %14, implicit $exec
+ %43:sreg_64 = COPY $exec, implicit-def $exec
+ %44:sreg_64 = S_AND_B64 %43, killed %42, implicit-def dead $scc
+ $exec = S_MOV_B64_term killed %44
+ S_CBRANCH_EXECZ %bb.4, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ successors: %bb.4(0x80000000)
+
+ S_BRANCH %bb.4
+
+ bb.3:
+ successors: %bb.9(0x40000000), %bb.12(0x40000000)
+
+ %45:sreg_64 = S_OR_SAVEEXEC_B64 killed %41, implicit-def $exec, implicit-def $scc, implicit $exec
+ %46:vreg_512_align2 = COPY killed %38
+ %47:vgpr_32 = COPY killed %37
+ %48:av_512_align2 = COPY killed %36
+ %49:av_32 = COPY killed %35
+ %50:av_32 = COPY killed %34
+ %51:av_32 = COPY killed %33
+ %52:av_32 = COPY killed %32
+ %53:av_32 = COPY killed %31
+ %54:av_32 = COPY killed %30
+ %55:av_32 = COPY killed %29
+ %56:av_32 = COPY killed %28
+ %57:av_32 = COPY killed %27
+ %58:av_32 = COPY killed %26
+ %59:av_32 = COPY killed %25
+ %60:av_32 = COPY killed %24
+ %61:av_32 = COPY killed %23
+ %62:av_32 = COPY killed %22
+ %63:av_32 = COPY killed %21
+ %64:av_32 = COPY killed %20
+ %65:av_32 = COPY killed %19
+ %66:av_32 = COPY killed %18
+ %67:av_32 = COPY killed %17
+ %68:av_32 = COPY killed %16
+ %69:vgpr_32 = COPY killed %49, implicit $exec
+ %70:vgpr_32 = COPY killed %50, implicit $exec
+ %71:vgpr_32 = COPY killed %51, implicit $exec
+ %72:vgpr_32 = COPY killed %52, implicit $exec
+ %73:vgpr_32 = COPY killed %53, implicit $exec
+ %74:vgpr_32 = COPY killed %54, implicit $exec
+ %75:vgpr_32 = COPY killed %55, implicit $exec
+ %76:vgpr_32 = COPY killed %56, implicit $exec
+ %77:vgpr_32 = COPY killed %57, implicit $exec
+ %78:vgpr_32 = COPY killed %58, implicit $exec
+ %79:vgpr_32 = COPY killed %59, implicit $exec
+ %80:vgpr_32 = COPY killed %60, implicit $exec
+ %81:vgpr_32 = COPY killed %61, implicit $exec
+ %82:vgpr_32 = COPY killed %62, implicit $exec
+ %83:vgpr_32 = COPY killed %63, implicit $exec
+ %84:vgpr_32 = COPY killed %64, implicit $exec
+ %85:vgpr_32 = COPY killed %65, implicit $exec
+ %86:vgpr_32 = COPY killed %66, implicit $exec
+ %87:vgpr_32 = COPY killed %67, implicit $exec
+ %88:vgpr_32 = COPY killed %68, implicit $exec
+ %89:vreg_512_align2 = COPY killed %48
+ %90:vgpr_32 = COPY killed %69
+ %91:vgpr_32 = COPY killed %70
+ %92:vgpr_32 = COPY killed %71
+ %93:vgpr_32 = COPY killed %72
+ %94:vgpr_32 = COPY killed %73
+ %95:vgpr_32 = COPY killed %74
+ %96:vgpr_32 = COPY killed %75
+ %97:vgpr_32 = COPY killed %76
+ %98:vgpr_32 = COPY killed %77
+ %99:vgpr_32 = COPY killed %78
+ %100:vgpr_32 = COPY killed %79
+ %101:vgpr_32 = COPY killed %80
+ %102:vgpr_32 = COPY killed %81
+ %103:vgpr_32 = COPY killed %82
+ %104:vgpr_32 = COPY killed %83
+ %105:vgpr_32 = COPY killed %84
+ %106:vgpr_32 = COPY killed %85
+ %107:vgpr_32 = COPY killed %86
+ %108:vgpr_32 = COPY killed %87
+ %109:vgpr_32 = COPY killed %88
+ %110:sreg_64 = S_AND_B64 $exec, %45, implicit-def $scc
+ $exec = S_XOR_B64_term $exec, %110, implicit-def $scc
+ S_CBRANCH_EXECZ %bb.12, implicit $exec
+ S_BRANCH %bb.9
+
+ bb.4:
+ successors: %bb.5(0x40000000), %bb.8(0x40000000)
+
+ $exec = S_OR_B64 $exec, killed %43, implicit-def $scc
+ early-clobber %111:sgpr_512 = S_LOAD_DWORDX16_IMM_ec %0, 228, 0 :: (dereferenceable invariant load (s512))
+ early-clobber %112:sgpr_128 = S_LOAD_DWORDX4_IMM_ec %0, 292, 0 :: (dereferenceable invariant load (s128))
+ undef %113.sub0:vreg_64_align2 = COPY %11.sub14
+ %113.sub1:vreg_64_align2 = COPY %11.sub15
+ %114:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %113, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %115.sub0:vreg_64_align2 = COPY %11.sub12
+ %115.sub1:vreg_64_align2 = COPY %11.sub13
+ %116:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %115, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %117.sub0:vreg_64_align2 = COPY %11.sub10
+ %117.sub1:vreg_64_align2 = COPY %11.sub11
+ %118:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %117, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %119.sub0:vreg_64_align2 = COPY %11.sub8
+ %119.sub1:vreg_64_align2 = COPY %11.sub9
+ %120:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %119, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %121.sub0:vreg_64_align2 = COPY %11.sub6
+ %121.sub1:vreg_64_align2 = COPY %11.sub7
+ %122:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %121, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %123.sub0:vreg_64_align2 = COPY %11.sub4
+ %123.sub1:vreg_64_align2 = COPY %11.sub5
+ %124:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %123, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %125.sub0:vreg_64_align2 = COPY %11.sub2
+ %125.sub1:vreg_64_align2 = COPY %11.sub3
+ %126:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %125, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %127:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %11.sub0_sub1, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %128.sub0:vreg_512_align2 = COPY %127.sub0
+ %128.sub1:vreg_512_align2 = COPY killed %127.sub1
+ %128.sub2:vreg_512_align2 = COPY %126.sub0
+ %128.sub3:vreg_512_align2 = COPY killed %126.sub1
+ %128.sub4:vreg_512_align2 = COPY %124.sub0
+ %128.sub5:vreg_512_align2 = COPY killed %124.sub1
+ %128.sub6:vreg_512_align2 = COPY %122.sub0
+ %128.sub7:vreg_512_align2 = COPY killed %122.sub1
+ %128.sub8:vreg_512_align2 = COPY %120.sub0
+ %128.sub9:vreg_512_align2 = COPY killed %120.sub1
+ %128.sub10:vreg_512_align2 = COPY %118.sub0
+ %128.sub11:vreg_512_align2 = COPY killed %118.sub1
+ %128.sub12:vreg_512_align2 = COPY %116.sub0
+ %128.sub13:vreg_512_align2 = COPY killed %116.sub1
+ %128.sub14:vreg_512_align2 = COPY %114.sub0
+ %128.sub15:vreg_512_align2 = COPY killed %114.sub1
+ undef %129.sub0:sgpr_64 = COPY %111.sub14
+ %129.sub1:sgpr_64 = COPY %111.sub15
+ %130:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %129, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %131.sub0:sgpr_64 = COPY %111.sub12
+ %131.sub1:sgpr_64 = COPY %111.sub13
+ %132:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %131, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %133.sub0:sgpr_64 = COPY %111.sub10
+ %133.sub1:sgpr_64 = COPY %111.sub11
+ %134:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %133, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %135.sub0:sgpr_64 = COPY %111.sub8
+ %135.sub1:sgpr_64 = COPY %111.sub9
+ %136:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %135, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %137.sub0:sgpr_64 = COPY %111.sub6
+ %137.sub1:sgpr_64 = COPY %111.sub7
+ %138:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %137, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %139.sub0:sgpr_64 = COPY %111.sub4
+ %139.sub1:sgpr_64 = COPY %111.sub5
+ %140:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %139, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %141.sub0:sgpr_64 = COPY %111.sub2
+ %141.sub1:sgpr_64 = COPY %111.sub3
+ %142:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %141, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %143:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %111.sub0_sub1, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %144.sub0:vreg_512_align2 = COPY %143.sub0
+ %144.sub1:vreg_512_align2 = COPY killed %143.sub1
+ %144.sub2:vreg_512_align2 = COPY %142.sub0
+ %144.sub3:vreg_512_align2 = COPY killed %142.sub1
+ %144.sub4:vreg_512_align2 = COPY %140.sub0
+ %144.sub5:vreg_512_align2 = COPY killed %140.sub1
+ %144.sub6:vreg_512_align2 = COPY %138.sub0
+ %144.sub7:vreg_512_align2 = COPY killed %138.sub1
+ %144.sub8:vreg_512_align2 = COPY %136.sub0
+ %144.sub9:vreg_512_align2 = COPY killed %136.sub1
+ %144.sub10:vreg_512_align2 = COPY %134.sub0
+ %144.sub11:vreg_512_align2 = COPY killed %134.sub1
+ %144.sub12:vreg_512_align2 = COPY %132.sub0
+ %144.sub13:vreg_512_align2 = COPY killed %132.sub1
+ %144.sub14:vreg_512_align2 = COPY %130.sub0
+ %144.sub15:vreg_512_align2 = COPY killed %130.sub1
+ %145:sreg_32 = S_MOV_B32 0
+ undef %146.sub0:sgpr_128 = COPY %145
+ %146.sub1:sgpr_128 = COPY %145
+ %146.sub2:sgpr_128 = COPY %145
+ %146.sub3:sgpr_128 = COPY killed %145
+ %147:av_128_align2 = COPY %146
+ %148:vreg_512_align2 = COPY killed %144
+ %148:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64 %147, %147, %148, 0, 0, 0, implicit $mode, implicit $exec
+ undef %149.sub0:vreg_64_align2 = COPY %8.sub14
+ %149.sub1:vreg_64_align2 = COPY %8.sub15
+ %150:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %149, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %151.sub0:vreg_64_align2 = COPY %8.sub12
+ %151.sub1:vreg_64_align2 = COPY %8.sub13
+ %152:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %151, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %153.sub0:vreg_64_align2 = COPY %8.sub10
+ %153.sub1:vreg_64_align2 = COPY %8.sub11
+ %154:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %153, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %155.sub0:vreg_64_align2 = COPY %8.sub8
+ %155.sub1:vreg_64_align2 = COPY %8.sub9
+ %156:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %155, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %157.sub0:vreg_64_align2 = COPY %8.sub6
+ %157.sub1:vreg_64_align2 = COPY %8.sub7
+ %158:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %157, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %159.sub0:vreg_64_align2 = COPY %8.sub4
+ %159.sub1:vreg_64_align2 = COPY %8.sub5
+ %160:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %159, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %161.sub0:vreg_64_align2 = COPY %8.sub2
+ %161.sub1:vreg_64_align2 = COPY %8.sub3
+ %162:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %161, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %163:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, killed %8.sub0_sub1, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ undef %164.sub0:vreg_512_align2 = COPY %163.sub0
+ %164.sub1:vreg_512_align2 = COPY killed %163.sub1
+ %164.sub2:vreg_512_align2 = COPY %162.sub0
+ %164.sub3:vreg_512_align2 = COPY killed %162.sub1
+ %164.sub4:vreg_512_align2 = COPY %160.sub0
+ %164.sub5:vreg_512_align2 = COPY killed %160.sub1
+ %164.sub6:vreg_512_align2 = COPY %158.sub0
+ %164.sub7:vreg_512_align2 = COPY killed %158.sub1
+ %164.sub8:vreg_512_align2 = COPY %156.sub0
+ %164.sub9:vreg_512_align2 = COPY killed %156.sub1
+ %164.sub10:vreg_512_align2 = COPY %154.sub0
+ %164.sub11:vreg_512_align2 = COPY killed %154.sub1
+ %164.sub12:vreg_512_align2 = COPY %152.sub0
+ %164.sub13:vreg_512_align2 = COPY killed %152.sub1
+ %164.sub14:vreg_512_align2 = COPY %150.sub0
+ %164.sub15:vreg_512_align2 = COPY killed %150.sub1
+ %165:vreg_512_align2 = COPY killed %164
+ %165:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64 %147, %147, %165, 0, 0, 0, implicit $mode, implicit $exec
+ %166:vreg_512_align2 = COPY killed %128
+ %166:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64 %147, %147, %166, 0, 0, 0, implicit $mode, implicit $exec
+ %167:av_128_align2 = COPY killed %112
+ %168:vreg_512_align2 = COPY %3
+ early-clobber %169:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_vgprcd_e64 %147, killed %167, %168, 0, 0, 0, implicit $mode, implicit $exec
+ early-clobber %170:vreg_512_align2 = V_MFMA_F32_32X32X16_BF16_vgprcd_e64 killed %147, %147, killed %168, 0, 0, 0, implicit $mode, implicit $exec
+ %171:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2, implicit $exec
+ %172:sreg_64_xexec = V_CMP_NE_U32_e64 1, killed %171, implicit $exec
+ $vcc = S_AND_B64 $exec, %172, implicit-def dead $scc
+ S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
+ S_BRANCH %bb.5
+
+ bb.5:
+ successors: %bb.6(0x40000000), %bb.7(0x40000000)
+
+ %173:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ %174:vgpr_32 = COPY killed %4
+ INLINEASM &"\0A v_mov_b32 $4, 0xc61c4000\0A v_cmp_lt_i32_e64 $2, $6, $5\0A v_cmp_lt_i32_e64 $3, $9, $8\0A v_cndmask_b32_e64 $0, $4, $7, $2\0A v_cndmask_b32_e64 $1, $4, $10, $3\0A ", sideeffect attdialect, regdef:VGPR_32, def dead %175:vgpr_32, regdef:VGPR_32, def dead %176:vgpr_32, regdef-ec:SGPR_64, def dead early-clobber %177:sgpr_64, regdef-ec:SGPR_64, def dead early-clobber %178:sgpr_64, regdef-ec:VGPR_32, def dead early-clobber %179:vgpr_32, reguse:VGPR_32, %173, imm, 0, reguse:VGPR_32, %173, reguse:VGPR_32, killed %174, imm, 0, reguse:VGPR_32, %173, clobber, implicit-def dead early-clobber $vcc
+ $vcc = S_AND_B64 $exec, killed %172, implicit-def dead $scc
+ S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
+ S_BRANCH %bb.6
+
+ bb.6:
+ successors: %bb.7(0x80000000)
+
+ %180:vgpr_32 = COPY killed %170.sub0
+ INLINEASM &"\0A v_mov_b32 $4, 0xc61c4000\0A v_cmp_lt_i32_e64 $2, $6, $5\0A v_cmp_lt_i32_e64 $3, $9, $8\0A v_cndmask_b32_e64 $0, $4, $7, $2\0A v_cndmask_b32_e64 $1, $4, $10, $3\0A ", sideeffect attdialect, regdef:VGPR_32, def dead %181:vgpr_32, regdef:VGPR_32, def dead %182:vgpr_32, regdef-ec:SGPR_64, def dead early-clobber %183:sgpr_64, regdef-ec:SGPR_64, def dead early-clobber %184:sgpr_64, regdef-ec:VGPR_32, def dead early-clobber %185:vgpr_32, reguse:VGPR_32, killed %173, imm, 0...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205962
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