[llvm] [RISCV] Add assembler support to lower `la/lla` to `qc.e.li` (PR #205782)

[via llvm-commits]

https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/205782

>From f163b03b20819f9c80d8485f11257928a41f951d Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 25 Jun 2026 15:25:52 +0530
Subject: [PATCH 1/2] [RISCV] Add assembler support to lower la/lla to qc.e.li

Change-Id: I62738d4157bb7566e8283c6a22d5c168eeed15f2
---
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  9 +++-
 llvm/test/MC/RISCV/xqcili-load-address.s      | 41 +++++++++++++++++++
 2 files changed, 48 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-load-address.s

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9362a600b12b3..345e649171de0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3646,8 +3646,13 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
   //             ADDI rdest, rdest, %pcrel_lo(TmpLabel)
   MCRegister DestReg = Inst.getOperand(0).getReg();
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
-  emitAuipcInstPair(DestReg, DestReg, Symbol, RISCV::S_PCREL_HI, RISCV::ADDI,
-                    IDLoc, Out);
+  if (STI->hasFeature(RISCV::Feature32Bit) &&
+      STI->hasFeature(RISCV::FeatureVendorXqcili)) {
+    emitToStreamer(
+        Out, MCInstBuilder(RISCV::QC_E_LI).addReg(DestReg).addExpr(Symbol));
+  } else
+    emitAuipcInstPair(DestReg, DestReg, Symbol, RISCV::S_PCREL_HI, RISCV::ADDI,
+                      IDLoc, Out);
 }
 
 void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
diff --git a/llvm/test/MC/RISCV/xqcili-load-address.s b/llvm/test/MC/RISCV/xqcili-load-address.s
new file mode 100644
index 0000000000000..33aa3c1a796cc
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcili-load-address.s
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple=riscv32 -mattr=+xqcili %s \
+# RUN:     | FileCheck -check-prefix=ASM %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+xqcili %s \
+# RUN:     -filetype=obj -o - \
+# RUN:     | llvm-objdump --no-addresses -dr --mattr=+xqcili - \
+# RUN:     | FileCheck -check-prefix=OBJ %s
+
+## This test checks that we are lowering la/lla to qc.e.li correctly
+
+lla x6, abs_sym
+// ASM: qc.e.li	t1, abs_sym
+// OBJ: 031f 0000 0000        	qc.e.li	t1, 0x0
+// OBJ-NEXT: R_RISCV_VENDOR	QUALCOMM
+// OBJ-NEXT: R_RISCV_QC_E_32	abs_sym
+
+lla x6, same_section
+// ASM: qc.e.li	t1, same_section
+// OBJ: 031f 0000 0000        	qc.e.li	t1, 0x0
+// OBJ-NEXT: R_RISCV_VENDOR	QUALCOMM
+// OBJ-NEXT: R_RISCV_QC_E_32	same_section
+
+.option nopic
+// ASM: .option	nopic
+
+la x6, same_section
+// ASM: qc.e.li	t1, same_section
+// OBJ: 031f 0000 0000        	qc.e.li	t1, 0x0
+// OBJ-NEXT: R_RISCV_VENDOR	QUALCOMM
+// OBJ-NEXT: R_RISCV_QC_E_32	same_section
+
+la x6, abs_sym
+// ASM: qc.e.li	t1, abs_sym
+// OBJ: 031f 0000 0000        	qc.e.li	t1, 0x0
+// OBJ-NEXT: R_RISCV_VENDOR	QUALCOMM
+// OBJ-NEXT: R_RISCV_QC_E_32	abs_sym
+
+same_section:
+// ASM: same_section:
+nop
+// ASM: nop
+// OBJ: 0001                  	nop

>From b6b3fabe21f5ec0dd07c205a7ee778132c3cf43b Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Fri, 26 Jun 2026 07:33:42 +0530
Subject: [PATCH 2/2] fixup! drop if braces

Change-Id: I6316ca53c71e0fbb6583bc4d7b73316fa488cf60
---
 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 345e649171de0..7298a4db866d5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3647,10 +3647,10 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
   MCRegister DestReg = Inst.getOperand(0).getReg();
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   if (STI->hasFeature(RISCV::Feature32Bit) &&
-      STI->hasFeature(RISCV::FeatureVendorXqcili)) {
+      STI->hasFeature(RISCV::FeatureVendorXqcili))
     emitToStreamer(
         Out, MCInstBuilder(RISCV::QC_E_LI).addReg(DestReg).addExpr(Symbol));
-  } else
+  else
     emitAuipcInstPair(DestReg, DestReg, Symbol, RISCV::S_PCREL_HI, RISCV::ADDI,
                       IDLoc, Out);
 }