[llvm] ff066c7 - [IR] Don't match icmp+select as min/max (#205595)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 25 08:14:05 PDT 2026
Author: Alexis Engelke
Date: 2026-06-25T17:13:59+02:00
New Revision: ff066c745de9f00b0bac8a98d1bd9bd864034da0
URL: https://github.com/llvm/llvm-project/commit/ff066c745de9f00b0bac8a98d1bd9bd864034da0
DIFF: https://github.com/llvm/llvm-project/commit/ff066c745de9f00b0bac8a98d1bd9bd864034da0.diff
LOG: [IR] Don't match icmp+select as min/max (#205595)
Since some time, we canonicalize integer min/max as intrinsics. Remove
the detection of icmp+select as min/max from the pattern matchers. These
matchers were quite expensive but, due to canonicalization, were almost
never hit.
Test updates are largely canonicalization of the input to use intrinics
instead of icmp+select. (Manual work, we unfortunately don't have a tool
to canonicalize the test input.)
Added:
Modified:
llvm/include/llvm/IR/PatternMatch.h
llvm/include/llvm/Transforms/Scalar/NaryReassociate.h
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/lib/Transforms/Scalar/NaryReassociate.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/CodeGen/X86/vec_minmax_match.ll
llvm/test/Transforms/InstSimplify/maxmin.ll
llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
llvm/test/Transforms/LoopVectorize/minmax-extra-outside-users.ll
llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
llvm/test/Transforms/LoopVectorize/select-reduction.ll
llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
llvm/test/Transforms/NaryReassociate/nary-req.ll
llvm/test/Transforms/NaryReassociate/nary-smax.ll
llvm/test/Transforms/NaryReassociate/nary-smin.ll
llvm/test/Transforms/NaryReassociate/nary-umax.ll
llvm/test/Transforms/NaryReassociate/nary-umin.ll
llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h
index 4ff324deeb026..1b19175156261 100644
--- a/llvm/include/llvm/IR/PatternMatch.h
+++ b/llvm/include/llvm/IR/PatternMatch.h
@@ -2447,37 +2447,25 @@ m_Br(const Cond_t &C, const TrueBlock_t &T, const FalseBlock_t &F) {
}
//===----------------------------------------------------------------------===//
-// Matchers for max/min idioms, eg: "select (sgt x, y), x, y" -> smax(x,y).
+// Matchers for fmax/fmin idioms, eg: "select (sgt x, y), x, y" -> smax(x,y).
//
-template <typename CmpInst_t, typename LHS_t, typename RHS_t, typename Pred_t,
- bool Commutable = false>
-struct MaxMin_match {
+template <typename LHS_t, typename RHS_t, typename Pred_t>
+struct FMaxMin_match {
using PredType = Pred_t;
LHS_t L;
RHS_t R;
// The evaluation order is always stable, regardless of Commutability.
// The LHS is always matched first.
- MaxMin_match(const LHS_t &LHS, const RHS_t &RHS) : L(LHS), R(RHS) {}
+ FMaxMin_match(const LHS_t &LHS, const RHS_t &RHS) : L(LHS), R(RHS) {}
template <typename OpTy> bool match(OpTy *V) const {
- if (auto *II = dyn_cast<IntrinsicInst>(V)) {
- Intrinsic::ID IID = II->getIntrinsicID();
- if ((IID == Intrinsic::smax && Pred_t::match(ICmpInst::ICMP_SGT)) ||
- (IID == Intrinsic::smin && Pred_t::match(ICmpInst::ICMP_SLT)) ||
- (IID == Intrinsic::umax && Pred_t::match(ICmpInst::ICMP_UGT)) ||
- (IID == Intrinsic::umin && Pred_t::match(ICmpInst::ICMP_ULT))) {
- Value *LHS = II->getOperand(0), *RHS = II->getOperand(1);
- return (L.match(LHS) && R.match(RHS)) ||
- (Commutable && L.match(RHS) && R.match(LHS));
- }
- }
// Look for "(x pred y) ? x : y" or "(x pred y) ? y : x".
auto *SI = dyn_cast<SelectInst>(V);
if (!SI)
return false;
- auto *Cmp = dyn_cast<CmpInst_t>(SI->getCondition());
+ auto *Cmp = dyn_cast<FCmpInst>(SI->getCondition());
if (!Cmp)
return false;
// At this point we have a select conditioned on a comparison. Check that
@@ -2489,42 +2477,13 @@ struct MaxMin_match {
if ((TrueVal != LHS || FalseVal != RHS) &&
(TrueVal != RHS || FalseVal != LHS))
return false;
- typename CmpInst_t::Predicate Pred =
+ FCmpInst::Predicate Pred =
LHS == TrueVal ? Cmp->getPredicate() : Cmp->getInversePredicate();
// Does "(x pred y) ? x : y" represent the desired max/min operation?
if (!Pred_t::match(Pred))
return false;
// It does! Bind the operands.
- return (L.match(LHS) && R.match(RHS)) ||
- (Commutable && L.match(RHS) && R.match(LHS));
- }
-};
-
-/// Helper class for identifying signed max predicates.
-struct smax_pred_ty {
- static bool match(ICmpInst::Predicate Pred) {
- return Pred == CmpInst::ICMP_SGT || Pred == CmpInst::ICMP_SGE;
- }
-};
-
-/// Helper class for identifying signed min predicates.
-struct smin_pred_ty {
- static bool match(ICmpInst::Predicate Pred) {
- return Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_SLE;
- }
-};
-
-/// Helper class for identifying unsigned max predicates.
-struct umax_pred_ty {
- static bool match(ICmpInst::Predicate Pred) {
- return Pred == CmpInst::ICMP_UGT || Pred == CmpInst::ICMP_UGE;
- }
-};
-
-/// Helper class for identifying unsigned min predicates.
-struct umin_pred_ty {
- static bool match(ICmpInst::Predicate Pred) {
- return Pred == CmpInst::ICMP_ULT || Pred == CmpInst::ICMP_ULE;
+ return L.match(LHS) && R.match(RHS);
}
};
@@ -2556,35 +2515,6 @@ struct ufmin_pred_ty {
}
};
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, smax_pred_ty> m_SMax(const LHS &L,
- const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, smax_pred_ty>(L, R);
-}
-
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, smin_pred_ty> m_SMin(const LHS &L,
- const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, smin_pred_ty>(L, R);
-}
-
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, umax_pred_ty> m_UMax(const LHS &L,
- const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, umax_pred_ty>(L, R);
-}
-
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, umin_pred_ty> m_UMin(const LHS &L,
- const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, umin_pred_ty>(L, R);
-}
-
-template <typename LHS, typename RHS>
-inline auto m_MaxOrMin(const LHS &L, const RHS &R) {
- return m_CombineOr(m_SMax(L, R), m_SMin(L, R), m_UMax(L, R), m_UMin(L, R));
-}
-
/// Match an 'ordered' floating point maximum function.
/// Floating point has one special value 'NaN'. Therefore, there is no total
/// order. However, if we can ignore the 'NaN' value (for example, because of a
@@ -2595,9 +2525,9 @@ inline auto m_MaxOrMin(const LHS &L, const RHS &R) {
/// max(L, R) iff L and R are not NaN
/// m_OrdFMax(L, R) = R iff L or R are NaN
template <typename LHS, typename RHS>
-inline MaxMin_match<FCmpInst, LHS, RHS, ofmax_pred_ty> m_OrdFMax(const LHS &L,
- const RHS &R) {
- return MaxMin_match<FCmpInst, LHS, RHS, ofmax_pred_ty>(L, R);
+inline FMaxMin_match<LHS, RHS, ofmax_pred_ty> m_OrdFMax(const LHS &L,
+ const RHS &R) {
+ return FMaxMin_match<LHS, RHS, ofmax_pred_ty>(L, R);
}
/// Match an 'ordered' floating point minimum function.
@@ -2610,9 +2540,9 @@ inline MaxMin_match<FCmpInst, LHS, RHS, ofmax_pred_ty> m_OrdFMax(const LHS &L,
/// min(L, R) iff L and R are not NaN
/// m_OrdFMin(L, R) = R iff L or R are NaN
template <typename LHS, typename RHS>
-inline MaxMin_match<FCmpInst, LHS, RHS, ofmin_pred_ty> m_OrdFMin(const LHS &L,
- const RHS &R) {
- return MaxMin_match<FCmpInst, LHS, RHS, ofmin_pred_ty>(L, R);
+inline FMaxMin_match<LHS, RHS, ofmin_pred_ty> m_OrdFMin(const LHS &L,
+ const RHS &R) {
+ return FMaxMin_match<LHS, RHS, ofmin_pred_ty>(L, R);
}
/// Match an 'unordered' floating point maximum function.
@@ -2625,9 +2555,9 @@ inline MaxMin_match<FCmpInst, LHS, RHS, ofmin_pred_ty> m_OrdFMin(const LHS &L,
/// max(L, R) iff L and R are not NaN
/// m_UnordFMax(L, R) = L iff L or R are NaN
template <typename LHS, typename RHS>
-inline MaxMin_match<FCmpInst, LHS, RHS, ufmax_pred_ty>
-m_UnordFMax(const LHS &L, const RHS &R) {
- return MaxMin_match<FCmpInst, LHS, RHS, ufmax_pred_ty>(L, R);
+inline FMaxMin_match<LHS, RHS, ufmax_pred_ty> m_UnordFMax(const LHS &L,
+ const RHS &R) {
+ return FMaxMin_match<LHS, RHS, ufmax_pred_ty>(L, R);
}
/// Match an 'unordered' floating point minimum function.
@@ -2640,9 +2570,9 @@ m_UnordFMax(const LHS &L, const RHS &R) {
/// min(L, R) iff L and R are not NaN
/// m_UnordFMin(L, R) = L iff L or R are NaN
template <typename LHS, typename RHS>
-inline MaxMin_match<FCmpInst, LHS, RHS, ufmin_pred_ty>
-m_UnordFMin(const LHS &L, const RHS &R) {
- return MaxMin_match<FCmpInst, LHS, RHS, ufmin_pred_ty>(L, R);
+inline FMaxMin_match<LHS, RHS, ufmin_pred_ty> m_UnordFMin(const LHS &L,
+ const RHS &R) {
+ return FMaxMin_match<LHS, RHS, ufmin_pred_ty>(L, R);
}
/// Match an 'ordered' or 'unordered' floating point maximum function.
@@ -2651,11 +2581,11 @@ m_UnordFMin(const LHS &L, const RHS &R) {
/// 'no-nans-float-math' flag) a combination of a fcmp and select has 'maximum'
/// semantics.
template <typename LHS, typename RHS>
-inline match_combine_or<MaxMin_match<FCmpInst, LHS, RHS, ofmax_pred_ty>,
- MaxMin_match<FCmpInst, LHS, RHS, ufmax_pred_ty>>
+inline match_combine_or<FMaxMin_match<LHS, RHS, ofmax_pred_ty>,
+ FMaxMin_match<LHS, RHS, ufmax_pred_ty>>
m_OrdOrUnordFMax(const LHS &L, const RHS &R) {
- return m_CombineOr(MaxMin_match<FCmpInst, LHS, RHS, ofmax_pred_ty>(L, R),
- MaxMin_match<FCmpInst, LHS, RHS, ufmax_pred_ty>(L, R));
+ return m_CombineOr(FMaxMin_match<LHS, RHS, ofmax_pred_ty>(L, R),
+ FMaxMin_match<LHS, RHS, ufmax_pred_ty>(L, R));
}
/// Match an 'ordered' or 'unordered' floating point minimum function.
@@ -2664,11 +2594,11 @@ m_OrdOrUnordFMax(const LHS &L, const RHS &R) {
/// 'no-nans-float-math' flag) a combination of a fcmp and select has 'minimum'
/// semantics.
template <typename LHS, typename RHS>
-inline match_combine_or<MaxMin_match<FCmpInst, LHS, RHS, ofmin_pred_ty>,
- MaxMin_match<FCmpInst, LHS, RHS, ufmin_pred_ty>>
+inline match_combine_or<FMaxMin_match<LHS, RHS, ofmin_pred_ty>,
+ FMaxMin_match<LHS, RHS, ufmin_pred_ty>>
m_OrdOrUnordFMin(const LHS &L, const RHS &R) {
- return m_CombineOr(MaxMin_match<FCmpInst, LHS, RHS, ofmin_pred_ty>(L, R),
- MaxMin_match<FCmpInst, LHS, RHS, ufmin_pred_ty>(L, R));
+ return m_CombineOr(FMaxMin_match<LHS, RHS, ofmin_pred_ty>(L, R),
+ FMaxMin_match<LHS, RHS, ufmin_pred_ty>(L, R));
}
/// Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
@@ -2962,6 +2892,32 @@ inline typename m_Intrinsic_Ty<Opnd0, Opnd1>::Ty m_Cttz(const Opnd0 &Op0,
return m_Intrinsic<Intrinsic::cttz>(Op0, Op1);
}
+template <typename Opnd0, typename Opnd1>
+inline auto m_SMax(const Opnd0 &Op0, const Opnd1 &Op1) {
+ return m_Intrinsic<Intrinsic::smax>(Op0, Op1);
+}
+
+template <typename Opnd0, typename Opnd1>
+inline auto m_SMin(const Opnd0 &Op0, const Opnd1 &Op1) {
+ return m_Intrinsic<Intrinsic::smin>(Op0, Op1);
+}
+
+template <typename Opnd0, typename Opnd1>
+inline auto m_UMax(const Opnd0 &Op0, const Opnd1 &Op1) {
+ return m_Intrinsic<Intrinsic::umax>(Op0, Op1);
+}
+
+template <typename Opnd0, typename Opnd1>
+inline auto m_UMin(const Opnd0 &Op0, const Opnd1 &Op1) {
+ return m_Intrinsic<Intrinsic::umin>(Op0, Op1);
+}
+
+template <typename Opnd0, typename Opnd1>
+inline auto m_MaxOrMin(const Opnd0 &Op0, const Opnd1 &Op1) {
+ return m_CombineOr(m_SMax(Op0, Op1), m_SMin(Op0, Op1), m_UMax(Op0, Op1),
+ m_UMin(Op0, Op1));
+}
+
template <typename Opnd0, typename Opnd1>
inline typename m_Intrinsic_Ty<Opnd0, Opnd1>::Ty m_FMinNum(const Opnd0 &Op0,
const Opnd1 &Op1) {
@@ -3128,37 +3084,6 @@ m_NSWNeg(const ValTy &V) {
return m_NSWSub(m_ZeroInt(), V);
}
-/// Matches an SMin with LHS and RHS in either order.
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, smin_pred_ty, true>
-m_c_SMin(const LHS &L, const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, smin_pred_ty, true>(L, R);
-}
-/// Matches an SMax with LHS and RHS in either order.
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, smax_pred_ty, true>
-m_c_SMax(const LHS &L, const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, smax_pred_ty, true>(L, R);
-}
-/// Matches a UMin with LHS and RHS in either order.
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, umin_pred_ty, true>
-m_c_UMin(const LHS &L, const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, umin_pred_ty, true>(L, R);
-}
-/// Matches a UMax with LHS and RHS in either order.
-template <typename LHS, typename RHS>
-inline MaxMin_match<ICmpInst, LHS, RHS, umax_pred_ty, true>
-m_c_UMax(const LHS &L, const RHS &R) {
- return MaxMin_match<ICmpInst, LHS, RHS, umax_pred_ty, true>(L, R);
-}
-
-template <typename LHS, typename RHS>
-inline auto m_c_MaxOrMin(const LHS &L, const RHS &R) {
- return m_CombineOr(m_c_SMax(L, R), m_c_SMin(L, R), m_c_UMax(L, R),
- m_c_UMin(L, R));
-}
-
template <Intrinsic::ID IntrID, typename LHS, typename RHS>
struct CommutativeBinaryIntrinsic_match {
LHS L;
@@ -3181,6 +3106,33 @@ m_c_Intrinsic(const T0 &Op0, const T1 &Op1) {
return CommutativeBinaryIntrinsic_match<IntrID, T0, T1>(Op0, Op1);
}
+/// Matches an SMin with LHS and RHS in either order.
+template <typename LHS, typename RHS>
+inline auto m_c_SMin(const LHS &L, const RHS &R) {
+ return m_c_Intrinsic<Intrinsic::smin>(L, R);
+}
+/// Matches an SMax with LHS and RHS in either order.
+template <typename LHS, typename RHS>
+inline auto m_c_SMax(const LHS &L, const RHS &R) {
+ return m_c_Intrinsic<Intrinsic::smax>(L, R);
+}
+/// Matches a UMin with LHS and RHS in either order.
+template <typename LHS, typename RHS>
+inline auto m_c_UMin(const LHS &L, const RHS &R) {
+ return m_c_Intrinsic<Intrinsic::umin>(L, R);
+}
+/// Matches a UMax with LHS and RHS in either order.
+template <typename LHS, typename RHS>
+inline auto m_c_UMax(const LHS &L, const RHS &R) {
+ return m_c_Intrinsic<Intrinsic::umax>(L, R);
+}
+
+template <typename LHS, typename RHS>
+inline auto m_c_MaxOrMin(const LHS &L, const RHS &R) {
+ return m_CombineOr(m_c_SMax(L, R), m_c_SMin(L, R), m_c_UMax(L, R),
+ m_c_UMin(L, R));
+}
+
/// Matches FAdd with LHS and RHS in either order.
template <typename LHS, typename RHS>
inline BinaryOp_match<LHS, RHS, Instruction::FAdd, true>
diff --git a/llvm/include/llvm/Transforms/Scalar/NaryReassociate.h b/llvm/include/llvm/Transforms/Scalar/NaryReassociate.h
index 7d0840f89c382..fa41ed1473c29 100644
--- a/llvm/include/llvm/Transforms/Scalar/NaryReassociate.h
+++ b/llvm/include/llvm/Transforms/Scalar/NaryReassociate.h
@@ -93,6 +93,7 @@ class DominatorTree;
class Function;
class GetElementPtrInst;
class Instruction;
+class IntrinsicInst;
class TargetLibraryInfo;
class TargetTransformInfo;
class Type;
@@ -156,17 +157,8 @@ class NaryReassociatePass : public OptionalPassInfoMixin<NaryReassociatePass> {
Instruction *findClosestMatchingDominator(SCEVUse CandidateExpr,
Instruction *Dominatee);
- // Try to match \p I as signed/unsigned Min/Max and reassociate it. \p
- // OrigSCEV is set if \I matches Min/Max regardless whether resassociation is
- // done or not. If reassociation was successful newly generated instruction is
- // returned, otherwise nullptr.
- template <typename PredT>
- Instruction *matchAndReassociateMinOrMax(Instruction *I, SCEVUse &OrigSCEV);
-
// Reassociate Min/Max.
- template <typename MaxMinT>
- Value *tryReassociateMinOrMax(Instruction *I, MaxMinT MaxMinMatch, Value *LHS,
- Value *RHS);
+ Value *tryReassociateMinOrMax(IntrinsicInst *I);
// GetElementPtrInst implicitly sign-extends an index if the index is shorter
// than the pointer size. This function returns whether Index is shorter than
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index af10ac712886a..d5ae2d3f2e0ad 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -273,16 +273,6 @@ static unsigned getSelectFoldableOperands(BinaryOperator *I) {
/// We have (select c, TI, FI), and we know that TI and FI have the same opcode.
Instruction *InstCombinerImpl::foldSelectOpOp(SelectInst &SI, Instruction *TI,
Instruction *FI) {
- // Don't break up min/max patterns. The hasOneUse checks below prevent that
- // for most cases, but vector min/max with bitcasts can be transformed. If the
- // one-use restrictions are eased for other patterns, we still don't want to
- // obfuscate min/max.
- if ((match(&SI, m_SMin(m_Value(), m_Value())) ||
- match(&SI, m_SMax(m_Value(), m_Value())) ||
- match(&SI, m_UMin(m_Value(), m_Value())) ||
- match(&SI, m_UMax(m_Value(), m_Value()))))
- return nullptr;
-
// If this is a cast from the same type, merge.
Value *Cond = SI.getCondition();
Type *CondTy = Cond->getType();
diff --git a/llvm/lib/Transforms/Scalar/NaryReassociate.cpp b/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
index 5bdbd3e8b47cb..d24440646f766 100644
--- a/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
@@ -270,28 +270,6 @@ bool NaryReassociatePass::doOneIteration(Function &F) {
return Changed;
}
-template <typename PredT>
-Instruction *
-NaryReassociatePass::matchAndReassociateMinOrMax(Instruction *I,
- SCEVUse &OrigSCEV) {
- Value *LHS = nullptr;
- Value *RHS = nullptr;
-
- auto MinMaxMatcher =
- MaxMin_match<ICmpInst, match_bind<Value>, match_bind<Value>, PredT>(
- m_Value(LHS), m_Value(RHS));
- if (match(I, MinMaxMatcher)) {
- OrigSCEV = SE->getSCEV(I);
- if (auto *NewMinMax = dyn_cast_or_null<Instruction>(
- tryReassociateMinOrMax(I, MinMaxMatcher, LHS, RHS)))
- return NewMinMax;
- if (auto *NewMinMax = dyn_cast_or_null<Instruction>(
- tryReassociateMinOrMax(I, MinMaxMatcher, RHS, LHS)))
- return NewMinMax;
- }
- return nullptr;
-}
-
Instruction *NaryReassociatePass::tryReassociate(Instruction *I,
SCEVUse &OrigSCEV) {
@@ -311,16 +289,11 @@ Instruction *NaryReassociatePass::tryReassociate(Instruction *I,
}
// Try to match signed/unsigned Min/Max.
- Instruction *ResI = nullptr;
- // TODO: Currently min/max reassociation is restricted to integer types only
- // due to use of SCEVExpander which my introduce incompatible forms of min/max
- // for pointer types.
- if (I->getType()->isIntegerTy())
- if ((ResI = matchAndReassociateMinOrMax<umin_pred_ty>(I, OrigSCEV)) ||
- (ResI = matchAndReassociateMinOrMax<smin_pred_ty>(I, OrigSCEV)) ||
- (ResI = matchAndReassociateMinOrMax<umax_pred_ty>(I, OrigSCEV)) ||
- (ResI = matchAndReassociateMinOrMax<smax_pred_ty>(I, OrigSCEV)))
- return ResI;
+ if (match(I, m_MaxOrMin(m_Value(), m_Value()))) {
+ OrigSCEV = SE->getSCEV(I);
+ return dyn_cast_or_null<Instruction>(
+ tryReassociateMinOrMax(cast<IntrinsicInst>(I)));
+ }
return nullptr;
}
@@ -583,35 +556,34 @@ NaryReassociatePass::findClosestMatchingDominator(SCEVUse CandidateExpr,
return nullptr;
}
-template <typename MaxMinT> static SCEVTypes convertToSCEVType(MaxMinT &MM) {
- if (std::is_same_v<smax_pred_ty, typename MaxMinT::PredType>)
+static SCEVTypes convertToSCEVType(Intrinsic::ID IntrinID) {
+ switch (IntrinID) {
+ case Intrinsic::smax:
return scSMaxExpr;
- else if (std::is_same_v<umax_pred_ty, typename MaxMinT::PredType>)
+ case Intrinsic::umax:
return scUMaxExpr;
- else if (std::is_same_v<smin_pred_ty, typename MaxMinT::PredType>)
+ case Intrinsic::smin:
return scSMinExpr;
- else if (std::is_same_v<umin_pred_ty, typename MaxMinT::PredType>)
+ case Intrinsic::umin:
return scUMinExpr;
-
- llvm_unreachable("Can't convert MinMax pattern to SCEV type");
- return scUnknown;
+ default:
+ llvm_unreachable("Can't convert MinMax pattern to SCEV type");
+ return scUnknown;
+ }
}
-// Parameters:
-// I - instruction matched by MaxMinMatch matcher
-// MaxMinMatch - min/max idiom matcher
-// LHS - first operand of I
-// RHS - second operand of I
-template <typename MaxMinT>
-Value *NaryReassociatePass::tryReassociateMinOrMax(Instruction *I,
- MaxMinT MaxMinMatch,
- Value *LHS, Value *RHS) {
- Value *A = nullptr, *B = nullptr;
- MaxMinT m_MaxMin(m_Value(A), m_Value(B));
-
- if (!match(LHS, m_MaxMin))
+Value *NaryReassociatePass::tryReassociateMinOrMax(IntrinsicInst *I) {
+ Value *LHS = I->getArgOperand(0);
+ Value *RHS = I->getArgOperand(1);
+ if (auto *RHSI = dyn_cast<IntrinsicInst>(RHS);
+ RHSI && RHSI->getIntrinsicID() == I->getIntrinsicID())
+ std::swap(LHS, RHS);
+ auto *LHSI = dyn_cast<IntrinsicInst>(LHS);
+ if (!LHSI || LHSI->getIntrinsicID() != I->getIntrinsicID())
return nullptr;
+ Value *A = LHSI->getArgOperand(0), *B = LHSI->getArgOperand(1);
+
if (LHS->hasNUsesOrMore(3) ||
// The optimization is profitable only if LHS can be removed in the end.
// In other words LHS should be used (directly or indirectly) by I only.
@@ -623,7 +595,7 @@ Value *NaryReassociatePass::tryReassociateMinOrMax(Instruction *I,
auto tryCombination = [&](Value *A, SCEVUse AExpr, Value *B, SCEVUse BExpr,
Value *C, SCEVUse CExpr) -> Value * {
SmallVector<SCEVUse, 2> Ops1{BExpr, AExpr};
- const SCEVTypes SCEVType = convertToSCEVType(m_MaxMin);
+ SCEVTypes SCEVType = convertToSCEVType(I->getIntrinsicID());
SCEVUse R1Expr = SE->getMinMaxExpr(SCEVType, Ops1);
Instruction *R1MinMax = findClosestMatchingDominator(R1Expr, I);
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index d3e491247f93f..4c787179712f0 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -28904,10 +28904,7 @@ class HorizontalReduction {
return RecurKind::FMaximum;
if (match(I, m_FMinimum(m_Value(), m_Value())))
return RecurKind::FMinimum;
- // This matches either cmp+select or intrinsics. SLP is expected to handle
- // either form.
- // TODO: If we are canonicalizing to intrinsics, we can remove several
- // special-case paths that deal with selects.
+ // TODO: remove several special-case paths that deal with selects.
if (match(I, m_SMax(m_Value(), m_Value())))
return RecurKind::SMax;
if (match(I, m_SMin(m_Value(), m_Value())))
diff --git a/llvm/test/CodeGen/X86/vec_minmax_match.ll b/llvm/test/CodeGen/X86/vec_minmax_match.ll
index 56a45fa9a4ff5..6f97937c95b39 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_match.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_match.ll
@@ -7,26 +7,26 @@
define <4 x i32> @smin_vec1(<4 x i32> %x) {
; CHECK-LABEL: smin_vec1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
- %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
- %cmp = icmp sgt <4 x i32> %x, zeroinitializer
- %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+ %1 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
+ %sel = xor <4 x i32> %1, splat (i32 -1)
ret <4 x i32> %sel
}
define <4 x i32> @smin_vec2(<4 x i32> %x) {
; CHECK-LABEL: smin_vec2:
; CHECK: # %bb.0:
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
- %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
- %cmp = icmp slt <4 x i32> %x, zeroinitializer
- %sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x
+ %1 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
+ %sel = xor <4 x i32> %1, splat (i32 -1)
ret <4 x i32> %sel
}
@@ -121,8 +121,7 @@ define <4 x i32> @umax_vec1(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp = icmp slt <4 x i32> %x, zeroinitializer
- %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %sel = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 2147483647))
ret <4 x i32> %sel
}
@@ -131,8 +130,7 @@ define <4 x i32> @umax_vec2(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
- %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x
+ %sel = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 -2147483648))
ret <4 x i32> %sel
}
@@ -141,8 +139,7 @@ define <4 x i32> @umin_vec1(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp = icmp slt <4 x i32> %x, zeroinitializer
- %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x
+ %sel = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> splat (i32 2147483647))
ret <4 x i32> %sel
}
@@ -151,8 +148,7 @@ define <4 x i32> @umin_vec2(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
- %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
+ %sel = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> splat (i32 -2147483648))
ret <4 x i32> %sel
}
@@ -164,13 +160,11 @@ define <4 x i32> @umin_vec2(<4 x i32> %x) {
define <4 x i32> @clamp_signed1(<4 x i32> %x) {
; CHECK-LABEL: clamp_signed1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp2 = icmp slt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
- %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
- %cmp1 = icmp slt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
- %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min
+ %1 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 15))
+ %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %1, <4 x i32> splat (i32 255))
ret <4 x i32> %r
}
@@ -182,10 +176,8 @@ define <4 x i32> @clamp_signed2(<4 x i32> %x) {
; CHECK-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp2 = icmp sgt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
- %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
- %cmp1 = icmp sgt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
- %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max
+ %max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 15))
+ %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %max, <4 x i32> splat (i32 255))
ret <4 x i32> %r
}
@@ -194,13 +186,11 @@ define <4 x i32> @clamp_signed2(<4 x i32> %x) {
define <4 x i32> @clamp_unsigned1(<4 x i32> %x) {
; CHECK-LABEL: clamp_unsigned1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp2 = icmp ult <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
- %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
- %cmp1 = icmp ult <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
- %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min
+ %1 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 15))
+ %r = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %1, <4 x i32> splat (i32 255))
ret <4 x i32> %r
}
@@ -212,37 +202,19 @@ define <4 x i32> @clamp_unsigned2(<4 x i32> %x) {
; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %cmp2 = icmp ugt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
- %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
- %cmp1 = icmp ugt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
- %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max
+ %max = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 15))
+ %r = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %max, <4 x i32> splat (i32 255))
ret <4 x i32> %r
}
define <4 x i32> @umin_not_ops(<4 x i32> %x) {
; CHECK-LABEL: umin_not_ops:
; CHECK: # %bb.0:
+; CHECK-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
- %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
- %cmp = icmp ugt <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
- %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>
+ %1 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> splat (i32 4))
+ %sel = xor <4 x i32> %1, splat (i32 -1)
ret <4 x i32> %sel
}
-
-define <4 x i32> @wrong_pred_for_smin_with_subnsw(<4 x i32> %x, <4 x i32> %y) {
-; CHECK-LABEL: wrong_pred_for_smin_with_subnsw:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2
-; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm1
-; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0
-; CHECK-NEXT: retq
- %sub = sub nsw <4 x i32> %x, %y
- %cmp = icmp ugt <4 x i32> %x, %y
- %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
- ret <4 x i32> %sel
-}
-
diff --git a/llvm/test/Transforms/InstSimplify/maxmin.ll b/llvm/test/Transforms/InstSimplify/maxmin.ll
index 048850796744d..9b8da488e3fbc 100644
--- a/llvm/test/Transforms/InstSimplify/maxmin.ll
+++ b/llvm/test/Transforms/InstSimplify/maxmin.ll
@@ -75,7 +75,10 @@ define i1 @max1(i32 %x, i32 %y) {
define i1 @max2(i32 %x, i32 %y) {
; CHECK-LABEL: @max2(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp sge i32 [[M]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sge i32 %x, %y
%m = select i1 %c, i32 %x, i32 %y
@@ -95,7 +98,10 @@ define i1 @max3(i32 %x, i32 %y) {
define i1 @max4(i32 %x, i32 %y) {
; CHECK-LABEL: @max4(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i32 [[M]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp uge i32 %x, %y
%m = select i1 %c, i32 %x, i32 %y
@@ -115,7 +121,10 @@ define i1 @max5(i32 %x, i32 %y) {
define i1 @max6(i32 %x, i32 %y) {
; CHECK-LABEL: @max6(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp sle i32 [[X]], [[M]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sge i32 %x, %y
%m = select i1 %c, i32 %x, i32 %y
@@ -135,7 +144,10 @@ define i1 @max7(i32 %x, i32 %y) {
define i1 @max8(i32 %x, i32 %y) {
; CHECK-LABEL: @max8(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i32 [[X]], [[M]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp uge i32 %x, %y
%m = select i1 %c, i32 %x, i32 %y
@@ -145,7 +157,10 @@ define i1 @max8(i32 %x, i32 %y) {
define i1 @min1(i32 %x, i32 %y) {
; CHECK-LABEL: @min1(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[M]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sgt i32 %x, %y
%m = select i1 %c, i32 %y, i32 %x
@@ -165,7 +180,10 @@ define i1 @min2(i32 %x, i32 %y) {
define i1 @min3(i32 %x, i32 %y) {
; CHECK-LABEL: @min3(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[M]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp ugt i32 %x, %y
%m = select i1 %c, i32 %y, i32 %x
@@ -185,7 +203,10 @@ define i1 @min4(i32 %x, i32 %y) {
define i1 @min5(i32 %x, i32 %y) {
; CHECK-LABEL: @min5(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X]], [[M]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sgt i32 %x, %y
%m = select i1 %c, i32 %y, i32 %x
@@ -205,7 +226,10 @@ define i1 @min6(i32 %x, i32 %y) {
define i1 @min7(i32 %x, i32 %y) {
; CHECK-LABEL: @min7(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[M:%.*]] = select i1 [[C]], i32 [[Y]], i32 [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[X]], [[M]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp ugt i32 %x, %y
%m = select i1 %c, i32 %y, i32 %x
@@ -225,7 +249,12 @@ define i1 @min8(i32 %x, i32 %y) {
define i1 @maxmin1(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin1(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp sge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[MAX]], [[MIN]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -237,7 +266,12 @@ define i1 @maxmin1(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin2(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin2(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp sge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[MIN]], [[MAX]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -249,7 +283,12 @@ define i1 @maxmin2(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin3(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin3(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp sge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp sle i32 [[MIN]], [[MAX]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -261,7 +300,12 @@ define i1 @maxmin3(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin4(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin4(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp sge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[MAX]], [[MIN]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -273,7 +317,12 @@ define i1 @maxmin4(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin5(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin5(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[MAX]], [[MIN]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -285,7 +334,12 @@ define i1 @maxmin5(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin6(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin6(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[MIN]], [[MAX]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -297,7 +351,12 @@ define i1 @maxmin6(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin7(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin7(
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[MIN]], [[MAX]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -309,7 +368,12 @@ define i1 @maxmin7(i32 %x, i32 %y, i32 %z) {
define i1 @maxmin8(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @maxmin8(
-; CHECK-NEXT: ret i1 false
+; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C1]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[MIN:%.*]] = select i1 [[C2]], i32 [[Z]], i32 [[X]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[MAX]], [[MIN]]
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, %y
%max = select i1 %c1, i32 %x, i32 %y
@@ -322,7 +386,9 @@ define i1 @maxmin8(i32 %x, i32 %y, i32 %z) {
define i1 @eqcmp1(i32 %x, i32 %y) {
; CHECK-LABEL: @eqcmp1(
; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[C]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[MAX]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sge i32 %x, %y
%max = select i1 %c, i32 %x, i32 %y
@@ -333,7 +399,9 @@ define i1 @eqcmp1(i32 %x, i32 %y) {
define i1 @eqcmp2(i32 %x, i32 %y) {
; CHECK-LABEL: @eqcmp2(
; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[C]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], [[MAX]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp sge i32 %x, %y
%max = select i1 %c, i32 %x, i32 %y
@@ -344,7 +412,9 @@ define i1 @eqcmp2(i32 %x, i32 %y) {
define i1 @eqcmp3(i32 %x, i32 %y) {
; CHECK-LABEL: @eqcmp3(
; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[C]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[MAX]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp uge i32 %x, %y
%max = select i1 %c, i32 %x, i32 %y
@@ -355,7 +425,9 @@ define i1 @eqcmp3(i32 %x, i32 %y) {
define i1 @eqcmp4(i32 %x, i32 %y) {
; CHECK-LABEL: @eqcmp4(
; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[C]]
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], [[MAX]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c = icmp uge i32 %x, %y
%max = select i1 %c, i32 %x, i32 %y
diff --git a/llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll b/llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
index 29067ff926347..3f89019e9c23f 100644
--- a/llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
+++ b/llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
@@ -241,8 +241,7 @@ define void @reduction_smin(ptr %A, i32 %init) {
; CHECK: [[FOR_J_SPLIT1]]:
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[A]], i32 0, i32 [[J]], i32 [[I]]
; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[IDX]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[SMIN_J]]
-; CHECK-NEXT: [[SMIN_J_NEXT]] = select i1 [[CMP]], i32 [[A]], i32 [[SMIN_J]]
+; CHECK-NEXT: [[SMIN_J_NEXT]] = call i32 @llvm.smin.i32(i32 [[A]], i32 [[SMIN_J]])
; CHECK-NEXT: [[J_INC:%.*]] = add i32 [[J]], 1
; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], 2
; CHECK-NEXT: br label %[[FOR_I_LATCH]]
@@ -271,8 +270,7 @@ for.j:
%smin.j = phi i32 [ %smin.i, %for.i.header ], [ %smin.j.next, %for.j ]
%idx = getelementptr inbounds [2 x [2 x i32]], ptr %A, i32 0, i32 %j, i32 %i
%a = load i32, ptr %idx, align 4
- %cmp = icmp slt i32 %a, %smin.j
- %smin.j.next = select i1 %cmp, i32 %a, i32 %smin.j
+ %smin.j.next = call i32 @llvm.smin(i32 %a, i32 %smin.j)
%j.inc = add i32 %j, 1
%cmp.j = icmp slt i32 %j.inc, 2
br i1 %cmp.j, label %for.j, label %for.i.latch
@@ -314,8 +312,7 @@ define void @reduction_smax(ptr %A, i32 %init) {
; CHECK: [[FOR_J_SPLIT1]]:
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[A]], i32 0, i32 [[J]], i32 [[I]]
; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[IDX]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], [[SMAX_J]]
-; CHECK-NEXT: [[SMAX_J_NEXT]] = select i1 [[CMP]], i32 [[A]], i32 [[SMAX_J]]
+; CHECK-NEXT: [[SMAX_J_NEXT]] = call i32 @llvm.smax.i32(i32 [[A]], i32 [[SMAX_J]])
; CHECK-NEXT: [[J_INC:%.*]] = add i32 [[J]], 1
; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], 2
; CHECK-NEXT: br label %[[FOR_I_LATCH]]
@@ -344,8 +341,7 @@ for.j:
%smax.j = phi i32 [ %smax.i, %for.i.header ], [ %smax.j.next, %for.j ]
%idx = getelementptr inbounds [2 x [2 x i32]], ptr %A, i32 0, i32 %j, i32 %i
%a = load i32, ptr %idx, align 4
- %cmp = icmp sgt i32 %a, %smax.j
- %smax.j.next = select i1 %cmp, i32 %a, i32 %smax.j
+ %smax.j.next = call i32 @llvm.smax(i32 %a, i32 %smax.j)
%j.inc = add i32 %j, 1
%cmp.j = icmp slt i32 %j.inc, 2
br i1 %cmp.j, label %for.j, label %for.i.latch
@@ -387,8 +383,7 @@ define void @reduction_umin(ptr %A, i32 %init) {
; CHECK: [[FOR_J_SPLIT1]]:
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[A]], i32 0, i32 [[J]], i32 [[I]]
; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[IDX]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[A]], [[UMIN_J]]
-; CHECK-NEXT: [[UMIN_J_NEXT]] = select i1 [[CMP]], i32 [[A]], i32 [[UMIN_J]]
+; CHECK-NEXT: [[UMIN_J_NEXT]] = call i32 @llvm.umin.i32(i32 [[A]], i32 [[UMIN_J]])
; CHECK-NEXT: [[J_INC:%.*]] = add i32 [[J]], 1
; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], 2
; CHECK-NEXT: br label %[[FOR_I_LATCH]]
@@ -417,8 +412,7 @@ for.j:
%umin.j = phi i32 [ %umin.i, %for.i.header ], [ %umin.j.next, %for.j ]
%idx = getelementptr inbounds [2 x [2 x i32]], ptr %A, i32 0, i32 %j, i32 %i
%a = load i32, ptr %idx, align 4
- %cmp = icmp ult i32 %a, %umin.j
- %umin.j.next = select i1 %cmp, i32 %a, i32 %umin.j
+ %umin.j.next = call i32 @llvm.umin(i32 %a, i32 %umin.j)
%j.inc = add i32 %j, 1
%cmp.j = icmp slt i32 %j.inc, 2
br i1 %cmp.j, label %for.j, label %for.i.latch
@@ -460,8 +454,7 @@ define void @reduction_umax(ptr %A) {
; CHECK: [[FOR_J_SPLIT1]]:
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[A]], i32 0, i32 [[J]], i32 [[I]]
; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[IDX]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A]], [[UMAX_J]]
-; CHECK-NEXT: [[UMAX_J_NEXT]] = select i1 [[CMP]], i32 [[A]], i32 [[UMAX_J]]
+; CHECK-NEXT: [[UMAX_J_NEXT]] = call i32 @llvm.umax.i32(i32 [[A]], i32 [[UMAX_J]])
; CHECK-NEXT: [[J_INC:%.*]] = add i32 [[J]], 1
; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], 2
; CHECK-NEXT: br label %[[FOR_I_LATCH]]
@@ -490,8 +483,7 @@ for.j:
%umax.j = phi i32 [ %umax.i, %for.i.header ], [ %umax.j.next, %for.j ]
%idx = getelementptr inbounds [2 x [2 x i32]], ptr %A, i32 0, i32 %j, i32 %i
%a = load i32, ptr %idx, align 4
- %cmp = icmp ugt i32 %a, %umax.j
- %umax.j.next = select i1 %cmp, i32 %a, i32 %umax.j
+ %umax.j.next = call i32 @llvm.umax(i32 %a, i32 %umax.j)
%j.inc = add i32 %j, 1
%cmp.j = icmp slt i32 %j.inc, 2
br i1 %cmp.j, label %for.j, label %for.i.latch
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
index 4b639b76ea4f8..e0f9131bb64c4 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
@@ -14,18 +14,15 @@ define i32 @test_smin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_1:%.*]] = phi i32 [ 2147483647, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN:%.*]] = phi i32 [ 2147483647, %[[ENTRY_NEW]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN:%.*]] = phi i32 [ 2147483647, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[MIN]], [[TMP2]]
-; CHECK-NEXT: [[RDX_NEXT]] = select i1 [[CMP]], i32 [[MIN]], i32 [[TMP2]]
+; CHECK-NEXT: [[RDX_NEXT:%.*]] = call i32 @llvm.smin.i32(i32 [[MIN]], i32 [[TMP2]])
; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_NEXT]]
+; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV_NEXT]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
-; CHECK-NEXT: [[CMP_1:%.*]] = icmp slt i32 [[MIN_1]], [[TMP3]]
-; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], i32 [[MIN_1]], i32 [[TMP3]]
+; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smin.i32(i32 [[RDX_NEXT]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
@@ -34,23 +31,21 @@ define i32 @test_smin_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[RES_PH:%.*]] = phi i32 [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_UNR:%.*]] = phi i32 [ [[RDX_NEXT_1]], %[[LOOP]] ]
-; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smin.i32(i32 [[RDX_NEXT]], i32 [[RDX_NEXT_1]])
; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]
; CHECK: [[LOOP_EPIL_PREHEADER]]:
; CHECK-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]
-; CHECK-NEXT: [[MIN_EPIL_INIT:%.*]] = phi i32 [ 2147483647, %[[ENTRY]] ], [ [[RDX_MINMAX]], %[[EXIT_UNR_LCSSA]] ]
+; CHECK-NEXT: [[MIN_EPIL_INIT:%.*]] = phi i32 [ 2147483647, %[[ENTRY]] ], [ [[MIN_UNR]], %[[EXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD2]])
; CHECK-NEXT: br label %[[LOOP_EPIL:.*]]
; CHECK: [[LOOP_EPIL]]:
-; CHECK-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_EPIL_INIT]]
+; CHECK-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV_EPIL_INIT]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[GEP_A_EPIL]], align 4
-; CHECK-NEXT: [[CMP_EPIL:%.*]] = icmp slt i32 [[MIN_EPIL_INIT]], [[TMP4]]
-; CHECK-NEXT: [[RDX_NEXT_EPIL:%.*]] = select i1 [[CMP_EPIL]], i32 [[MIN_EPIL_INIT]], i32 [[TMP4]]
+; CHECK-NEXT: [[RDX_NEXT_EPIL:%.*]] = call i32 @llvm.smin.i32(i32 [[MIN_EPIL_INIT]], i32 [[TMP4]])
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RDX_MINMAX]], %[[EXIT_UNR_LCSSA]] ], [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]
+; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES_PH]], %[[EXIT_UNR_LCSSA]] ], [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
@@ -59,10 +54,9 @@ entry:
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%min = phi i32 [ 2147483647, %entry ], [ %rdx.next, %loop ]
- %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
- %1 = load i32, ptr %gep.a, align 4
- %cmp = icmp slt i32 %min, %1
- %rdx.next = select i1 %cmp, i32 %min, i32 %1
+ %gep.a = getelementptr inbounds nuw [4 x i8], ptr %a, i64 %iv
+ %0 = load i32, ptr %gep.a, align 4
+ %rdx.next = call i32 @llvm.smin.i32(i32 %min, i32 %0)
%iv.next = add nuw nsw i64 %iv, 1
%ec = icmp eq i64 %iv.next, %n
br i1 %ec, label %exit, label %loop, !llvm.loop !0
@@ -85,18 +79,15 @@ define i32 @test_smax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[IV_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_1:%.*]] = phi i32 [ -2147483648, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ -2147483648, %[[ENTRY_NEW]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ -2147483648, %[[ENTRY_NEW]] ], [ [[RDX_NEXT_1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, %[[ENTRY_NEW]] ], [ [[NITER_NEXT_1:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[GEP_A]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[MAX]], [[TMP2]]
-; CHECK-NEXT: [[RDX_NEXT]] = select i1 [[CMP]], i32 [[MAX]], i32 [[TMP2]]
+; CHECK-NEXT: [[RDX_NEXT:%.*]] = call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[TMP2]])
; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_NEXT]]
+; CHECK-NEXT: [[GEP_A_1:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV_NEXT]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP_A_1]], align 4
-; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[MAX_1]], [[TMP3]]
-; CHECK-NEXT: [[RDX_NEXT_1]] = select i1 [[CMP_1]], i32 [[MAX_1]], i32 [[TMP3]]
+; CHECK-NEXT: [[RDX_NEXT_1]] = call i32 @llvm.smax.i32(i32 [[RDX_NEXT]], i32 [[TMP3]])
; CHECK-NEXT: [[IV_NEXT_1]] = add nuw nsw i64 [[IV]], 2
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
@@ -105,23 +96,21 @@ define i32 @test_smax_reduction(ptr %a, i64 %n) {
; CHECK-NEXT: [[RES_PH:%.*]] = phi i32 [ [[RDX_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[IV_UNR:%.*]] = phi i64 [ [[IV_NEXT_1]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_UNR:%.*]] = phi i32 [ [[RDX_NEXT_1]], %[[LOOP]] ]
-; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_NEXT]], i32 [[RDX_NEXT_1]])
; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[LOOP_EPIL_PREHEADER]], label %[[EXIT:.*]]
; CHECK: [[LOOP_EPIL_PREHEADER]]:
; CHECK-NEXT: [[IV_EPIL_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_UNR]], %[[EXIT_UNR_LCSSA]] ]
-; CHECK-NEXT: [[MAX_EPIL_INIT:%.*]] = phi i32 [ -2147483648, %[[ENTRY]] ], [ [[RDX_MINMAX]], %[[EXIT_UNR_LCSSA]] ]
+; CHECK-NEXT: [[MAX_EPIL_INIT:%.*]] = phi i32 [ -2147483648, %[[ENTRY]] ], [ [[MAX_UNR]], %[[EXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD2]])
; CHECK-NEXT: br label %[[LOOP_EPIL:.*]]
; CHECK: [[LOOP_EPIL]]:
-; CHECK-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_EPIL_INIT]]
+; CHECK-NEXT: [[GEP_A_EPIL:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 [[IV_EPIL_INIT]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[GEP_A_EPIL]], align 4
-; CHECK-NEXT: [[CMP_EPIL:%.*]] = icmp sgt i32 [[MAX_EPIL_INIT]], [[TMP4]]
-; CHECK-NEXT: [[RDX_NEXT_EPIL:%.*]] = select i1 [[CMP_EPIL]], i32 [[MAX_EPIL_INIT]], i32 [[TMP4]]
+; CHECK-NEXT: [[RDX_NEXT_EPIL:%.*]] = call i32 @llvm.smax.i32(i32 [[MAX_EPIL_INIT]], i32 [[TMP4]])
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RDX_MINMAX]], %[[EXIT_UNR_LCSSA]] ], [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]
+; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES_PH]], %[[EXIT_UNR_LCSSA]] ], [ [[RDX_NEXT_EPIL]], %[[LOOP_EPIL]] ]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
@@ -130,10 +119,9 @@ entry:
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%max = phi i32 [ -2147483648, %entry ], [ %rdx.next, %loop ]
- %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
- %1 = load i32, ptr %gep.a, align 4
- %cmp = icmp sgt i32 %max, %1
- %rdx.next = select i1 %cmp, i32 %max, i32 %1
+ %gep.a = getelementptr inbounds nuw [4 x i8], ptr %a, i64 %iv
+ %0 = load i32, ptr %gep.a, align 4
+ %rdx.next = call i32 @llvm.smax.i32(i32 %max, i32 %0)
%iv.next = add nuw nsw i64 %iv, 1
%ec = icmp eq i64 %iv.next, %n
br i1 %ec, label %exit, label %loop, !llvm.loop !0
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
index 8a0cfa74a3ee6..a72fdeb6f10fe 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
@@ -23,10 +23,8 @@ for.body:
%c.042 = phi i16 [ 0, %for.body.lr.ph ], [ %c.0., %for.body ]
%arrayidx = getelementptr inbounds i16, ptr %1, i64 %indvars.iv
%4 = load i16, ptr %arrayidx, align 2, !tbaa !7
- %cmp2 = icmp sgt i16 %c.042, %4
- %c.0. = select i1 %cmp2, i16 %c.042, i16 %4
- %cmp13 = icmp slt i16 %d.043, %4
- %.sink28 = select i1 %cmp13, i16 %d.043, i16 %4
+ %c.0. = call i16 @llvm.smax(i16 %c.042, i16 %4)
+ %.sink28 = call i16 @llvm.smin(i16 %d.043, i16 %4)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp = icmp slt i64 %indvars.iv.next, %3
br i1 %cmp, label %for.body, label %for.end
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
index 6adb5e5dd8a1f..5f43b71e1444c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
@@ -132,10 +132,8 @@ define i32 @smin(ptr nocapture %a, ptr nocapture readonly %b, i64 %n) {
; CHECK: vector.body:
; CHECK: %[[LOAD1:.*]] = load <vscale x 8 x i32>
; CHECK: %[[LOAD2:.*]] = load <vscale x 8 x i32>
-; CHECK: %[[ICMP1:.*]] = icmp slt <vscale x 8 x i32> %[[LOAD1]]
-; CHECK: %[[ICMP2:.*]] = icmp slt <vscale x 8 x i32> %[[LOAD2]]
-; CHECK: %[[SEL1:.*]] = select <vscale x 8 x i1> %[[ICMP1]], <vscale x 8 x i32> %[[LOAD1]]
-; CHECK: %[[SEL2:.*]] = select <vscale x 8 x i1> %[[ICMP2]], <vscale x 8 x i32> %[[LOAD2]]
+; CHECK: %[[SEL1:.*]] = call <vscale x 8 x i32> @llvm.smin
+; CHECK: %[[SEL2:.*]] = call <vscale x 8 x i32> @llvm.smin
; CHECK: middle.block:
; CHECK: %[[RDX:.*]] = call <vscale x 8 x i32> @llvm.smin.nxv8i32(<vscale x 8 x i32> %[[SEL1]], <vscale x 8 x i32> %[[SEL2]])
; CHECK-NEXT: call i32 @llvm.vector.reduce.smin.nxv8i32(<vscale x 8 x i32> %[[RDX]])
@@ -147,8 +145,7 @@ for.body:
%sum.010 = phi i32 [ 2, %entry ], [ %.sroa.speculated, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp slt i32 %0, %sum.010
- %.sroa.speculated = select i1 %cmp.i, i32 %0, i32 %sum.010
+ %.sroa.speculated = call i32 @llvm.smin(i32 %0, i32 %sum.010)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -165,10 +162,8 @@ define i32 @umax(ptr nocapture %a, ptr nocapture readonly %b, i64 %n) {
; CHECK: vector.body:
; CHECK: %[[LOAD1:.*]] = load <vscale x 8 x i32>
; CHECK: %[[LOAD2:.*]] = load <vscale x 8 x i32>
-; CHECK: %[[ICMP1:.*]] = icmp ugt <vscale x 8 x i32> %[[LOAD1]]
-; CHECK: %[[ICMP2:.*]] = icmp ugt <vscale x 8 x i32> %[[LOAD2]]
-; CHECK: %[[SEL1:.*]] = select <vscale x 8 x i1> %[[ICMP1]], <vscale x 8 x i32> %[[LOAD1]]
-; CHECK: %[[SEL2:.*]] = select <vscale x 8 x i1> %[[ICMP2]], <vscale x 8 x i32> %[[LOAD2]]
+; CHECK: %[[SEL1:.*]] = call <vscale x 8 x i32> @llvm.umax
+; CHECK: %[[SEL2:.*]] = call <vscale x 8 x i32> @llvm.umax
; CHECK: middle.block:
; CHECK: %[[RDX:.*]] = call <vscale x 8 x i32> @llvm.umax.nxv8i32(<vscale x 8 x i32> %[[SEL1]], <vscale x 8 x i32> %[[SEL2]])
; CHECK-NEXT: call i32 @llvm.vector.reduce.umax.nxv8i32(<vscale x 8 x i32> %[[RDX]])
@@ -180,8 +175,7 @@ for.body:
%sum.010 = phi i32 [ 2, %entry ], [ %.sroa.speculated, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ugt i32 %0, %sum.010
- %.sroa.speculated = select i1 %cmp.i, i32 %0, i32 %sum.010
+ %.sroa.speculated = call i32 @llvm.umax(i32 %0, i32 %sum.010)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
index a56524697a540..e564151015e63 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
@@ -393,8 +393,7 @@ define i32 @reduction_min(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP1]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
@@ -408,8 +407,7 @@ define i32 @reduction_min(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: [[RESULT_08:%.*]] = phi i32 [ [[V0:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INDVARS_IV]]
; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[RESULT_08]], [[L0]]
-; CHECK-NEXT: [[V0]] = select i1 [[C0]], i32 [[RESULT_08]], i32 [[L0]]
+; CHECK-NEXT: [[V0]] = call i32 @llvm.smin.i32(i32 [[RESULT_08]], i32 [[L0]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 257
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -425,8 +423,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp slt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.smin(i32 %result.08, i32 %l0)
%indvars.iv.next = add i32 %indvars.iv, 1
%exitcond = icmp eq i32 %indvars.iv.next, 257
br i1 %exitcond, label %for.end, label %for.body
@@ -447,8 +444,7 @@ define i32 @reduction_max(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP1]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -462,8 +458,7 @@ define i32 @reduction_max(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: [[RESULT_08:%.*]] = phi i32 [ [[V0:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INDVARS_IV]]
; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C0:%.*]] = icmp ugt i32 [[RESULT_08]], [[L0]]
-; CHECK-NEXT: [[V0]] = select i1 [[C0]], i32 [[RESULT_08]], i32 [[L0]]
+; CHECK-NEXT: [[V0]] = call i32 @llvm.umax.i32(i32 [[RESULT_08]], i32 [[L0]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 257
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -479,8 +474,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp ugt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.umax(i32 %result.08, i32 %l0)
%indvars.iv.next = add i32 %indvars.iv, 1
%exitcond = icmp eq i32 %indvars.iv.next, 257
br i1 %exitcond, label %for.end, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
index a314e4a2e82c2..4f91e3331bab1 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
@@ -500,8 +500,7 @@ define i32 @smin_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 2147483647), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -518,8 +517,7 @@ define i32 @smin_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.smin.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -539,8 +537,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 2147483647, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp slt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.smin(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -567,8 +564,7 @@ define i32 @smax_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -585,8 +581,7 @@ define i32 @smax_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.smax.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
@@ -606,8 +601,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ -2147483648, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp sgt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.smax(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -634,8 +628,7 @@ define i32 @umin_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -1), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -652,8 +645,7 @@ define i32 @umin_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.umin.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -673,8 +665,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 4294967295, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp ult i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.umin(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -701,8 +692,7 @@ define i32 @umax_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -719,8 +709,7 @@ define i32 @umax_i32(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.umax.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
@@ -740,8 +729,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp ugt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.umax(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
index 6185c152ddc22..1a8f3dd4f1e84 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
@@ -21,10 +21,8 @@ define arm_aapcs_vfpcc i32 @minmaxval4(ptr nocapture readonly %x, ptr nocapture
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[VEC_PHI1]]
-; CHECK-NEXT: [[TMP1]] = select <4 x i1> [[TMP7]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI1]]
-; CHECK-NEXT: [[TMP8:%.*]] = icmp slt <4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP2]] = select <4 x i1> [[TMP8]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI1]])
+; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -53,10 +51,8 @@ define arm_aapcs_vfpcc i32 @minmaxval4(ptr nocapture readonly %x, ptr nocapture
; CHECK-NEXT: [[MAX_027:%.*]] = phi i32 [ [[COND]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX2]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_029]]
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP6]], [[MAX_027]]
-; CHECK-NEXT: [[COND]] = select i1 [[CMP1]], i32 [[TMP6]], i32 [[MAX_027]]
-; CHECK-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], [[MIN_028]]
-; CHECK-NEXT: [[COND9]] = select i1 [[CMP4]], i32 [[TMP6]], i32 [[MIN_028]]
+; CHECK-NEXT: [[COND]] = call i32 @llvm.smax.i32(i32 [[TMP6]], i32 [[MAX_027]])
+; CHECK-NEXT: [[COND9]] = call i32 @llvm.smin.i32(i32 [[TMP6]], i32 [[MIN_028]])
; CHECK-NEXT: [[INC]] = add nuw i32 [[I_029]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -77,10 +73,8 @@ for.body:
%max.027 = phi i32 [ %cond, %for.body ], [ -2147483648, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.029
%0 = load i32, ptr %arrayidx, align 4
- %cmp1 = icmp sgt i32 %0, %max.027
- %cond = select i1 %cmp1, i32 %0, i32 %max.027
- %cmp4 = icmp slt i32 %0, %min.028
- %cond9 = select i1 %cmp4, i32 %0, i32 %min.028
+ %cond = call i32 @llvm.smax(i32 %0, i32 %max.027)
+ %cond9 = call i32 @llvm.smin(i32 %0, i32 %min.028)
%inc = add nuw i32 %i.029, 1
%exitcond.not = icmp eq i32 %inc, %N
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
index 384ecd5e11782..36058a5004003 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
@@ -579,8 +579,7 @@ define i32 @i32_smin_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 2147483647), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -597,8 +596,7 @@ define i32 @i32_smin_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.smin.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -618,8 +616,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 2147483647, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp slt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.smin(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -646,8 +643,7 @@ define i32 @i32_smax_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
@@ -664,8 +660,7 @@ define i32 @i32_smax_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.smax.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
@@ -685,8 +680,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ -2147483648, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp sgt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.smax(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -713,8 +707,7 @@ define i32 @i32_umin_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -1), [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
@@ -731,8 +724,7 @@ define i32 @i32_umin_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.umin.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
@@ -752,8 +744,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 4294967295, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp ult i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.umin(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
@@ -780,8 +771,7 @@ define i32 @i32_umax_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP4]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
@@ -798,8 +788,7 @@ define i32 @i32_umax_reduction(ptr nocapture readonly %x, i32 %n) #0 {
; CHECK-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X]], i32 [[I_08]]
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R_07]], [[TMP7]]
-; CHECK-NEXT: [[ADD]] = select i1 [[C]], i32 [[R_07]], i32 [[TMP7]]
+; CHECK-NEXT: [[ADD]] = call i32 @llvm.umax.i32(i32 [[R_07]], i32 [[TMP7]])
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
@@ -819,8 +808,7 @@ for.body:
%r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %x, i32 %i.08
%0 = load i32, ptr %arrayidx, align 4
- %c = icmp ugt i32 %r.07, %0
- %add = select i1 %c, i32 %r.07, i32 %0
+ %add = call i32 @llvm.umax(i32 %r.07, i32 %0)
%inc = add nuw nsw i32 %i.08, 1
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.cond.cleanup, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
index 88be959a70b3a..022f491eb8d04 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
@@ -213,8 +213,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; OUTLOOP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
; OUTLOOP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; OUTLOOP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; OUTLOOP-NEXT: [[TMP9:%.*]] = icmp slt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; OUTLOOP-NEXT: [[TMP10]] = select <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; OUTLOOP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; OUTLOOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; OUTLOOP-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; OUTLOOP-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -231,8 +230,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; OUTLOOP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMIN:%.*]], [[FOR_BODY]] ]
; OUTLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; OUTLOOP-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; OUTLOOP-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[TMP13]], [[RDX]]
-; OUTLOOP-NEXT: [[SMIN]] = select i1 [[CMP_I]], i32 [[TMP13]], i32 [[RDX]]
+; OUTLOOP-NEXT: [[SMIN]] = call i32 @llvm.smin.i32(i32 [[TMP13]], i32 [[RDX]])
; OUTLOOP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; OUTLOOP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; OUTLOOP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -252,18 +250,20 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; INLOOP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 2
; INLOOP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; INLOOP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; INLOOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; INLOOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; INLOOP-NEXT: br label [[VECTOR_BODY:%.*]]
; INLOOP: vector.body:
; INLOOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; INLOOP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
; INLOOP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; INLOOP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; INLOOP-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
-; INLOOP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP9]], i32 [[VEC_PHI]])
+; INLOOP-NEXT: [[TMP5]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; INLOOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; INLOOP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; INLOOP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; INLOOP: middle.block:
+; INLOOP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[TMP5]])
; INLOOP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; INLOOP-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; INLOOP: scalar.ph:
@@ -275,8 +275,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; INLOOP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMIN:%.*]], [[FOR_BODY]] ]
; INLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; INLOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; INLOOP-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[TMP11]], [[RDX]]
-; INLOOP-NEXT: [[SMIN]] = select i1 [[CMP_I]], i32 [[TMP11]], i32 [[RDX]]
+; INLOOP-NEXT: [[SMIN]] = call i32 @llvm.smin.i32(i32 [[TMP11]], i32 [[RDX]])
; INLOOP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; INLOOP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; INLOOP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -298,8 +297,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-OUTLOOP-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-OUTLOOP-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-OUTLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-OUTLOOP-NEXT: [[TMP13:%.*]] = icmp slt <vscale x 4 x i32> [[VP_OP_LOAD]], [[VEC_PHI]]
-; IF-EVL-OUTLOOP-NEXT: [[TMP14:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; IF-EVL-OUTLOOP-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; IF-EVL-OUTLOOP-NEXT: [[TMP15]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-OUTLOOP-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-OUTLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
@@ -316,22 +314,25 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-INLOOP-NEXT: entry:
; IF-EVL-INLOOP-NEXT: br label [[VECTOR_PH:%.*]]
; IF-EVL-INLOOP: vector.ph:
+; IF-EVL-INLOOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; IF-EVL-INLOOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; IF-EVL-INLOOP-NEXT: br label [[VECTOR_BODY:%.*]]
; IF-EVL-INLOOP: vector.body:
; IF-EVL-INLOOP-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
-; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-INLOOP-NEXT: [[AVL:%.*]] = phi i64 [ [[N:%.*]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-INLOOP-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-INLOOP-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-INLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = call i32 @llvm.vp.reduce.smin.nxv4i32(i32 2147483647, <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-INLOOP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP13]], i32 [[VEC_PHI]])
+; IF-EVL-INLOOP-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
+; IF-EVL-INLOOP-NEXT: [[TMP3]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-INLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP14]], [[EVL_BASED_IV]]
; IF-EVL-INLOOP-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP14]]
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; IF-EVL-INLOOP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; IF-EVL-INLOOP: middle.block:
+; IF-EVL-INLOOP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[TMP3]])
; IF-EVL-INLOOP-NEXT: br label [[FOR_BODY:%.*]]
; IF-EVL-INLOOP: for.end:
; IF-EVL-INLOOP-NEXT: ret i32 [[RDX_MINMAX]]
@@ -403,8 +404,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %smin, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp slt i32 %0, %rdx
- %smin = select i1 %cmp.i, i32 %0, i32 %rdx
+ %smin = call i32 @llvm.smin(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
index a09ffdeb25691..b8a6f625f6566 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
@@ -298,8 +298,7 @@ define i32 @smin(ptr nocapture %a, ptr nocapture readonly %b, i64 %n) {
; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP6]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP14]])
-; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP8:%.*]] = select <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; CHECK-NEXT: [[TMP9]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP14]])
; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP14]] to i64
; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP10]], [[INDEX]]
@@ -320,8 +319,7 @@ for.body:
%sum.010 = phi i32 [ 2, %entry ], [ %.sroa.speculated, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp slt i32 %0, %sum.010
- %.sroa.speculated = select i1 %cmp.i, i32 %0, i32 %sum.010
+ %.sroa.speculated = call i32 @llvm.smin(i32 %0, i32 %sum.010)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body
@@ -346,8 +344,7 @@ define i32 @umax(ptr nocapture %a, ptr nocapture readonly %b, i64 %n) {
; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP6]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP14]])
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP8:%.*]] = select <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; CHECK-NEXT: [[TMP9]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP14]])
; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP14]] to i64
; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP10]], [[INDEX]]
@@ -368,8 +365,7 @@ for.body:
%sum.010 = phi i32 [ 2, %entry ], [ %.sroa.speculated, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ugt i32 %0, %sum.010
- %.sroa.speculated = select i1 %cmp.i, i32 %0, i32 %sum.010
+ %.sroa.speculated = call i32 @llvm.umax(i32 %0, i32 %sum.010)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
index f057a94ed2967..1fad71f9f9e04 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
@@ -453,22 +453,25 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: entry:
; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]
; IF-EVL: vector.ph:
+; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]
; IF-EVL: vector.body:
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
-; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N:%.*]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call i32 @llvm.vp.reduce.smin.nxv4i32(i32 2147483647, <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP14]], i32 [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP3]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP11]])
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP8]], [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]
; IF-EVL-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; IF-EVL-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; IF-EVL: middle.block:
+; IF-EVL-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[TMP3]])
; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]
; IF-EVL: for.end:
; IF-EVL-NEXT: ret i32 [[RDX_MINMAX]]
@@ -483,18 +486,20 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]
; NO-VP: vector.body:
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
-; NO-VP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP9]], i32 [[VEC_PHI]])
+; NO-VP-NEXT: [[TMP4]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; NO-VP: middle.block:
+; NO-VP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> [[TMP4]])
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; NO-VP: scalar.ph:
@@ -506,8 +511,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMIN:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[TMP11]], [[RDX]]
-; NO-VP-NEXT: [[SMIN]] = select i1 [[CMP_I]], i32 [[TMP11]], i32 [[RDX]]
+; NO-VP-NEXT: [[SMIN]] = call i32 @llvm.smin.i32(i32 [[TMP11]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -523,8 +527,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %smin, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp slt i32 %0, %rdx
- %smin = select i1 %cmp.i, i32 %0, i32 %rdx
+ %smin = call i32 @llvm.smin(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -538,22 +541,25 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: entry:
; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]
; IF-EVL: vector.ph:
+; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]
; IF-EVL: vector.body:
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
-; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N:%.*]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call i32 @llvm.vp.reduce.smax.nxv4i32(i32 -2147483648, <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smax.i32(i32 [[TMP14]], i32 [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP3]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP11]])
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP8]], [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]
; IF-EVL-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; IF-EVL-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; IF-EVL: middle.block:
+; IF-EVL-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> [[TMP3]])
; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]
; IF-EVL: for.end:
; IF-EVL-NEXT: ret i32 [[RDX_MINMAX]]
@@ -568,18 +574,20 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]
; NO-VP: vector.body:
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
-; NO-VP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smax.i32(i32 [[TMP9]], i32 [[VEC_PHI]])
+; NO-VP-NEXT: [[TMP4]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; NO-VP: middle.block:
+; NO-VP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> [[TMP4]])
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; NO-VP: scalar.ph:
@@ -591,8 +599,7 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMAX:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[TMP11]], [[RDX]]
-; NO-VP-NEXT: [[SMAX]] = select i1 [[CMP_I]], i32 [[TMP11]], i32 [[RDX]]
+; NO-VP-NEXT: [[SMAX]] = call i32 @llvm.smax.i32(i32 [[TMP11]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -608,8 +615,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %smax, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp sgt i32 %0, %rdx
- %smax = select i1 %cmp.i, i32 %0, i32 %rdx
+ %smax = call i32 @llvm.smax(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -623,22 +629,25 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: entry:
; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]
; IF-EVL: vector.ph:
+; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]
; IF-EVL: vector.body:
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
-; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N:%.*]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call i32 @llvm.vp.reduce.umin.nxv4i32(i32 -1, <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umin.i32(i32 [[TMP14]], i32 [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP3]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP11]])
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP8]], [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]
; IF-EVL-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; IF-EVL-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; IF-EVL: middle.block:
+; IF-EVL-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> [[TMP3]])
; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]
; IF-EVL: for.end:
; IF-EVL-NEXT: ret i32 [[RDX_MINMAX]]
@@ -653,18 +662,20 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]
; NO-VP: vector.body:
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
-; NO-VP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umin.i32(i32 [[TMP9]], i32 [[VEC_PHI]])
+; NO-VP-NEXT: [[TMP4]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; NO-VP: middle.block:
+; NO-VP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> [[TMP4]])
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; NO-VP: scalar.ph:
@@ -676,8 +687,7 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[UMIN:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp ult i32 [[TMP11]], [[RDX]]
-; NO-VP-NEXT: [[UMIN]] = select i1 [[CMP_I]], i32 [[TMP11]], i32 [[RDX]]
+; NO-VP-NEXT: [[UMIN]] = call i32 @llvm.umin.i32(i32 [[TMP11]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -693,8 +703,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %umin, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ult i32 %0, %rdx
- %umin = select i1 %cmp.i, i32 %0, i32 %rdx
+ %umin = call i32 @llvm.umin(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -708,22 +717,25 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: entry:
; IF-EVL-NEXT: br label [[VECTOR_PH:%.*]]
; IF-EVL: vector.ph:
+; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]
; IF-EVL: vector.body:
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
-; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; IF-EVL-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ [[N:%.*]], [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ]
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call i32 @llvm.vp.reduce.umax.nxv4i32(i32 0, <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umax.i32(i32 [[TMP14]], i32 [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
+; IF-EVL-NEXT: [[TMP3]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP11]])
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP8]], [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]
; IF-EVL-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; IF-EVL-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; IF-EVL: middle.block:
+; IF-EVL-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> [[TMP3]])
; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]
; IF-EVL: for.end:
; IF-EVL-NEXT: ret i32 [[RDX_MINMAX]]
@@ -738,18 +750,20 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[START:%.*]], i64 0
+; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
; NO-VP-NEXT: br label [[VECTOR_BODY:%.*]]
; NO-VP: vector.body:
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START:%.*]], [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
-; NO-VP-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umax.i32(i32 [[TMP9]], i32 [[VEC_PHI]])
+; NO-VP-NEXT: [[TMP4]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; NO-VP: middle.block:
+; NO-VP-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> [[TMP4]])
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; NO-VP: scalar.ph:
@@ -761,8 +775,7 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[UMAX:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp ugt i32 [[TMP11]], [[RDX]]
-; NO-VP-NEXT: [[UMAX]] = select i1 [[CMP_I]], i32 [[TMP11]], i32 [[RDX]]
+; NO-VP-NEXT: [[UMAX]] = call i32 @llvm.umax.i32(i32 [[TMP11]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
@@ -778,8 +791,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %umax, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ugt i32 %0, %rdx
- %umax = select i1 %cmp.i, i32 %0, i32 %rdx
+ %umax = call i32 @llvm.umax(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
index 53b0e95395869..a918e4c61425d 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
@@ -473,8 +473,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-NEXT: [[TMP13:%.*]] = icmp slt <vscale x 4 x i32> [[VP_OP_LOAD]], [[VEC_PHI]]
-; IF-EVL-NEXT: [[TMP14:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
@@ -505,8 +504,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = icmp slt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; NO-VP-NEXT: [[TMP10]] = select <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; NO-VP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -523,8 +521,7 @@ define i32 @smin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMIN:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[TMP13]], [[RDX]]
-; NO-VP-NEXT: [[SMIN]] = select i1 [[CMP_I]], i32 [[TMP13]], i32 [[RDX]]
+; NO-VP-NEXT: [[SMIN]] = call i32 @llvm.smin.i32(i32 [[TMP13]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -540,8 +537,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %smin, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp slt i32 %0, %rdx
- %smin = select i1 %cmp.i, i32 %0, i32 %rdx
+ %smin = call i32 @llvm.smin.i32(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -565,8 +561,7 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-NEXT: [[TMP13:%.*]] = icmp sgt <vscale x 4 x i32> [[VP_OP_LOAD]], [[VEC_PHI]]
-; IF-EVL-NEXT: [[TMP14:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
@@ -597,8 +592,7 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = icmp sgt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; NO-VP-NEXT: [[TMP10]] = select <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; NO-VP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
@@ -615,8 +609,7 @@ define i32 @smax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[SMAX:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[TMP13]], [[RDX]]
-; NO-VP-NEXT: [[SMAX]] = select i1 [[CMP_I]], i32 [[TMP13]], i32 [[RDX]]
+; NO-VP-NEXT: [[SMAX]] = call i32 @llvm.smax.i32(i32 [[TMP13]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -632,8 +625,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %smax, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp sgt i32 %0, %rdx
- %smax = select i1 %cmp.i, i32 %0, i32 %rdx
+ %smax = call i32 @llvm.smax.i32(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -657,8 +649,7 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-NEXT: [[TMP13:%.*]] = icmp ult <vscale x 4 x i32> [[VP_OP_LOAD]], [[VEC_PHI]]
-; IF-EVL-NEXT: [[TMP14:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
@@ -689,8 +680,7 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = icmp ult <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; NO-VP-NEXT: [[TMP10]] = select <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; NO-VP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -707,8 +697,7 @@ define i32 @umin(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[UMIN:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp ult i32 [[TMP13]], [[RDX]]
-; NO-VP-NEXT: [[UMIN]] = select i1 [[CMP_I]], i32 [[TMP13]], i32 [[RDX]]
+; NO-VP-NEXT: [[UMIN]] = call i32 @llvm.umin.i32(i32 [[TMP13]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -724,8 +713,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %umin, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ult i32 %0, %rdx
- %umin = select i1 %cmp.i, i32 %0, i32 %rdx
+ %umin = call i32 @llvm.umin.i32(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
@@ -749,8 +737,7 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; IF-EVL-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP11]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
-; IF-EVL-NEXT: [[TMP13:%.*]] = icmp ugt <vscale x 4 x i32> [[VP_OP_LOAD]], [[VEC_PHI]]
-; IF-EVL-NEXT: [[TMP14:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x i32> @llvm.vp.merge.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[VEC_PHI]], i32 [[TMP9]])
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
@@ -781,8 +768,7 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ [[BROADCAST_SPLAT]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ]
; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDEX]]
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; NO-VP-NEXT: [[TMP9:%.*]] = icmp ugt <vscale x 4 x i32> [[WIDE_LOAD]], [[VEC_PHI]]
-; NO-VP-NEXT: [[TMP10]] = select <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
+; NO-VP-NEXT: [[TMP10]] = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]])
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; NO-VP-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; NO-VP-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
@@ -799,8 +785,7 @@ define i32 @umax(ptr %a, i64 %n, i32 %start) {
; NO-VP-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[UMAX:%.*]], [[FOR_BODY]] ]
; NO-VP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; NO-VP-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; NO-VP-NEXT: [[CMP_I:%.*]] = icmp ugt i32 [[TMP13]], [[RDX]]
-; NO-VP-NEXT: [[UMAX]] = select i1 [[CMP_I]], i32 [[TMP13]], i32 [[RDX]]
+; NO-VP-NEXT: [[UMAX]] = call i32 @llvm.umax.i32(i32 [[TMP13]], i32 [[RDX]])
; NO-VP-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
@@ -816,8 +801,7 @@ for.body:
%rdx = phi i32 [ %start, %entry ], [ %umax, %for.body ]
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp.i = icmp ugt i32 %0, %rdx
- %umax = select i1 %cmp.i, i32 %0, i32 %rdx
+ %umax = call i32 @llvm.umax.i32(i32 %0, i32 %rdx)
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
index 95a6601c4a2a2..beba6a437d880 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
@@ -1256,7 +1256,7 @@ define i32 @print_umax_reduction(ptr %y) {
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.umax (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umax(ir<%red>, ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1264,7 +1264,7 @@ define i32 @print_umax_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umax, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umax) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1283,8 +1283,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp ult i32 %lv, %red
- %red.next = select i1 %icmp, i32 %red, i32 %lv
+ %red.next = call i32 @llvm.umax(i32 %red, i32 %lv)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1316,7 +1315,7 @@ define i32 @print_umin_reduction(ptr %y) {
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.umin (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umin(ir<%lv>, ir<%red>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1324,7 +1323,7 @@ define i32 @print_umin_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umin, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umin) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1343,8 +1342,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp ult i32 %lv, %red
- %red.next = select i1 %icmp, i32 %lv, i32 %red
+ %red.next = call i32 @llvm.umin(i32 %lv, i32 %red)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1376,7 +1374,7 @@ define i32 @print_smax_reduction(ptr %y) {
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.smax (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.smax(ir<%red>, ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1384,7 +1382,7 @@ define i32 @print_smax_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smax, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smax) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1403,8 +1401,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp slt i32 %lv, %red
- %red.next = select i1 %icmp, i32 %red, i32 %lv
+ %red.next = call i32 @llvm.smax(i32 %red, i32 %lv)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1436,7 +1433,7 @@ define i32 @print_smin_reduction(ptr %y) {
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.smin (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.smin(ir<%lv>, ir<%red>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1444,7 +1441,7 @@ define i32 @print_smin_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smin, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smin) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1463,8 +1460,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp slt i32 %lv, %red
- %red.next = select i1 %icmp, i32 %lv, i32 %red
+ %red.next = call i32 @llvm.smin(i32 %lv, i32 %red)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
index e6bddd4d18a67..1aee414ec7ee1 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
@@ -26,7 +26,7 @@ define float @print_reduction(i64 %n, ptr noalias %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (fadd) fast vp<[[VP3]]>, ir<%red.next>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP6]]>
; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -100,7 +100,7 @@ define void @print_reduction_with_invariant_store(i64 %n, ptr noalias %y, ptr no
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (fadd) fast vp<[[VP3]]>, ir<%red.next>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP6]]>
; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -176,10 +176,10 @@ define float @print_fmuladd_strict(ptr %a, ptr %b, i64 %n) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%sum.07> = phi (fmuladd) nnan ninf nsz vp<[[VP3]]>, ir<%muladd>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%b>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2>, ir<1>
; CHECK-NEXT: WIDEN ir<%l.b> = load vp<[[VP7]]>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = fmul nnan ninf nsz ir<%l.a>, ir<%l.b>
; CHECK-NEXT: REDUCE ir<%muladd> = ir<%sum.07> + nnan ninf nsz reduce.fmuladd (vp<[[VP8]]>)
@@ -259,7 +259,7 @@ define i64 @find_last_iv(ptr %a, i64 %n, i64 %start) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (find-iv) ir<-9223372036854775808>, ir<%cond>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr inbounds ir<%a>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.a>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.a>, ir<1>
; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VP5]]>
; CHECK-NEXT: WIDEN ir<%cmp2> = icmp eq ir<%l.a>, ir<%start>
; CHECK-NEXT: WIDEN ir<%cond> = select ir<%cmp2>, ir<%iv>, ir<%rdx>
@@ -338,7 +338,7 @@ define i64 @print_extended_reduction(ptr nocapture readonly %x, ptr nocapture re
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.add (ir<%load0> zext to i64)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -415,10 +415,10 @@ define i64 @print_mulacc(ptr nocapture readonly %x, ptr nocapture readonly %y, i
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>, ir<1>
; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]>
; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.add (mul nsw ir<%load0>, ir<%load1>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -499,10 +499,10 @@ define i64 @print_mulacc_extended(ptr nocapture readonly %x, ptr nocapture reado
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>, ir<1>
; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]>
; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.add (mul nsw (ir<%load0> sext to i64), (ir<%load1> sext to i64))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -589,7 +589,7 @@ define i64 @print_extended_sub_reduction(ptr nocapture readonly %x, ptr nocaptur
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (sub) vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.sub (ir<%load0> zext to i64)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -666,10 +666,10 @@ define i32 @print_mulacc_sub(ptr %a, ptr %b) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi (sub) vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a>, ir<1>
; CHECK-NEXT: WIDEN ir<%load.a> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b>, ir<1>
; CHECK-NEXT: WIDEN ir<%load.b> = load vp<[[VP7]]>
; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%accum> + reduce.sub (mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -753,10 +753,10 @@ define i32 @print_mulacc_negated(ptr %a, ptr %b) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi (add) vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a>, ir<1>
; CHECK-NEXT: WIDEN ir<%load.a> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b>, ir<1>
; CHECK-NEXT: WIDEN ir<%load.b> = load vp<[[VP7]]>
; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%accum> + reduce.add (sub (0, mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32)))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -842,10 +842,10 @@ define i64 @print_mulacc_sub_extended(ptr nocapture readonly %x, ptr nocapture r
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (sub) vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1>, ir<1>
; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]>
; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.sub (mul nsw (ir<%load0> sext to i64), (ir<%load1> sext to i64))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -932,7 +932,7 @@ define i64 @print_mulacc_duplicate_extends(ptr nocapture readonly %x, ptr nocapt
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (sub) vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]>
-; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]>
; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.sub (mul nsw (ir<%load0> sext to i64), (ir<%load0> sext to i64))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
@@ -1015,7 +1015,7 @@ define i32 @print_mulacc_extended_const(ptr %start, ptr %end) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (add) vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
-; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]>
; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul (ir<%l> zext to i32), (ir<63> zext to i32))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]>
@@ -1093,7 +1093,7 @@ define i32 @print_mulacc_extended_const_lhs(ptr %start, ptr %end) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (add) vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
-; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]>
; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = zext ir<%l> to i32
; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul ir<63>, ir<%l.ext>)
@@ -1173,7 +1173,7 @@ define i32 @print_mulacc_not_extended_const(ptr %start, ptr %end) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (add) vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
-; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]>
; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i32
; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul ir<%l.ext>, ir<128>)
@@ -1253,7 +1253,7 @@ define i64 @print_ext_mulacc_extended_const(ptr %start, ptr %end) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (add) vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
-; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]>
; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul (ir<%l> zext to i64), (ir<63> zext to i64))
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]>
@@ -1334,7 +1334,7 @@ define i64 @print_ext_mulacc_not_extended_const(ptr %start, ptr %end) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (add) vp<[[VP5]]>, vp<[[VP10:%[0-9]+]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]>
-; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]>
; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i32
; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = shl ir<%l.ext>, ir<7>
@@ -1510,7 +1510,7 @@ define i32 @print_umax_reduction_out_of_loop(ptr %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (umax) ir<0>, ir<%red.next>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umax(ir<%lv>, ir<%red>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
@@ -1583,9 +1583,9 @@ define i32 @print_umax_reduction(ptr %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (umax) ir<0>, ir<%red.next>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.umax (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umax(ir<%red>, ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1593,7 +1593,7 @@ define i32 @print_umax_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umax, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umax) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1612,8 +1612,7 @@ define i32 @print_umax_reduction(ptr %y) {
; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds i32, ptr %y, i64 %iv
; CHECK-NEXT: IR %lv = load i32, ptr %gep, align 4
-; CHECK-NEXT: IR %icmp = icmp ult i32 %lv, %red
-; CHECK-NEXT: IR %red.next = select i1 %icmp, i32 %red, i32 %lv
+; CHECK-NEXT: IR %red.next = call i32 @llvm.umax.i32(i32 %red, i32 %lv)
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 100
; CHECK-NEXT: No successors
@@ -1627,8 +1626,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp ult i32 %lv, %red
- %red.next = select i1 %icmp, i32 %red, i32 %lv
+ %red.next = call i32 @llvm.umax(i32 %red, i32 %lv)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1658,9 +1656,9 @@ define i32 @print_umin_reduction(ptr %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (umin) ir<0>, ir<%red.next>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.umin (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umin(ir<%lv>, ir<%red>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1668,7 +1666,7 @@ define i32 @print_umin_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umin, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umin) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1687,8 +1685,7 @@ define i32 @print_umin_reduction(ptr %y) {
; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds i32, ptr %y, i64 %iv
; CHECK-NEXT: IR %lv = load i32, ptr %gep, align 4
-; CHECK-NEXT: IR %icmp = icmp ult i32 %lv, %red
-; CHECK-NEXT: IR %red.next = select i1 %icmp, i32 %lv, i32 %red
+; CHECK-NEXT: IR %red.next = call i32 @llvm.umin.i32(i32 %lv, i32 %red)
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 100
; CHECK-NEXT: No successors
@@ -1702,8 +1699,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp ult i32 %lv, %red
- %red.next = select i1 %icmp, i32 %lv, i32 %red
+ %red.next = call i32 @llvm.umin(i32 %lv, i32 %red)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1733,9 +1729,9 @@ define i32 @print_smax_reduction(ptr %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (smax) ir<0>, ir<%red.next>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.smax (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.smax(ir<%red>, ir<%lv>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1743,7 +1739,7 @@ define i32 @print_smax_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smax, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smax) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1762,8 +1758,7 @@ define i32 @print_smax_reduction(ptr %y) {
; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds i32, ptr %y, i64 %iv
; CHECK-NEXT: IR %lv = load i32, ptr %gep, align 4
-; CHECK-NEXT: IR %icmp = icmp slt i32 %lv, %red
-; CHECK-NEXT: IR %red.next = select i1 %icmp, i32 %red, i32 %lv
+; CHECK-NEXT: IR %red.next = call i32 @llvm.smax.i32(i32 %red, i32 %lv)
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 100
; CHECK-NEXT: No successors
@@ -1777,8 +1772,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp slt i32 %lv, %red
- %red.next = select i1 %icmp, i32 %red, i32 %lv
+ %red.next = call i32 @llvm.smax(i32 %red, i32 %lv)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
@@ -1808,9 +1802,9 @@ define i32 @print_smin_reduction(ptr %y) {
; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi (smin) ir<0>, ir<%red.next>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]>
-; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.smin (ir<%lv>)
+; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.smin(ir<%lv>, ir<%red>)
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -1818,7 +1812,7 @@ define i32 @print_smin_reduction(ptr %y) {
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smin, in-loop) ir<%red.next>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smin) ir<%red.next>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
@@ -1837,8 +1831,7 @@ define i32 @print_smin_reduction(ptr %y) {
; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds i32, ptr %y, i64 %iv
; CHECK-NEXT: IR %lv = load i32, ptr %gep, align 4
-; CHECK-NEXT: IR %icmp = icmp slt i32 %lv, %red
-; CHECK-NEXT: IR %red.next = select i1 %icmp, i32 %lv, i32 %red
+; CHECK-NEXT: IR %red.next = call i32 @llvm.smin.i32(i32 %lv, i32 %red)
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 100
; CHECK-NEXT: No successors
@@ -1852,8 +1845,7 @@ loop:
%red = phi i32 [ 0, %entry ], [ %red.next, %loop ]
%gep = getelementptr inbounds i32, ptr %y, i64 %iv
%lv = load i32, ptr %gep, align 4
- %icmp = icmp slt i32 %lv, %red
- %red.next = select i1 %icmp, i32 %lv, i32 %red
+ %red.next = call i32 @llvm.smin(i32 %lv, i32 %red)
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 100
br i1 %ec, label %exit, label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
index a79636c0f1eef..100afc7049ebc 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
@@ -242,14 +242,10 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; UNROLL-NO-IC-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> [[WIDE_LOAD2]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
; UNROLL-NO-IC-NEXT: [[TMP7:%.*]] = sub nsw <4 x i32> [[WIDE_LOAD]], [[TMP5]]
; UNROLL-NO-IC-NEXT: [[TMP8:%.*]] = sub nsw <4 x i32> [[WIDE_LOAD2]], [[TMP6]]
-; UNROLL-NO-IC-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i32> [[TMP7]], zeroinitializer
-; UNROLL-NO-IC-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i32> [[TMP8]], zeroinitializer
-; UNROLL-NO-IC-NEXT: [[TMP11:%.*]] = select <4 x i1> [[TMP9]], <4 x i32> [[TMP7]], <4 x i32> zeroinitializer
-; UNROLL-NO-IC-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP8]], <4 x i32> zeroinitializer
-; UNROLL-NO-IC-NEXT: [[TMP13:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[TMP11]]
-; UNROLL-NO-IC-NEXT: [[TMP14:%.*]] = icmp slt <4 x i32> [[VEC_PHI1]], [[TMP12]]
-; UNROLL-NO-IC-NEXT: [[TMP15]] = select <4 x i1> [[TMP13]], <4 x i32> [[VEC_PHI]], <4 x i32> [[TMP11]]
-; UNROLL-NO-IC-NEXT: [[TMP16]] = select <4 x i1> [[TMP14]], <4 x i32> [[VEC_PHI1]], <4 x i32> [[TMP12]]
+; UNROLL-NO-IC-NEXT: [[TMP9:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP7]], <4 x i32> zeroinitializer)
+; UNROLL-NO-IC-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP8]], <4 x i32> zeroinitializer)
+; UNROLL-NO-IC-NEXT: [[TMP15]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[TMP9]])
+; UNROLL-NO-IC-NEXT: [[TMP16]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI1]], <4 x i32> [[TMP10]])
; UNROLL-NO-IC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; UNROLL-NO-IC-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; UNROLL-NO-IC-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -277,10 +273,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; UNROLL-NO-IC-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
; UNROLL-NO-IC-NEXT: [[TMP20]] = load i32, ptr [[ARRAYIDX]], align 4
; UNROLL-NO-IC-NEXT: [[SUB3:%.*]] = sub nsw i32 [[TMP20]], [[TMP19]]
-; UNROLL-NO-IC-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB3]], 0
-; UNROLL-NO-IC-NEXT: [[COND:%.*]] = select i1 [[CMP4]], i32 [[SUB3]], i32 0
-; UNROLL-NO-IC-NEXT: [[CMP5:%.*]] = icmp slt i32 [[MINMAX_028]], [[COND]]
-; UNROLL-NO-IC-NEXT: [[MINMAX_0_COND]] = select i1 [[CMP5]], i32 [[MINMAX_028]], i32 [[COND]]
+; UNROLL-NO-IC-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB3]], i32 0)
+; UNROLL-NO-IC-NEXT: [[MINMAX_0_COND]] = call i32 @llvm.smin.i32(i32 [[MINMAX_028]], i32 [[COND]])
; UNROLL-NO-IC-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; UNROLL-NO-IC-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; UNROLL-NO-IC-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]]
@@ -313,14 +307,10 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; UNROLL-NO-VF-NEXT: [[TMP6]] = load i32, ptr [[TMP4]], align 4
; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = sub nsw i32 [[TMP5]], [[VECTOR_RECUR]]
; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = sub nsw i32 [[TMP6]], [[TMP5]]
-; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[TMP7]], 0
-; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = icmp sgt i32 [[TMP8]], 0
-; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = select i1 [[TMP9]], i32 [[TMP7]], i32 0
-; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 0
-; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp slt i32 [[VEC_PHI]], [[TMP11]]
-; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = icmp slt i32 [[VEC_PHI1]], [[TMP12]]
-; UNROLL-NO-VF-NEXT: [[TMP15]] = select i1 [[TMP13]], i32 [[VEC_PHI]], i32 [[TMP11]]
-; UNROLL-NO-VF-NEXT: [[TMP16]] = select i1 [[TMP14]], i32 [[VEC_PHI1]], i32 [[TMP12]]
+; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP7]], i32 0)
+; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP8]], i32 0)
+; UNROLL-NO-VF-NEXT: [[TMP15]] = call i32 @llvm.smin.i32(i32 [[VEC_PHI]], i32 [[TMP10]])
+; UNROLL-NO-VF-NEXT: [[TMP16]] = call i32 @llvm.smin.i32(i32 [[VEC_PHI1]], i32 [[TMP9]])
; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; UNROLL-NO-VF-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -346,10 +336,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; UNROLL-NO-VF-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
; UNROLL-NO-VF-NEXT: [[TMP19]] = load i32, ptr [[ARRAYIDX]], align 4
; UNROLL-NO-VF-NEXT: [[SUB3:%.*]] = sub nsw i32 [[TMP19]], [[TMP18]]
-; UNROLL-NO-VF-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB3]], 0
-; UNROLL-NO-VF-NEXT: [[COND:%.*]] = select i1 [[CMP4]], i32 [[SUB3]], i32 0
-; UNROLL-NO-VF-NEXT: [[CMP5:%.*]] = icmp slt i32 [[MINMAX_028]], [[COND]]
-; UNROLL-NO-VF-NEXT: [[MINMAX_0_COND]] = select i1 [[CMP5]], i32 [[MINMAX_028]], i32 [[COND]]
+; UNROLL-NO-VF-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB3]], i32 0)
+; UNROLL-NO-VF-NEXT: [[MINMAX_0_COND]] = call i32 @llvm.smin.i32(i32 [[MINMAX_028]], i32 [[COND]])
; UNROLL-NO-VF-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; UNROLL-NO-VF-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]]
@@ -379,10 +367,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; SINK-AFTER-NEXT: [[WIDE_LOAD]] = load <4 x i32>, ptr [[TMP2]], align 4
; SINK-AFTER-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[VECTOR_RECUR]], <4 x i32> [[WIDE_LOAD]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
; SINK-AFTER-NEXT: [[TMP5:%.*]] = sub nsw <4 x i32> [[WIDE_LOAD]], [[TMP4]]
-; SINK-AFTER-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[TMP5]], zeroinitializer
-; SINK-AFTER-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP5]], <4 x i32> zeroinitializer
-; SINK-AFTER-NEXT: [[TMP8:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[TMP7]]
-; SINK-AFTER-NEXT: [[TMP9]] = select <4 x i1> [[TMP8]], <4 x i32> [[VEC_PHI]], <4 x i32> [[TMP7]]
+; SINK-AFTER-NEXT: [[TMP6:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP5]], <4 x i32> zeroinitializer)
+; SINK-AFTER-NEXT: [[TMP9]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[TMP6]])
; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; SINK-AFTER-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; SINK-AFTER-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -409,10 +395,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; SINK-AFTER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
; SINK-AFTER-NEXT: [[TMP13]] = load i32, ptr [[ARRAYIDX]], align 4
; SINK-AFTER-NEXT: [[SUB3:%.*]] = sub nsw i32 [[TMP13]], [[TMP12]]
-; SINK-AFTER-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB3]], 0
-; SINK-AFTER-NEXT: [[COND:%.*]] = select i1 [[CMP4]], i32 [[SUB3]], i32 0
-; SINK-AFTER-NEXT: [[CMP5:%.*]] = icmp slt i32 [[MINMAX_028]], [[COND]]
-; SINK-AFTER-NEXT: [[MINMAX_0_COND]] = select i1 [[CMP5]], i32 [[MINMAX_028]], i32 [[COND]]
+; SINK-AFTER-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB3]], i32 0)
+; SINK-AFTER-NEXT: [[MINMAX_0_COND]] = call i32 @llvm.smin.i32(i32 [[MINMAX_028]], i32 [[COND]])
; SINK-AFTER-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; SINK-AFTER-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; SINK-AFTER-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]]
@@ -442,10 +426,8 @@ scalar.body:
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
%1 = load i32, ptr %arrayidx, align 4
%sub3 = sub nsw i32 %1, %0
- %cmp4 = icmp sgt i32 %sub3, 0
- %cond = select i1 %cmp4, i32 %sub3, i32 0
- %cmp5 = icmp slt i32 %minmax.028, %cond
- %minmax.0.cond = select i1 %cmp5, i32 %minmax.028, i32 %cond
+ %cond = call i32 @llvm.smax(i32 %sub3, i32 0)
+ %minmax.0.cond = call i32 @llvm.smin(i32 %minmax.028, i32 %cond)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, %n
@@ -3351,12 +3333,12 @@ define void @unused_recurrence(ptr %a, i16 %n) {
; UNROLL-NO-IC-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
; UNROLL-NO-IC-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; UNROLL-NO-IC: [[SCALAR_PH]]:
-; UNROLL-NO-IC-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
-; UNROLL-NO-IC-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i16 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; UNROLL-NO-IC-NEXT: [[TMP9:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
+; UNROLL-NO-IC-NEXT: [[TMP10:%.*]] = phi i16 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; UNROLL-NO-IC-NEXT: br label %[[FOR_COND:.*]]
; UNROLL-NO-IC: [[FOR_COND]]:
-; UNROLL-NO-IC-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
-; UNROLL-NO-IC-NEXT: [[REC_1:%.*]] = phi i16 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
+; UNROLL-NO-IC-NEXT: [[IV:%.*]] = phi i16 [ [[TMP9]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
+; UNROLL-NO-IC-NEXT: [[REC_1:%.*]] = phi i16 [ [[TMP10]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
; UNROLL-NO-IC-NEXT: [[USE_REC_1:%.*]] = sub i16 [[REC_1]], 10
; UNROLL-NO-IC-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
; UNROLL-NO-IC-NEXT: [[REC_1_PREV]] = add i16 [[IV_NEXT]], 5
@@ -3393,12 +3375,12 @@ define void @unused_recurrence(ptr %a, i16 %n) {
; UNROLL-NO-VF-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP6]], [[N_VEC]]
; UNROLL-NO-VF-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; UNROLL-NO-VF: [[SCALAR_PH]]:
-; UNROLL-NO-VF-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
-; UNROLL-NO-VF-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i16 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
+; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = phi i16 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; UNROLL-NO-VF-NEXT: br label %[[FOR_COND:.*]]
; UNROLL-NO-VF: [[FOR_COND]]:
-; UNROLL-NO-VF-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
-; UNROLL-NO-VF-NEXT: [[REC_1:%.*]] = phi i16 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
+; UNROLL-NO-VF-NEXT: [[IV:%.*]] = phi i16 [ [[TMP11]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
+; UNROLL-NO-VF-NEXT: [[REC_1:%.*]] = phi i16 [ [[TMP12]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
; UNROLL-NO-VF-NEXT: [[USE_REC_1:%.*]] = sub i16 [[REC_1]], 10
; UNROLL-NO-VF-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
; UNROLL-NO-VF-NEXT: [[REC_1_PREV]] = add i16 [[IV_NEXT]], 5
@@ -3435,12 +3417,12 @@ define void @unused_recurrence(ptr %a, i16 %n) {
; SINK-AFTER-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
; SINK-AFTER-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; SINK-AFTER: [[SCALAR_PH]]:
-; SINK-AFTER-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
-; SINK-AFTER-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i16 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; SINK-AFTER-NEXT: [[TMP9:%.*]] = phi i16 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ -27, %[[ENTRY]] ]
+; SINK-AFTER-NEXT: [[TMP10:%.*]] = phi i16 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; SINK-AFTER-NEXT: br label %[[FOR_COND:.*]]
; SINK-AFTER: [[FOR_COND]]:
-; SINK-AFTER-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
-; SINK-AFTER-NEXT: [[REC_1:%.*]] = phi i16 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
+; SINK-AFTER-NEXT: [[IV:%.*]] = phi i16 [ [[TMP9]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_COND]] ]
+; SINK-AFTER-NEXT: [[REC_1:%.*]] = phi i16 [ [[TMP10]], %[[SCALAR_PH]] ], [ [[REC_1_PREV:%.*]], %[[FOR_COND]] ]
; SINK-AFTER-NEXT: [[USE_REC_1:%.*]] = sub i16 [[REC_1]], 10
; SINK-AFTER-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
; SINK-AFTER-NEXT: [[REC_1_PREV]] = add i16 [[IV_NEXT]], 5
diff --git a/llvm/test/Transforms/LoopVectorize/minmax-extra-outside-users.ll b/llvm/test/Transforms/LoopVectorize/minmax-extra-outside-users.ll
index 1c58544bea456..55cace5738248 100644
--- a/llvm/test/Transforms/LoopVectorize/minmax-extra-outside-users.ll
+++ b/llvm/test/Transforms/LoopVectorize/minmax-extra-outside-users.ll
@@ -16,8 +16,7 @@ define i32 @smin_three_exit_users(ptr %src, i64 %n) {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 2147483647), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP2]] = select <4 x i1> [[TMP1]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -34,8 +33,7 @@ define i32 @smin_three_exit_users(ptr %src, i64 %n) {
; CHECK-NEXT: [[MIN:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[MIN]], [[V]]
-; CHECK-NEXT: [[MIN_NEXT]] = select i1 [[CMP]], i32 [[MIN]], i32 [[V]]
+; CHECK-NEXT: [[MIN_NEXT]] = call i32 @llvm.smin.i32(i32 [[MIN]], i32 [[V]])
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -55,8 +53,7 @@ loop:
%min = phi i32 [ 2147483647, %entry ], [ %min.next, %loop ]
%gep = getelementptr inbounds i32, ptr %src, i64 %iv
%v = load i32, ptr %gep, align 4
- %cmp = icmp slt i32 %min, %v
- %min.next = select i1 %cmp, i32 %min, i32 %v
+ %min.next = call i32 @llvm.smin(i32 %min, i32 %v)
%iv.next = add nuw nsw i64 %iv, 1
%ec = icmp eq i64 %iv.next, %n
br i1 %ec, label %exit, label %loop
@@ -85,8 +82,7 @@ define i32 @smax_three_exit_users(ptr %src, i64 %n) {
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP2]] = select <4 x i1> [[TMP1]], <4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP2]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -103,8 +99,7 @@ define i32 @smax_three_exit_users(ptr %src, i64 %n) {
; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[MAX]], [[V]]
-; CHECK-NEXT: [[MAX_NEXT]] = select i1 [[CMP]], i32 [[MAX]], i32 [[V]]
+; CHECK-NEXT: [[MAX_NEXT]] = call i32 @llvm.smax.i32(i32 [[MAX]], i32 [[V]])
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -124,8 +119,7 @@ loop:
%max = phi i32 [ -2147483648, %entry ], [ %max.next, %loop ]
%gep = getelementptr inbounds i32, ptr %src, i64 %iv
%v = load i32, ptr %gep, align 4
- %cmp = icmp sgt i32 %max, %v
- %max.next = select i1 %cmp, i32 %max, i32 %v
+ %max.next = call i32 @llvm.smax(i32 %max, i32 %v)
%iv.next = add nuw nsw i64 %iv, 1
%ec = icmp eq i64 %iv.next, %n
br i1 %ec, label %exit, label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/minmax_reduction.ll b/llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
index bf6f1f89e2e6e..bc6ce82606cf2 100644
--- a/llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
@@ -13,8 +13,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK-LABEL: @max_red(
; CHECK: %[[VAR:.*]] = insertelement <2 x i32> poison, i32 %max, i64 0
; CHECK: {{.*}} = shufflevector <2 x i32> %[[VAR]], <2 x i32> poison, <2 x i32> zeroinitializer
-; CHECK: icmp sgt <2 x i32>
-; CHECK: select <2 x i1>
+; CHECK: call <2 x i32> @llvm.smax
; CHECK: middle.block
; CHECK: call i32 @llvm.vector.reduce.smax.v2i32
@@ -27,36 +26,7 @@ for.body:
%max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
%arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp sgt i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; Turn this into a max reduction. The select has its inputs reversed therefore
-; this is a max reduction.
-; CHECK-LABEL: @max_red_inverse_select(
-; CHECK: icmp slt <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.smax.v2i32
-
-define i32 @max_red_inverse_select(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp slt i32 %max.red.08, %0
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
+ %max.red.0 = call i32 @llvm.smax.i32(i32 %0, i32 %max.red.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 1024
@@ -68,8 +38,7 @@ for.end:
; Turn this into a min reduction.
; CHECK-LABEL: @min_red(
-; CHECK: icmp slt <2 x i32>
-; CHECK: select <2 x i1>
+; CHECK: call <2 x i32> @llvm.smin
; CHECK: middle.block
; CHECK: call i32 @llvm.vector.reduce.smin.v2i32
@@ -82,36 +51,7 @@ for.body:
%max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
%arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp slt i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; Turn this into a min reduction. The select has its inputs reversed therefore
-; this is a min reduction.
-; CHECK-LABEL: @min_red_inverse_select(
-; CHECK: icmp sgt <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.smin.v2i32
-
-define i32 @min_red_inverse_select(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp sgt i32 %max.red.08, %0
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
+ %max.red.0 = call i32 @llvm.smin.i32(i32 %0, i32 %max.red.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 1024
@@ -125,8 +65,7 @@ for.end:
; Turn this into a max reduction.
; CHECK-LABEL: @umax_red(
-; CHECK: icmp ugt <2 x i32>
-; CHECK: select <2 x i1>
+; CHECK: call <2 x i32> @llvm.umax
; CHECK: middle.block
; CHECK: call i32 @llvm.vector.reduce.umax.v2i32
@@ -139,36 +78,7 @@ for.body:
%max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
%arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp ugt i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; Turn this into a max reduction. The select has its inputs reversed therefore
-; this is a max reduction.
-; CHECK-LABEL: @umax_red_inverse_select(
-; CHECK: icmp ult <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.umax.v2i32
-
-define i32 @umax_red_inverse_select(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp ult i32 %max.red.08, %0
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
+ %max.red.0 = call i32 @llvm.umax.i32(i32 %0, i32 %max.red.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 1024
@@ -180,8 +90,7 @@ for.end:
; Turn this into a min reduction.
; CHECK-LABEL: @umin_red(
-; CHECK: icmp ult <2 x i32>
-; CHECK: select <2 x i1>
+; CHECK: call <2 x i32> @llvm.umin
; CHECK: middle.block
; CHECK: call i32 @llvm.vector.reduce.umin.v2i32
@@ -194,148 +103,7 @@ for.body:
%max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
%arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
%0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp ult i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; Turn this into a min reduction. The select has its inputs reversed therefore
-; this is a min reduction.
-; CHECK-LABEL: @umin_red_inverse_select(
-; CHECK: icmp ugt <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.umin.v2i32
-
-define i32 @umin_red_inverse_select(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp ugt i32 %max.red.08, %0
- %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; SGE -> SLT
-; Turn this into a min reduction (select inputs are reversed).
-; CHECK-LABEL: @sge_min_red(
-; CHECK: icmp sge <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.smin.v2i32
-
-define i32 @sge_min_red(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp sge i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; SLE -> SGT
-; Turn this into a max reduction (select inputs are reversed).
-; CHECK-LABEL: @sle_min_red(
-; CHECK: icmp sle <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.smax.v2i32
-
-define i32 @sle_min_red(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp sle i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; UGE -> ULT
-; Turn this into a min reduction (select inputs are reversed).
-; CHECK-LABEL: @uge_min_red(
-; CHECK: icmp uge <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.umin.v2i32
-
-define i32 @uge_min_red(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp uge i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
- %indvars.iv.next = add i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, 1024
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end:
- ret i32 %max.red.0
-}
-
-; ULE -> UGT
-; Turn this into a max reduction (select inputs are reversed).
-; CHECK-LABEL: @ule_min_red(
-; CHECK: icmp ule <2 x i32>
-; CHECK: select <2 x i1>
-; CHECK: middle.block
-; CHECK: call i32 @llvm.vector.reduce.umax.v2i32
-
-define i32 @ule_min_red(i32 %max) {
-entry:
- br label %for.body
-
-for.body:
- %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
- %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ]
- %arrayidx = getelementptr inbounds [1024 x i32], ptr @A, i64 0, i64 %indvars.iv
- %0 = load i32, ptr %arrayidx, align 4
- %cmp3 = icmp ule i32 %0, %max.red.08
- %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0
+ %max.red.0 = call i32 @llvm.umin.i32(i32 %0, i32 %max.red.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 1024
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll
index e6c80d34ab3a0..f0825392a148c 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll
@@ -10,18 +10,18 @@ define i32 @reduction_smin(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[WIDE_LOAD]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: br label [[FOR_END:%.*]]
; CHECK: for.end:
-; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
+; CHECK-NEXT: ret i32 [[TMP3]]
;
entry:
br label %for.body
@@ -31,8 +31,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp slt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.smin(i32 %result.08, i32 %l0)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 256
@@ -52,18 +51,18 @@ define i32 @reduction_smin_select_ops_flipped(ptr nocapture %A, ptr nocapture %B
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[WIDE_LOAD]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: middle.block:
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: br label [[FOR_END:%.*]]
; CHECK: for.end:
-; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
+; CHECK-NEXT: ret i32 [[TMP3]]
;
entry:
br label %for.body
@@ -73,8 +72,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp slt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %l0, i32 %result.08
+ %v0 = call i32 @llvm.smax(i32 %l0, i32 %result.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 256
@@ -136,18 +134,18 @@ define i32 @reduction_umax(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[WIDE_LOAD]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umax.i32(i32 [[TMP1]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: middle.block:
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: br label [[FOR_END:%.*]]
; CHECK: for.end:
-; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
+; CHECK-NEXT: ret i32 [[TMP3]]
;
entry:
br label %for.body
@@ -157,8 +155,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp ugt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.umax(i32 %result.08, i32 %l0)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 256
@@ -178,18 +175,18 @@ define i32 @reduction_umax_select_ops_flipped(ptr nocapture %A, ptr nocapture %B
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[WIDE_LOAD]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[TMP1]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: middle.block:
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: br label [[FOR_END:%.*]]
; CHECK: for.end:
-; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
+; CHECK-NEXT: ret i32 [[TMP3]]
;
entry:
br label %for.body
@@ -199,8 +196,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp ugt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %l0, i32 %result.08
+ %v0 = call i32 @llvm.umin(i32 %l0, i32 %result.08)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 256
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
index c0364c6fc5032..4a1ce5a8a3f4c 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
@@ -570,13 +570,12 @@ define i32 @reduction_min(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult <4 x i16> [[VEC_IND]], splat (i16 257)
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP24:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP2]], <4 x i1> [[TMP0]], <4 x i32> splat (i32 2147483647))
-; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP24]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.smin.i32(i32 [[TMP25]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP2]], <4 x i1> [[TMP0]], <4 x i32> poison)
+; CHECK-NEXT: [[TMP3]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_MASKED_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i16> [[VEC_IND]], splat (i16 4)
; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260
@@ -584,6 +583,8 @@ define i32 @reduction_min(ptr nocapture %A, ptr nocapture %B) {
; CHECK: middle.block:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.end:
+; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP3]], <4 x i32> [[VEC_PHI]]
+; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP4]])
; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
;
entry:
@@ -594,8 +595,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp slt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.smin(i32 %result.08, i32 %l0)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 257
@@ -614,13 +614,12 @@ define i32 @reduction_max(ptr nocapture %A, ptr nocapture %B) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 1000, [[VECTOR_PH]] ], [ [[RDX_MINMAX:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 1000), [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult <4 x i16> [[VEC_IND]], splat (i16 257)
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP24:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP2]], <4 x i1> [[TMP0]], <4 x i32> zeroinitializer)
-; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP24]])
-; CHECK-NEXT: [[RDX_MINMAX]] = call i32 @llvm.umax.i32(i32 [[TMP25]], i32 [[VEC_PHI]])
+; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP2]], <4 x i1> [[TMP0]], <4 x i32> poison)
+; CHECK-NEXT: [[TMP3]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[WIDE_MASKED_LOAD]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i16> [[VEC_IND]], splat (i16 4)
; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260
@@ -628,6 +627,8 @@ define i32 @reduction_max(ptr nocapture %A, ptr nocapture %B) {
; CHECK: middle.block:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.end:
+; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP3]], <4 x i32> [[VEC_PHI]]
+; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP4]])
; CHECK-NEXT: ret i32 [[RDX_MINMAX]]
;
entry:
@@ -638,8 +639,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp ugt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.umax(i32 %result.08, i32 %l0)
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 257
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-predselect.ll b/llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
index 9402688464792..ce451ea1a3d8b 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
@@ -423,8 +423,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp slt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.smin(i32 %result.08, i32 %l0)
%indvars.iv.next = add i32 %indvars.iv, 1
%exitcond = icmp eq i32 %indvars.iv.next, 257
br i1 %exitcond, label %for.end, label %for.body
@@ -467,8 +466,7 @@ for.body:
%result.08 = phi i32 [ %v0, %for.body ], [ 1000, %entry ]
%arrayidx = getelementptr inbounds i32, ptr %A, i32 %indvars.iv
%l0 = load i32, ptr %arrayidx, align 4
- %c0 = icmp ugt i32 %result.08, %l0
- %v0 = select i1 %c0, i32 %result.08, i32 %l0
+ %v0 = call i32 @llvm.umax(i32 %result.08, i32 %l0)
%indvars.iv.next = add i32 %indvars.iv, 1
%exitcond = icmp eq i32 %indvars.iv.next, 257
br i1 %exitcond, label %for.end, label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
index 2275aef2b4f97..ad991e5170473 100644
--- a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
@@ -202,10 +202,8 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; CHECK-VF4UF1-NEXT: [[WIDE_LOAD]] = load <vscale x 4 x i32>, ptr [[TMP10]], align 4
; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i32> @llvm.vector.splice.right.nxv4i32(<vscale x 4 x i32> [[VECTOR_RECUR]], <vscale x 4 x i32> [[WIDE_LOAD]], i32 1)
; CHECK-VF4UF1-NEXT: [[TMP13:%.*]] = sub nsw <vscale x 4 x i32> [[WIDE_LOAD]], [[TMP12]]
-; CHECK-VF4UF1-NEXT: [[TMP14:%.*]] = icmp sgt <vscale x 4 x i32> [[TMP13]], zeroinitializer
-; CHECK-VF4UF1-NEXT: [[TMP15:%.*]] = select <vscale x 4 x i1> [[TMP14]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> zeroinitializer
-; CHECK-VF4UF1-NEXT: [[TMP16:%.*]] = icmp slt <vscale x 4 x i32> [[VEC_PHI]], [[TMP15]]
-; CHECK-VF4UF1-NEXT: [[TMP17]] = select <vscale x 4 x i1> [[TMP16]], <vscale x 4 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP15]]
+; CHECK-VF4UF1-NEXT: [[TMP14:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> zeroinitializer)
+; CHECK-VF4UF1-NEXT: [[TMP17]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP14]])
; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]]
; CHECK-VF4UF1-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-VF4UF1-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -266,14 +264,10 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) {
; CHECK-VF4UF2-NEXT: [[TMP16:%.*]] = call <vscale x 4 x i32> @llvm.vector.splice.right.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[WIDE_LOAD2]], i32 1)
; CHECK-VF4UF2-NEXT: [[TMP17:%.*]] = sub nsw <vscale x 4 x i32> [[WIDE_LOAD]], [[TMP15]]
; CHECK-VF4UF2-NEXT: [[TMP18:%.*]] = sub nsw <vscale x 4 x i32> [[WIDE_LOAD2]], [[TMP16]]
-; CHECK-VF4UF2-NEXT: [[TMP19:%.*]] = icmp sgt <vscale x 4 x i32> [[TMP17]], zeroinitializer
-; CHECK-VF4UF2-NEXT: [[TMP20:%.*]] = icmp sgt <vscale x 4 x i32> [[TMP18]], zeroinitializer
-; CHECK-VF4UF2-NEXT: [[TMP21:%.*]] = select <vscale x 4 x i1> [[TMP19]], <vscale x 4 x i32> [[TMP17]], <vscale x 4 x i32> zeroinitializer
-; CHECK-VF4UF2-NEXT: [[TMP22:%.*]] = select <vscale x 4 x i1> [[TMP20]], <vscale x 4 x i32> [[TMP18]], <vscale x 4 x i32> zeroinitializer
-; CHECK-VF4UF2-NEXT: [[TMP23:%.*]] = icmp slt <vscale x 4 x i32> [[VEC_PHI]], [[TMP21]]
-; CHECK-VF4UF2-NEXT: [[TMP24:%.*]] = icmp slt <vscale x 4 x i32> [[VEC_PHI1]], [[TMP22]]
-; CHECK-VF4UF2-NEXT: [[TMP25]] = select <vscale x 4 x i1> [[TMP23]], <vscale x 4 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP21]]
-; CHECK-VF4UF2-NEXT: [[TMP26]] = select <vscale x 4 x i1> [[TMP24]], <vscale x 4 x i32> [[VEC_PHI1]], <vscale x 4 x i32> [[TMP22]]
+; CHECK-VF4UF2-NEXT: [[TMP19:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[TMP17]], <vscale x 4 x i32> zeroinitializer)
+; CHECK-VF4UF2-NEXT: [[TMP20:%.*]] = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> [[TMP18]], <vscale x 4 x i32> zeroinitializer)
+; CHECK-VF4UF2-NEXT: [[TMP25]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 4 x i32> [[TMP19]])
+; CHECK-VF4UF2-NEXT: [[TMP26]] = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> [[VEC_PHI1]], <vscale x 4 x i32> [[TMP20]])
; CHECK-VF4UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]]
; CHECK-VF4UF2-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-VF4UF2-NEXT: br i1 [[TMP27]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
@@ -320,10 +314,8 @@ scalar.body:
%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
%1 = load i32, ptr %arrayidx, align 4
%sub3 = sub nsw i32 %1, %0
- %cmp4 = icmp sgt i32 %sub3, 0
- %cond = select i1 %cmp4, i32 %sub3, i32 0
- %cmp5 = icmp slt i32 %minmax.028, %cond
- %minmax.0.cond = select i1 %cmp5, i32 %minmax.028, i32 %cond
+ %cond = call i32 @llvm.smax(i32 %sub3, i32 0)
+ %minmax.0.cond = call i32 @llvm.smin(i32 %minmax.028, i32 %cond)
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, %n
diff --git a/llvm/test/Transforms/LoopVectorize/select-reduction.ll b/llvm/test/Transforms/LoopVectorize/select-reduction.ll
index 28bb8a2b13114..c69ef5299fe6c 100644
--- a/llvm/test/Transforms/LoopVectorize/select-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-reduction.ll
@@ -23,18 +23,18 @@ define i32 @test(i64 %N, i32 %x) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IV:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[VEC_PHI]], splat (i32 10)
-; CHECK-NEXT: [[TMP2]] = select <4 x i1> [[TMP1]], <4 x i32> [[VEC_PHI]], <4 x i32> splat (i32 10)
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP1]] = select <4 x i1> [[TMP0]], <4 x i1> splat (i1 true), <4 x i1> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i64> [[VEC_IV]], splat (i64 4)
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]
-; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP2]], <4 x i32> [[VEC_PHI]]
-; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP3]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP1]])
+; CHECK-NEXT: [[TMP6:%.*]] = freeze i1 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP6]], i32 10, i32 0
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: exit.loopexit:
; CHECK-NEXT: br label [[EXIT]]
diff --git a/llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll b/llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
index ed2204fa807b3..4c77b61607607 100644
--- a/llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
+++ b/llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
@@ -603,7 +603,7 @@ define void @test12(i1 %arg) {
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[INDVAR]], 1
-; CHECK-NEXT: br i1 %arg, label [[EXIT:%.*]], label [[FOR_BODY]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[EXIT:%.*]], label [[FOR_BODY]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
@@ -801,10 +801,8 @@ define i32 @test16(float %f) {
; CHECK-LABEL: @test16(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[I:%.*]] = fptosi float [[F:%.*]] to i64
-; CHECK-NEXT: [[COND_LEFT:%.*]] = icmp slt i64 [[I]], 0
-; CHECK-NEXT: [[CLAMP_LEFT:%.*]] = select i1 [[COND_LEFT]], i64 0, i64 [[I]]
-; CHECK-NEXT: [[COND_RIGHT:%.*]] = icmp sgt i64 [[I]], 3
-; CHECK-NEXT: [[CLAMP:%.*]] = select i1 [[COND_RIGHT]], i64 3, i64 [[CLAMP_LEFT]]
+; CHECK-NEXT: [[CLAMP_LEFT:%.*]] = call i64 @llvm.smax.i64(i64 [[I]], i64 0)
+; CHECK-NEXT: [[CLAMP:%.*]] = call i64 @llvm.smin.i64(i64 [[CLAMP_LEFT]], i64 3)
; CHECK-NEXT: br label [[LEAFBLOCK:%.*]]
; CHECK: LeafBlock:
; CHECK-NEXT: [[SWITCHLEAF:%.*]] = icmp sge i64 [[CLAMP]], 2
@@ -821,10 +819,8 @@ define i32 @test16(float %f) {
;
entry:
%i = fptosi float %f to i64
- %cond.left = icmp slt i64 %i, 0
- %clamp.left = select i1 %cond.left, i64 0, i64 %i
- %cond.right = icmp sgt i64 %i, 3
- %clamp = select i1 %cond.right, i64 3, i64 %clamp.left
+ %clamp.left = call i64 @llvm.smax.i64(i64 %i, i64 0)
+ %clamp = call i64 @llvm.smin.i64(i64 %clamp.left, i64 3)
switch i64 %clamp, label %case.D [
i64 0, label %case.1
i64 1, label %case.1
diff --git a/llvm/test/Transforms/NaryReassociate/nary-req.ll b/llvm/test/Transforms/NaryReassociate/nary-req.ll
index 054afd7d44e00..8f339769831fd 100644
--- a/llvm/test/Transforms/NaryReassociate/nary-req.ll
+++ b/llvm/test/Transforms/NaryReassociate/nary-req.ll
@@ -9,22 +9,16 @@ declare i64 @llvm.umin.i64(i64, i64)
; use from %smax3 and side use from %res2.
define i32 @smax_test1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test1(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[SMAX2]], [[A]]
-; CHECK-NEXT: [[SMAX3:%.*]] = select i1 [[C3]], i32 [[SMAX2]], i32 [[A]]
+; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[SMAX2:%.*]] = call i32 @llvm.smax.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[SMAX3:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3]]
; CHECK-NEXT: [[RES2:%.*]] = add i32 [[RES]], [[SMAX2]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %b, %c
- %smax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sgt i32 %smax2, %a
- %smax3 = select i1 %c3, i32 %smax2, i32 %a
+ %smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %smax3 = call i32 @llvm.smax.i32(i32 %smax2, i32 %a)
%res = add i32 %smax1, %smax3
%res2 = add i32 %res, %smax2
ret i32 %res
@@ -71,33 +65,18 @@ bb:
; which is matched on the next iteration.
define i32 @nary_infinite_loop_minmax(i32 %d0, i32 %d1, i32 %d2, i32 %d3) {
; CHECK-LABEL: @nary_infinite_loop_minmax(
-; CHECK-NEXT: [[CMP0:%.*]] = icmp slt i32 [[D2:%.*]], [[D1:%.*]]
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 [[D1]], i32 [[D2]]
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[D3:%.*]], [[D0:%.*]]
-; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 [[D0]], i32 [[D3]]
-; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[SEL1]], [[SEL0]]
-; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 [[SEL1]], i32 [[SEL0]]
-; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i32 [[D3]], [[D0]]
-; CHECK-NEXT: [[SEL3:%.*]] = select i1 [[CMP3]], i32 [[D0]], i32 [[D3]]
-; CHECK-NEXT: [[SEL5_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SEL0]], i32 [[SEL3]])
+; CHECK-NEXT: [[SEL0:%.*]] = call i32 @llvm.smax.i32(i32 [[D2:%.*]], i32 [[D1:%.*]])
+; CHECK-NEXT: [[SEL1:%.*]] = call i32 @llvm.smax.i32(i32 [[D3:%.*]], i32 [[D0:%.*]])
+; CHECK-NEXT: [[SEL2:%.*]] = call i32 @llvm.smax.i32(i32 [[SEL1]], i32 [[SEL0]])
+; CHECK-NEXT: [[SEL3:%.*]] = call i32 @llvm.smax.i32(i32 [[D3]], i32 [[D0]])
+; CHECK-NEXT: [[SEL5_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SEL3]], i32 [[SEL0]])
; CHECK-NEXT: ret i32 [[SEL5_NARY]]
;
- %cmp0 = icmp slt i32 %d2, %d1
- %sel0 = select i1 %cmp0, i32 %d1, i32 %d2
-
- %cmp1 = icmp slt i32 %d3, %d0
- %sel1 = select i1 %cmp1, i32 %d0, i32 %d3
-
- %cmp2 = icmp slt i32 %sel1, %sel0
- %sel2 = select i1 %cmp2, i32 %sel1, i32 %sel0
-
- %cmp3 = icmp slt i32 %d3, %d0
- %sel3 = select i1 %cmp3, i32 %d0, i32 %d3
-
- %cmp4 = icmp slt i32 %sel3, %d2
- %sel4 = select i1 %cmp4, i32 %d2, i32 %sel3
-
- %cmp5 = icmp slt i32 %sel4, %d1
- %sel5 = select i1 %cmp5, i32 %d1, i32 %sel4
+ %sel0 = call i32 @llvm.smax.i32(i32 %d2, i32 %d1)
+ %sel1 = call i32 @llvm.smax.i32(i32 %d3, i32 %d0)
+ %sel2 = call i32 @llvm.smax.i32(i32 %sel1, i32 %sel0)
+ %sel3 = call i32 @llvm.smax.i32(i32 %d3, i32 %d0)
+ %sel4 = call i32 @llvm.smax.i32(i32 %sel3, i32 %d2)
+ %sel5 = call i32 @llvm.smax.i32(i32 %sel4, i32 %d1)
ret i32 %sel5
}
diff --git a/llvm/test/Transforms/NaryReassociate/nary-smax.ll b/llvm/test/Transforms/NaryReassociate/nary-smax.ll
index 43e93c7d2a08f..4889039a4e271 100644
--- a/llvm/test/Transforms/NaryReassociate/nary-smax.ll
+++ b/llvm/test/Transforms/NaryReassociate/nary-smax.ll
@@ -7,18 +7,14 @@ declare i32 @llvm.smax.i32(i32 %a, i32 %b)
; m2 = smax(smax((b,c), a) -> m2 = smax(m1, c)
define i32 @smax_test1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test1(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMAX3_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %b, %c
- %smax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sgt i32 %smax2, %a
- %smax3 = select i1 %c3, i32 %smax2, i32 %a
+ %smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %smax3 = call i32 @llvm.smax.i32(i32 %smax2, i32 %a)
%res = add i32 %smax1, %smax3
ret i32 %res
}
@@ -27,33 +23,14 @@ define i32 @smax_test1(i32 %a, i32 %b, i32 %c) {
; m2 = smax(b, (smax(a, c))) -> m2 = smax(m1, c)
define i32 @smax_test2(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test2(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[SMAX3_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX1]], i32 [[C:%.*]])
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3_NARY]]
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %a, %c
- %smax2 = select i1 %c2, i32 %a, i32 %c
- %c3 = icmp sgt i32 %b, %smax2
- %smax3 = select i1 %c3, i32 %b, i32 %smax2
- %res = add i32 %smax1, %smax3
- ret i32 %res
-}
-
-; Same test as smax_test1 but uses @llvm.smax intrinsic
-define i32 @smax_test3(i32 %a, i32 %b, i32 %c) {
-; CHECK-LABEL: @smax_test3(
; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMAX3_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
%smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
- %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
- %smax3 = call i32 @llvm.smax.i32(i32 %smax2, i32 %a)
+ %smax2 = call i32 @llvm.smax.i32(i32 %a, i32 %c)
+ %smax3 = call i32 @llvm.smax.i32(i32 %b, i32 %smax2)
%res = add i32 %smax1, %smax3
ret i32 %res
}
@@ -62,18 +39,14 @@ define i32 @smax_test3(i32 %a, i32 %b, i32 %c) {
; m2 = smax(smax_or_eq((b,c), a) -> m2 = smax(m1, c)
define i32 @umax_test4(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test4(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMAX3_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sge i32 %b, %c
- %smax_or_eq2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sgt i32 %smax_or_eq2, %a
- %smax3 = select i1 %c3, i32 %smax_or_eq2, i32 %a
+ %smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %smax_or_eq2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %smax3 = call i32 @llvm.smax.i32(i32 %smax_or_eq2, i32 %a)
%res = add i32 %smax1, %smax3
ret i32 %res
}
@@ -82,18 +55,14 @@ define i32 @umax_test4(i32 %a, i32 %b, i32 %c) {
; m2 = smax_or_eq(smax((b,c), a) -> m2 = smax(m1, c)
define i32 @smax_test5(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test5(
-; CHECK-NEXT: [[C1:%.*]] = icmp sge i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX_OR_EQ1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMAX_OR_EQ1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMAX_OR_EQ3_NARY:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX_OR_EQ1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX_OR_EQ1]], [[SMAX_OR_EQ3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sge i32 %a, %b
- %smax_or_eq1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %b, %c
- %smax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sge i32 %smax2, %a
- %smax_or_eq3 = select i1 %c3, i32 %smax2, i32 %a
+ %smax_or_eq1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %smax_or_eq3 = call i32 @llvm.smax.i32(i32 %smax2, i32 %a)
%res = add i32 %smax_or_eq1, %smax_or_eq3
ret i32 %res
}
@@ -102,21 +71,15 @@ define i32 @smax_test5(i32 %a, i32 %b, i32 %c) {
; m2 = smax(umax((b,c), a) ; check that signed and unsigned maxs are not mixed
define i32 @smax_test6(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test6(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp ugt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[UMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[UMAX2]], [[A]]
-; CHECK-NEXT: [[SMAX3:%.*]] = select i1 [[C3]], i32 [[UMAX2]], i32 [[A]]
+; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[UMAX2:%.*]] = call i32 @llvm.umax.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[SMAX3:%.*]] = call i32 @llvm.smax.i32(i32 [[UMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ugt i32 %b, %c
- %umax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sgt i32 %umax2, %a
- %smax3 = select i1 %c3, i32 %umax2, i32 %a
+ %smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %umax2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
+ %smax3 = call i32 @llvm.smax.i32(i32 %umax2, i32 %a)
%res = add i32 %smax1, %smax3
ret i32 %res
}
@@ -125,21 +88,15 @@ define i32 @smax_test6(i32 %a, i32 %b, i32 %c) {
; m2 = smax(smin((b,c), a) ; check that max and min are not mixed
define i32 @smax_test7(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smax_test7(
-; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[SMIN2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[SMIN2]], [[A]]
-; CHECK-NEXT: [[SMAX3:%.*]] = select i1 [[C3]], i32 [[SMIN2]], i32 [[A]]
+; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[SMIN2:%.*]] = call i32 @llvm.smin.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[SMAX3:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMAX1]], [[SMAX3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sgt i32 %a, %b
- %smax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp slt i32 %b, %c
- %smin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp slt i32 %smin2, %a
- %smax3 = select i1 %c3, i32 %smin2, i32 %a
+ %smax1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %smin2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
+ %smax3 = call i32 @llvm.smin.i32(i32 %smin2, i32 %a)
%res = add i32 %smax1, %smax3
ret i32 %res
}
diff --git a/llvm/test/Transforms/NaryReassociate/nary-smin.ll b/llvm/test/Transforms/NaryReassociate/nary-smin.ll
index a8e9fe8247c7a..c0416999681e5 100644
--- a/llvm/test/Transforms/NaryReassociate/nary-smin.ll
+++ b/llvm/test/Transforms/NaryReassociate/nary-smin.ll
@@ -7,18 +7,14 @@ declare i32 @llvm.smin.i32(i32 %a, i32 %b)
; m2 = smin(smin((b,c), a) -> m2 = smin(m1, c)
define i32 @smin_test1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smin_test1(
-; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMIN3_NARY:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp slt i32 %a, %b
- %smin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp slt i32 %b, %c
- %smin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp slt i32 %smin2, %a
- %smin3 = select i1 %c3, i32 %smin2, i32 %a
+ %smin1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %smin2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
+ %smin3 = call i32 @llvm.smin.i32(i32 %smin2, i32 %a)
%res = add i32 %smin1, %smin3
ret i32 %res
}
@@ -27,33 +23,14 @@ define i32 @smin_test1(i32 %a, i32 %b, i32 %c) {
; m2 = smin(b, (smin(a, c))) -> m2 = smin(m1, c)
define i32 @smin_test2(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smin_test2(
-; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[SMIN3_NARY:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN1]], i32 [[C:%.*]])
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3_NARY]]
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %c1 = icmp slt i32 %a, %b
- %smin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp slt i32 %a, %c
- %smin2 = select i1 %c2, i32 %a, i32 %c
- %c3 = icmp slt i32 %b, %smin2
- %smin3 = select i1 %c3, i32 %b, i32 %smin2
- %res = add i32 %smin1, %smin3
- ret i32 %res
-}
-
-; Same test as smin_test1 but uses @llvm.smin intrinsic
-define i32 @smin_test3(i32 %a, i32 %b, i32 %c) {
-; CHECK-LABEL: @smin_test3(
; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMIN3_NARY:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
%smin1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
- %smin2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
- %smin3 = call i32 @llvm.smin.i32(i32 %smin2, i32 %a)
+ %smin2 = call i32 @llvm.smin.i32(i32 %a, i32 %c)
+ %smin3 = call i32 @llvm.smin.i32(i32 %b, i32 %smin2)
%res = add i32 %smin1, %smin3
ret i32 %res
}
@@ -62,18 +39,14 @@ define i32 @smin_test3(i32 %a, i32 %b, i32 %c) {
; m2 = smin(smin_or_eq((b,c), a) -> m2 = smin(m1, c)
define i32 @umin_test4(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test4(
-; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMIN3_NARY:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp slt i32 %a, %b
- %smin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sle i32 %b, %c
- %smin_or_eq2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp slt i32 %smin_or_eq2, %a
- %smin3 = select i1 %c3, i32 %smin_or_eq2, i32 %a
+ %smin1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %smin_or_eq2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
+ %smin3 = call i32 @llvm.smin.i32(i32 %smin_or_eq2, i32 %a)
%res = add i32 %smin1, %smin3
ret i32 %res
}
@@ -82,18 +55,14 @@ define i32 @umin_test4(i32 %a, i32 %b, i32 %c) {
; m2 = smin_or_eq(smin((b,c), a) -> m2 = smin(m1, c)
define i32 @smin_test5(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smin_test5(
-; CHECK-NEXT: [[C1:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN_OR_EQ1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[SMIN_OR_EQ1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[SMIN_OR_EQ3_NARY:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN_OR_EQ1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN_OR_EQ1]], [[SMIN_OR_EQ3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp sle i32 %a, %b
- %smin_or_eq1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp slt i32 %b, %c
- %smin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp sle i32 %smin2, %a
- %smin_or_eq3 = select i1 %c3, i32 %smin2, i32 %a
+ %smin_or_eq1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %smin2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
+ %smin_or_eq3 = call i32 @llvm.smin.i32(i32 %smin2, i32 %a)
%res = add i32 %smin_or_eq1, %smin_or_eq3
ret i32 %res
}
@@ -102,21 +71,15 @@ define i32 @smin_test5(i32 %a, i32 %b, i32 %c) {
; m2 = smin(umin((b,c), a) ; check that signed and unsigned mins are not mixed
define i32 @smin_test6(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smin_test6(
-; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[UMIN2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[UMIN2]], [[A]]
-; CHECK-NEXT: [[SMIN3:%.*]] = select i1 [[C3]], i32 [[UMIN2]], i32 [[A]]
+; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[UMIN2:%.*]] = call i32 @llvm.umin.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[SMIN3:%.*]] = call i32 @llvm.smin.i32(i32 [[UMIN2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp slt i32 %a, %b
- %smin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ult i32 %b, %c
- %umin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp slt i32 %umin2, %a
- %smin3 = select i1 %c3, i32 %umin2, i32 %a
+ %smin1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %umin2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
+ %smin3 = call i32 @llvm.smin.i32(i32 %umin2, i32 %a)
%res = add i32 %smin1, %smin3
ret i32 %res
}
@@ -125,21 +88,15 @@ define i32 @smin_test6(i32 %a, i32 %b, i32 %c) {
; m2 = smin(smax((b,c), a) ; check that min and max are not mixed
define i32 @smin_test7(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @smin_test7(
-; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[SMAX2]], [[A]]
-; CHECK-NEXT: [[SMIN3:%.*]] = select i1 [[C3]], i32 [[SMAX2]], i32 [[A]]
+; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[SMAX2:%.*]] = call i32 @llvm.smax.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[SMIN3:%.*]] = call i32 @llvm.smin.i32(i32 [[SMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[SMIN1]], [[SMIN3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp slt i32 %a, %b
- %smin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %b, %c
- %smax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp slt i32 %smax2, %a
- %smin3 = select i1 %c3, i32 %smax2, i32 %a
+ %smin1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %smin3 = call i32 @llvm.smin.i32(i32 %smax2, i32 %a)
%res = add i32 %smin1, %smin3
ret i32 %res
}
diff --git a/llvm/test/Transforms/NaryReassociate/nary-umax.ll b/llvm/test/Transforms/NaryReassociate/nary-umax.ll
index b391fc4ba3ebb..08c9875e05278 100644
--- a/llvm/test/Transforms/NaryReassociate/nary-umax.ll
+++ b/llvm/test/Transforms/NaryReassociate/nary-umax.ll
@@ -7,18 +7,14 @@ declare i32 @llvm.umax.i32(i32 %a, i32 %b)
; m2 = umax(umax((b,c), a) -> m2 = umax(m1, c)
define i32 @umax_test1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test1(
-; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMAX3_NARY:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ugt i32 %a, %b
- %umax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ugt i32 %b, %c
- %umax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ugt i32 %umax2, %a
- %umax3 = select i1 %c3, i32 %umax2, i32 %a
+ %umax1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %umax2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
+ %umax3 = call i32 @llvm.umax.i32(i32 %umax2, i32 %a)
%res = add i32 %umax1, %umax3
ret i32 %res
}
@@ -27,33 +23,14 @@ define i32 @umax_test1(i32 %a, i32 %b, i32 %c) {
; m2 = umax(b, (umax(a, c))) -> m2 = umax(m1, c)
define i32 @umax_test2(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test2(
-; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[UMAX3_NARY:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX1]], i32 [[C:%.*]])
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3_NARY]]
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %c1 = icmp ugt i32 %a, %b
- %umax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ugt i32 %a, %c
- %umax2 = select i1 %c2, i32 %a, i32 %c
- %c3 = icmp ugt i32 %b, %umax2
- %umax3 = select i1 %c3, i32 %b, i32 %umax2
- %res = add i32 %umax1, %umax3
- ret i32 %res
-}
-
-; Same test as umax_test1 but uses @llvm.umax intrinsic
-define i32 @umax_test3(i32 %a, i32 %b, i32 %c) {
-; CHECK-LABEL: @umax_test3(
; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMAX3_NARY:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
%umax1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
- %umax2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
- %umax3 = call i32 @llvm.umax.i32(i32 %umax2, i32 %a)
+ %umax2 = call i32 @llvm.umax.i32(i32 %a, i32 %c)
+ %umax3 = call i32 @llvm.umax.i32(i32 %b, i32 %umax2)
%res = add i32 %umax1, %umax3
ret i32 %res
}
@@ -62,18 +39,14 @@ define i32 @umax_test3(i32 %a, i32 %b, i32 %c) {
; m2 = umax(umax_or_eq((b,c), a) -> m2 = umax(m1, c)
define i32 @umax_test4(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test4(
-; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMAX3_NARY:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ugt i32 %a, %b
- %umax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp uge i32 %b, %c
- %umax_or_eq2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ugt i32 %umax_or_eq2, %a
- %umax3 = select i1 %c3, i32 %umax_or_eq2, i32 %a
+ %umax1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %umax_or_eq2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
+ %umax3 = call i32 @llvm.umax.i32(i32 %umax_or_eq2, i32 %a)
%res = add i32 %umax1, %umax3
ret i32 %res
}
@@ -82,18 +55,14 @@ define i32 @umax_test4(i32 %a, i32 %b, i32 %c) {
; m2 = umax_or_eq(umax((b,c), a) -> m2 = umax(m1, c)
define i32 @umax_test5(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test5(
-; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX_OR_EQ1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMAX_OR_EQ1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMAX_OR_EQ3_NARY:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX_OR_EQ1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX_OR_EQ1]], [[UMAX_OR_EQ3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp uge i32 %a, %b
- %umax_or_eq1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ugt i32 %b, %c
- %umax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp uge i32 %umax2, %a
- %umax_or_eq3 = select i1 %c3, i32 %umax2, i32 %a
+ %umax_or_eq1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %umax2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
+ %umax_or_eq3 = call i32 @llvm.umax.i32(i32 %umax2, i32 %a)
%res = add i32 %umax_or_eq1, %umax_or_eq3
ret i32 %res
}
@@ -102,21 +71,15 @@ define i32 @umax_test5(i32 %a, i32 %b, i32 %c) {
; m2 = umax(smax((b,c), a) ; check that signed and unsigned maxs are not mixed
define i32 @umax_test6(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test6(
-; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp ugt i32 [[SMAX2]], [[A]]
-; CHECK-NEXT: [[UMAX3:%.*]] = select i1 [[C3]], i32 [[SMAX2]], i32 [[A]]
+; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[SMAX2:%.*]] = call i32 @llvm.smax.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[SMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ugt i32 %a, %b
- %umax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp sgt i32 %b, %c
- %smax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ugt i32 %smax2, %a
- %umax3 = select i1 %c3, i32 %smax2, i32 %a
+ %umax1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %smax2 = call i32 @llvm.smax.i32(i32 %b, i32 %c)
+ %umax3 = call i32 @llvm.umax.i32(i32 %smax2, i32 %a)
%res = add i32 %umax1, %umax3
ret i32 %res
}
@@ -125,21 +88,15 @@ define i32 @umax_test6(i32 %a, i32 %b, i32 %c) {
; m2 = umax(umin((b,c), a) ; check that max and min are not mixed
define i32 @umax_test7(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umax_test7(
-; CHECK-NEXT: [[C1:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMAX1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[UMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp ugt i32 [[UMAX2]], [[A]]
-; CHECK-NEXT: [[UMAX3:%.*]] = select i1 [[C3]], i32 [[UMAX2]], i32 [[A]]
+; CHECK-NEXT: [[UMAX1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[UMAX2:%.*]] = call i32 @llvm.umin.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[UMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMAX1]], [[UMAX3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ugt i32 %a, %b
- %umax1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ult i32 %b, %c
- %umax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ugt i32 %umax2, %a
- %umax3 = select i1 %c3, i32 %umax2, i32 %a
+ %umax1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %umax2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
+ %umax3 = call i32 @llvm.umax.i32(i32 %umax2, i32 %a)
%res = add i32 %umax1, %umax3
ret i32 %res
}
diff --git a/llvm/test/Transforms/NaryReassociate/nary-umin.ll b/llvm/test/Transforms/NaryReassociate/nary-umin.ll
index 58fdcc3f47a5a..b0be4ea801f63 100644
--- a/llvm/test/Transforms/NaryReassociate/nary-umin.ll
+++ b/llvm/test/Transforms/NaryReassociate/nary-umin.ll
@@ -7,18 +7,14 @@ declare i32 @llvm.umin.i32(i32 %a, i32 %b)
; m2 = umin(umin((b,c), a) -> m2 = umin(m1, c)
define i32 @umin_test1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test1(
-; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMIN3_NARY:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ult i32 %a, %b
- %umin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ult i32 %b, %c
- %umin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ult i32 %umin2, %a
- %umin3 = select i1 %c3, i32 %umin2, i32 %a
+ %umin1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %umin2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
+ %umin3 = call i32 @llvm.umin.i32(i32 %umin2, i32 %a)
%res = add i32 %umin1, %umin3
ret i32 %res
}
@@ -27,33 +23,14 @@ define i32 @umin_test1(i32 %a, i32 %b, i32 %c) {
; m2 = umin(b, (umin(a, c))) -> m2 = umin(m1, c)
define i32 @umin_test2(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test2(
-; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[UMIN3_NARY:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN1]], i32 [[C:%.*]])
-; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3_NARY]]
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %c1 = icmp ult i32 %a, %b
- %umin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ult i32 %a, %c
- %umin2 = select i1 %c2, i32 %a, i32 %c
- %c3 = icmp ult i32 %b, %umin2
- %umin3 = select i1 %c3, i32 %b, i32 %umin2
- %res = add i32 %umin1, %umin3
- ret i32 %res
-}
-
-; Same test as umin_test1 but uses @llvm.umin intrinsic
-define i32 @umin_test3(i32 %a, i32 %b, i32 %c) {
-; CHECK-LABEL: @umin_test3(
; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMIN3_NARY:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
%umin1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
- %umin2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
- %umin3 = call i32 @llvm.umin.i32(i32 %umin2, i32 %a)
+ %umin2 = call i32 @llvm.umin.i32(i32 %a, i32 %c)
+ %umin3 = call i32 @llvm.umin.i32(i32 %b, i32 %umin2)
%res = add i32 %umin1, %umin3
ret i32 %res
}
@@ -62,18 +39,14 @@ define i32 @umin_test3(i32 %a, i32 %b, i32 %c) {
; m2 = umin(umin_or_eq((b,c), a) -> m2 = umin(m1, c)
define i32 @umin_test4(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test4(
-; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMIN3_NARY:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ult i32 %a, %b
- %umin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ule i32 %b, %c
- %umin_or_eq2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ult i32 %umin_or_eq2, %a
- %umin3 = select i1 %c3, i32 %umin_or_eq2, i32 %a
+ %umin1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %umin_or_eq2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
+ %umin3 = call i32 @llvm.umin.i32(i32 %umin_or_eq2, i32 %a)
%res = add i32 %umin1, %umin3
ret i32 %res
}
@@ -82,18 +55,14 @@ define i32 @umin_test4(i32 %a, i32 %b, i32 %c) {
; m2 = umin_or_eq(umin((b,c), a) -> m2 = umin(m1, c)
define i32 @umin_test5(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test5(
-; CHECK-NEXT: [[C1:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN_OR_EQ1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT: [[UMIN_OR_EQ1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
; CHECK-NEXT: [[UMIN_OR_EQ3_NARY:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN_OR_EQ1]], i32 [[C:%.*]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN_OR_EQ1]], [[UMIN_OR_EQ3_NARY]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ule i32 %a, %b
- %umin_or_eq1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ult i32 %b, %c
- %umin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ule i32 %umin2, %a
- %umin_or_eq3 = select i1 %c3, i32 %umin2, i32 %a
+ %umin_or_eq1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %umin2 = call i32 @llvm.umin.i32(i32 %b, i32 %c)
+ %umin_or_eq3 = call i32 @llvm.umin.i32(i32 %umin2, i32 %a)
%res = add i32 %umin_or_eq1, %umin_or_eq3
ret i32 %res
}
@@ -102,21 +71,15 @@ define i32 @umin_test5(i32 %a, i32 %b, i32 %c) {
; m2 = umin(smin((b,c), a) ; check that signed and unsigned mins are not mixed
define i32 @umin_test6(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test6(
-; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[SMIN2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp ult i32 [[SMIN2]], [[A]]
-; CHECK-NEXT: [[UMIN3:%.*]] = select i1 [[C3]], i32 [[SMIN2]], i32 [[A]]
+; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[SMIN2:%.*]] = call i32 @llvm.smin.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[UMIN3:%.*]] = call i32 @llvm.umin.i32(i32 [[SMIN2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ult i32 %a, %b
- %umin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp slt i32 %b, %c
- %smin2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ult i32 %smin2, %a
- %umin3 = select i1 %c3, i32 %smin2, i32 %a
+ %umin1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %smin2 = call i32 @llvm.smin.i32(i32 %b, i32 %c)
+ %umin3 = call i32 @llvm.umin.i32(i32 %smin2, i32 %a)
%res = add i32 %umin1, %umin3
ret i32 %res
}
@@ -125,21 +88,15 @@ define i32 @umin_test6(i32 %a, i32 %b, i32 %c) {
; m2 = umin(umax((b,c), a) ; check that min and max are not mixed
define i32 @umin_test7(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: @umin_test7(
-; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[UMIN1:%.*]] = select i1 [[C1]], i32 [[A]], i32 [[B]]
-; CHECK-NEXT: [[C2:%.*]] = icmp ugt i32 [[B]], [[C:%.*]]
-; CHECK-NEXT: [[UMAX2:%.*]] = select i1 [[C2]], i32 [[B]], i32 [[C]]
-; CHECK-NEXT: [[C3:%.*]] = icmp ult i32 [[UMAX2]], [[A]]
-; CHECK-NEXT: [[UMIN3:%.*]] = select i1 [[C3]], i32 [[UMAX2]], i32 [[A]]
+; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+; CHECK-NEXT: [[UMAX2:%.*]] = call i32 @llvm.umax.i32(i32 [[B]], i32 [[C:%.*]])
+; CHECK-NEXT: [[UMIN3:%.*]] = call i32 @llvm.umin.i32(i32 [[UMAX2]], i32 [[A]])
; CHECK-NEXT: [[RES:%.*]] = add i32 [[UMIN1]], [[UMIN3]]
; CHECK-NEXT: ret i32 [[RES]]
;
- %c1 = icmp ult i32 %a, %b
- %umin1 = select i1 %c1, i32 %a, i32 %b
- %c2 = icmp ugt i32 %b, %c
- %umax2 = select i1 %c2, i32 %b, i32 %c
- %c3 = icmp ult i32 %umax2, %a
- %umin3 = select i1 %c3, i32 %umax2, i32 %a
+ %umin1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %umax2 = call i32 @llvm.umax.i32(i32 %b, i32 %c)
+ %umin3 = call i32 @llvm.umin.i32(i32 %umax2, i32 %a)
%res = add i32 %umin1, %umin3
ret i32 %res
}
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
index 72fb03e60a297..c6dc69e69dd31 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
@@ -15,40 +15,31 @@
; Tests whether the min/max reduction pattern is vectorized if SLP starts at the store.
define i32 @smaxv6() {
; GFX9-LABEL: @smaxv6(
-; GFX9-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @arr, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @arr, align 16
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i32 [[TMP2]], i32 [[TMP3]]
-; GFX9-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; GFX9-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]])
-; GFX9-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP5]], [[SELECT1]]
-; GFX9-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP5]], i32 [[SELECT1]]
+; GFX9-NEXT: [[LOAD5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+; GFX9-NEXT: [[LOAD6:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+; GFX9-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP1]])
+; GFX9-NEXT: [[TMP5:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP4]], i32 [[LOAD5]])
+; GFX9-NEXT: [[TMP6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP5]], i32 [[LOAD6]])
; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i32 3, i32 4
; GFX9-NEXT: store i32 [[STORE_SELECT]], ptr @var, align 8
-; GFX9-NEXT: ret i32 [[OP_RDX1]]
+; GFX9-NEXT: ret i32 [[TMP6]]
;
%load1 = load i32, ptr @arr, align 16
%load2 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
%cmp1 = icmp sgt i32 %load1, %load2
- %select1 = select i1 %cmp1, i32 %load1, i32 %load2
-
- %load3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %cmp2 = icmp sgt i32 %select1, %load3
- %select2 = select i1 %cmp2, i32 %select1, i32 %load3
-
- %load4 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %cmp3 = icmp sgt i32 %select2, %load4
- %select3 = select i1 %cmp3, i32 %select2, i32 %load4
-
- %load5 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %cmp4 = icmp sgt i32 %select3, %load5
- %select4 = select i1 %cmp4, i32 %select3, i32 %load5
-
- %load6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %cmp5 = icmp sgt i32 %select4, %load6
- %select5 = select i1 %cmp5, i32 %select4, i32 %load6
-
+ %select1 = call i32 @llvm.smax.i32(i32 %load1, i32 %load2)
+ %load3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %select2 = call i32 @llvm.smax.i32(i32 %select1, i32 %load3)
+ %load4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %select3 = call i32 @llvm.smax.i32(i32 %select2, i32 %load4)
+ %load5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %select4 = call i32 @llvm.smax.i32(i32 %select3, i32 %load5)
+ %load6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %select5 = call i32 @llvm.smax.i32(i32 %select4, i32 %load6)
%store-select = select i1 %cmp1, i32 3, i32 4
store i32 %store-select, ptr @var, align 8
ret i32 %select5
@@ -56,40 +47,31 @@ define i32 @smaxv6() {
define i64 @sminv6() {
; GFX9-LABEL: @sminv6(
-; GFX9-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @arr64, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @arr64, align 16
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP1]], i32 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP1]], i32 1
; GFX9-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
-; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i64 [[TMP2]], i64 [[TMP3]]
-; GFX9-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 2), align 16
-; GFX9-NEXT: [[TMP5:%.*]] = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> [[TMP4]])
-; GFX9-NEXT: [[OP_RDX:%.*]] = icmp slt i64 [[TMP5]], [[SELECT1]]
-; GFX9-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i64 [[TMP5]], i64 [[SELECT1]]
+; GFX9-NEXT: [[LOAD5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 32), align 16
+; GFX9-NEXT: [[LOAD6:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 40), align 8
+; GFX9-NEXT: [[TMP4:%.*]] = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> [[TMP1]])
+; GFX9-NEXT: [[TMP5:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP4]], i64 [[LOAD5]])
+; GFX9-NEXT: [[TMP6:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP5]], i64 [[LOAD6]])
; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i64 3, i64 4
; GFX9-NEXT: store i64 [[STORE_SELECT]], ptr @var64, align 8
-; GFX9-NEXT: ret i64 [[OP_RDX1]]
+; GFX9-NEXT: ret i64 [[TMP6]]
;
%load1 = load i64, ptr @arr64, align 16
%load2 = load i64, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 1), align 8
%cmp1 = icmp slt i64 %load1, %load2
- %select1 = select i1 %cmp1, i64 %load1, i64 %load2
-
- %load3 = load i64, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 2), align 16
- %cmp2 = icmp slt i64 %select1, %load3
- %select2 = select i1 %cmp2, i64 %select1, i64 %load3
-
- %load4 = load i64, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 3), align 8
- %cmp3 = icmp slt i64 %select2, %load4
- %select3 = select i1 %cmp3, i64 %select2, i64 %load4
-
- %load5 = load i64, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 4), align 16
- %cmp4 = icmp slt i64 %select3, %load5
- %select4 = select i1 %cmp4, i64 %select3, i64 %load5
-
- %load6 = load i64, ptr getelementptr inbounds ([32 x i64], ptr @arr64, i64 0, i64 5), align 8
- %cmp5 = icmp slt i64 %select4, %load6
- %select5 = select i1 %cmp5, i64 %select4, i64 %load6
-
+ %select1 = call i64 @llvm.smin.i64(i64 %load1, i64 %load2)
+ %load3 = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 16), align 16
+ %select2 = call i64 @llvm.smin.i64(i64 %select1, i64 %load3)
+ %load4 = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 24), align 8
+ %select3 = call i64 @llvm.smin.i64(i64 %select2, i64 %load4)
+ %load5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 32), align 16
+ %select4 = call i64 @llvm.smin.i64(i64 %select3, i64 %load5)
+ %load6 = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 40), align 8
+ %select5 = call i64 @llvm.smin.i64(i64 %select4, i64 %load6)
%store-select = select i1 %cmp1, i64 3, i64 4
store i64 %store-select, ptr @var64, align 8
ret i64 %select5
@@ -197,43 +179,33 @@ define double @dminv6() {
ret double %select5
}
-define i32 @smax_w
diff _valuenum(i32, i32 %v1) {
+define i32 @smax_w
diff _valuenum(i32 %0, i32 %v1) {
; GFX9-LABEL: @smax_w
diff _valuenum(
; GFX9-NEXT: [[VLOAD:%.*]] = load <2 x i32>, ptr @arr, align 16
; GFX9-NEXT: [[ELT1:%.*]] = extractelement <2 x i32> [[VLOAD]], i32 0
; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[ELT1]], [[V1:%.*]]
; GFX9-NEXT: [[EX0:%.*]] = extractelement <2 x i32> [[VLOAD]], i32 0
; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i32 [[EX0]], i32 [[V1]]
-; GFX9-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
+; GFX9-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
; GFX9-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])
-; GFX9-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP3]], [[SELECT1]]
-; GFX9-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP3]], i32 [[SELECT1]]
+; GFX9-NEXT: [[TMP4:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP3]], i32 [[SELECT1]])
; GFX9-NEXT: [[STOREVAL:%.*]] = select i1 [[CMP1]], i32 3, i32 4
; GFX9-NEXT: store i32 [[STOREVAL]], ptr @var, align 8
-; GFX9-NEXT: ret i32 [[OP_RDX1]]
+; GFX9-NEXT: ret i32 [[TMP4]]
;
%vload = load <2 x i32>, ptr @arr, align 16
%elt1 = extractelement <2 x i32> %vload, i32 0
%cmp1 = icmp sgt i32 %elt1, %v1
%ex0 = extractelement <2 x i32> %vload, i32 0
%select1 = select i1 %cmp1, i32 %ex0, i32 %v1
-
- %load3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %cmp2 = icmp sgt i32 %select1, %load3
- %select2 = select i1 %cmp2, i32 %select1, i32 %load3
-
- %load4 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %cmp3 = icmp sgt i32 %select2, %load4
- %select3 = select i1 %cmp3, i32 %select2, i32 %load4
-
- %load5 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %cmp4 = icmp sgt i32 %select3, %load5
- %select4 = select i1 %cmp4, i32 %select3, i32 %load5
-
- %load6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %cmp5 = icmp sgt i32 %select4, %load6
- %select5 = select i1 %cmp5, i32 %select4, i32 %load6
-
+ %load3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %select2 = call i32 @llvm.smax.i32(i32 %select1, i32 %load3)
+ %load4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %select3 = call i32 @llvm.smax.i32(i32 %select2, i32 %load4)
+ %load5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %select4 = call i32 @llvm.smax.i32(i32 %select3, i32 %load5)
+ %load6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %select5 = call i32 @llvm.smax.i32(i32 %select4, i32 %load6)
%storeval = select i1 %cmp1, i32 3, i32 4
store i32 %storeval, ptr @var, align 8
ret i32 %select5
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
index f89a9b6287dae..28a77fcb5aff6 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
@@ -270,12 +270,9 @@ define i16 @reduction_umin_v4i16(<4 x i16> %vec4) {
; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1
; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2
; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3
-; VI-NEXT: [[CMP1:%.*]] = icmp ult i16 [[ELT1]], [[ELT0]]
-; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]
-; VI-NEXT: [[CMP2:%.*]] = icmp ult i16 [[ELT2]], [[MIN1]]
-; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MIN1]]
-; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT3]], [[MIN2]]
-; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
+; VI-NEXT: [[MIN1:%.*]] = call i16 @llvm.umin.i16(i16 [[ELT1]], i16 [[ELT0]])
+; VI-NEXT: [[MIN2:%.*]] = call i16 @llvm.umin.i16(i16 [[ELT2]], i16 [[MIN1]])
+; VI-NEXT: [[MIN3:%.*]] = call i16 @llvm.umin.i16(i16 [[ELT3]], i16 [[MIN2]])
; VI-NEXT: ret i16 [[MIN3]]
;
entry:
@@ -283,48 +280,38 @@ entry:
%elt1 = extractelement <4 x i16> %vec4, i64 1
%elt2 = extractelement <4 x i16> %vec4, i64 2
%elt3 = extractelement <4 x i16> %vec4, i64 3
-
- %cmp1 = icmp ult i16 %elt1, %elt0
- %min1 = select i1 %cmp1, i16 %elt1, i16 %elt0
- %cmp2 = icmp ult i16 %elt2, %min1
- %min2 = select i1 %cmp2, i16 %elt2, i16 %min1
- %cmp3 = icmp ult i16 %elt3, %min2
- %min3 = select i1 %cmp3, i16 %elt3, i16 %min2
-
+ %min1 = call i16 @llvm.umin.i16(i16 %elt1, i16 %elt0)
+ %min2 = call i16 @llvm.umin.i16(i16 %elt2, i16 %min1)
+ %min3 = call i16 @llvm.umin.i16(i16 %elt3, i16 %min2)
ret i16 %min3
}
define i16 @reduction_icmp_v8i16(<8 x i16> %vec8) {
-; GFX9-LABEL: @reduction_icmp_v8i16(
-; GFX9-NEXT: entry:
-; GFX9-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> [[VEC8:%.*]])
-; GFX9-NEXT: ret i16 [[TMP0]]
-;
-; VI-LABEL: @reduction_icmp_v8i16(
-; VI-NEXT: entry:
-; VI-NEXT: [[ELT0:%.*]] = extractelement <8 x i16> [[VEC8:%.*]], i64 0
-; VI-NEXT: [[ELT1:%.*]] = extractelement <8 x i16> [[VEC8]], i64 1
-; VI-NEXT: [[ELT2:%.*]] = extractelement <8 x i16> [[VEC8]], i64 2
-; VI-NEXT: [[ELT3:%.*]] = extractelement <8 x i16> [[VEC8]], i64 3
-; VI-NEXT: [[ELT4:%.*]] = extractelement <8 x i16> [[VEC8]], i64 4
-; VI-NEXT: [[ELT5:%.*]] = extractelement <8 x i16> [[VEC8]], i64 5
-; VI-NEXT: [[ELT6:%.*]] = extractelement <8 x i16> [[VEC8]], i64 6
-; VI-NEXT: [[ELT7:%.*]] = extractelement <8 x i16> [[VEC8]], i64 7
-; VI-NEXT: [[CMP0:%.*]] = icmp ult i16 [[ELT1]], [[ELT0]]
-; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP0]], i16 [[ELT1]], i16 [[ELT0]]
-; VI-NEXT: [[CMP1:%.*]] = icmp ult i16 [[ELT2]], [[MIN1]]
-; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP1]], i16 [[ELT2]], i16 [[MIN1]]
-; VI-NEXT: [[CMP2:%.*]] = icmp ult i16 [[ELT3]], [[MIN2]]
-; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
-; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
-; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
-; VI-NEXT: [[CMP4:%.*]] = icmp ult i16 [[ELT5]], [[MIN4]]
-; VI-NEXT: [[MIN5:%.*]] = select i1 [[CMP4]], i16 [[ELT5]], i16 [[MIN4]]
-; VI-NEXT: [[CMP5:%.*]] = icmp ult i16 [[ELT6]], [[MIN5]]
-; VI-NEXT: [[MIN6:%.*]] = select i1 [[CMP5]], i16 [[ELT6]], i16 [[MIN5]]
-; VI-NEXT: [[CMP6:%.*]] = icmp ult i16 [[ELT7]], [[MIN6]]
-; VI-NEXT: [[MIN7:%.*]] = select i1 [[CMP6]], i16 [[ELT7]], i16 [[MIN6]]
-; VI-NEXT: ret i16 [[MIN7]]
+; GCN-LABEL: @reduction_icmp_v8i16(
+; GCN-NEXT: entry:
+; GCN-NEXT: [[ELT0:%.*]] = extractelement <8 x i16> [[VEC8:%.*]], i64 0
+; GCN-NEXT: [[ELT1:%.*]] = extractelement <8 x i16> [[VEC8]], i64 1
+; GCN-NEXT: [[ELT2:%.*]] = extractelement <8 x i16> [[VEC8]], i64 2
+; GCN-NEXT: [[ELT3:%.*]] = extractelement <8 x i16> [[VEC8]], i64 3
+; GCN-NEXT: [[ELT4:%.*]] = extractelement <8 x i16> [[VEC8]], i64 4
+; GCN-NEXT: [[ELT5:%.*]] = extractelement <8 x i16> [[VEC8]], i64 5
+; GCN-NEXT: [[ELT6:%.*]] = extractelement <8 x i16> [[VEC8]], i64 6
+; GCN-NEXT: [[ELT7:%.*]] = extractelement <8 x i16> [[VEC8]], i64 7
+; GCN-NEXT: [[CMP0:%.*]] = icmp ult i16 [[ELT1]], [[ELT0]]
+; GCN-NEXT: [[MIN1:%.*]] = select i1 [[CMP0]], i16 [[ELT1]], i16 [[ELT0]]
+; GCN-NEXT: [[CMP1:%.*]] = icmp ult i16 [[ELT2]], [[MIN1]]
+; GCN-NEXT: [[MIN2:%.*]] = select i1 [[CMP1]], i16 [[ELT2]], i16 [[MIN1]]
+; GCN-NEXT: [[CMP2:%.*]] = icmp ult i16 [[ELT3]], [[MIN2]]
+; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
+; GCN-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
+; GCN-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
+; GCN-NEXT: [[CMP4:%.*]] = icmp ult i16 [[ELT5]], [[MIN4]]
+; GCN-NEXT: [[MIN5:%.*]] = select i1 [[CMP4]], i16 [[ELT5]], i16 [[MIN4]]
+; GCN-NEXT: [[CMP5:%.*]] = icmp ult i16 [[ELT6]], [[MIN5]]
+; GCN-NEXT: [[MIN6:%.*]] = select i1 [[CMP5]], i16 [[ELT6]], i16 [[MIN5]]
+; GCN-NEXT: [[CMP6:%.*]] = icmp ult i16 [[ELT7]], [[MIN6]]
+; GCN-NEXT: [[MIN7:%.*]] = select i1 [[CMP6]], i16 [[ELT7]], i16 [[MIN6]]
+; GCN-NEXT: ret i16 [[MIN7]]
;
entry:
%elt0 = extractelement <8 x i16> %vec8, i64 0
@@ -380,36 +367,21 @@ define i16 @reduction_smin_v16i16(<16 x i16> %vec16) {
; VI-NEXT: [[ELT13:%.*]] = extractelement <16 x i16> [[VEC16]], i64 13
; VI-NEXT: [[ELT14:%.*]] = extractelement <16 x i16> [[VEC16]], i64 14
; VI-NEXT: [[ELT15:%.*]] = extractelement <16 x i16> [[VEC16]], i64 15
-; VI-NEXT: [[CMP0:%.*]] = icmp slt i16 [[ELT1]], [[ELT0]]
-; VI-NEXT: [[MIN1:%.*]] = select i1 [[CMP0]], i16 [[ELT1]], i16 [[ELT0]]
-; VI-NEXT: [[CMP1:%.*]] = icmp slt i16 [[ELT2]], [[MIN1]]
-; VI-NEXT: [[MIN2:%.*]] = select i1 [[CMP1]], i16 [[ELT2]], i16 [[MIN1]]
-; VI-NEXT: [[CMP2:%.*]] = icmp slt i16 [[ELT3]], [[MIN2]]
-; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
-; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
-; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
-; VI-NEXT: [[CMP4:%.*]] = icmp slt i16 [[ELT5]], [[MIN4]]
-; VI-NEXT: [[MIN5:%.*]] = select i1 [[CMP4]], i16 [[ELT5]], i16 [[MIN4]]
-; VI-NEXT: [[CMP5:%.*]] = icmp slt i16 [[ELT6]], [[MIN5]]
-; VI-NEXT: [[MIN6:%.*]] = select i1 [[CMP5]], i16 [[ELT6]], i16 [[MIN5]]
-; VI-NEXT: [[CMP6:%.*]] = icmp slt i16 [[ELT7]], [[MIN6]]
-; VI-NEXT: [[MIN7:%.*]] = select i1 [[CMP6]], i16 [[ELT7]], i16 [[MIN6]]
-; VI-NEXT: [[CMP7:%.*]] = icmp slt i16 [[ELT8]], [[MIN7]]
-; VI-NEXT: [[MIN8:%.*]] = select i1 [[CMP7]], i16 [[ELT8]], i16 [[MIN7]]
-; VI-NEXT: [[CMP8:%.*]] = icmp slt i16 [[ELT9]], [[MIN8]]
-; VI-NEXT: [[MIN9:%.*]] = select i1 [[CMP8]], i16 [[ELT9]], i16 [[MIN8]]
-; VI-NEXT: [[CMP9:%.*]] = icmp slt i16 [[ELT10]], [[MIN9]]
-; VI-NEXT: [[MIN10:%.*]] = select i1 [[CMP9]], i16 [[ELT10]], i16 [[MIN9]]
-; VI-NEXT: [[CMP10:%.*]] = icmp slt i16 [[ELT11]], [[MIN10]]
-; VI-NEXT: [[MIN11:%.*]] = select i1 [[CMP10]], i16 [[ELT11]], i16 [[MIN10]]
-; VI-NEXT: [[CMP11:%.*]] = icmp slt i16 [[ELT12]], [[MIN11]]
-; VI-NEXT: [[MIN12:%.*]] = select i1 [[CMP11]], i16 [[ELT12]], i16 [[MIN11]]
-; VI-NEXT: [[CMP12:%.*]] = icmp slt i16 [[ELT13]], [[MIN12]]
-; VI-NEXT: [[MIN13:%.*]] = select i1 [[CMP12]], i16 [[ELT13]], i16 [[MIN12]]
-; VI-NEXT: [[CMP13:%.*]] = icmp slt i16 [[ELT14]], [[MIN13]]
-; VI-NEXT: [[MIN14:%.*]] = select i1 [[CMP13]], i16 [[ELT14]], i16 [[MIN13]]
-; VI-NEXT: [[CMP14:%.*]] = icmp slt i16 [[ELT15]], [[MIN14]]
-; VI-NEXT: [[MIN15:%.*]] = select i1 [[CMP14]], i16 [[ELT15]], i16 [[MIN14]]
+; VI-NEXT: [[MIN1:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT1]], i16 [[ELT0]])
+; VI-NEXT: [[MIN2:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT2]], i16 [[MIN1]])
+; VI-NEXT: [[MIN3:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT3]], i16 [[MIN2]])
+; VI-NEXT: [[MIN4:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT4]], i16 [[MIN3]])
+; VI-NEXT: [[MIN5:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT5]], i16 [[MIN4]])
+; VI-NEXT: [[MIN6:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT6]], i16 [[MIN5]])
+; VI-NEXT: [[MIN7:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT7]], i16 [[MIN6]])
+; VI-NEXT: [[MIN8:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT8]], i16 [[MIN7]])
+; VI-NEXT: [[MIN9:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT9]], i16 [[MIN8]])
+; VI-NEXT: [[MIN10:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT10]], i16 [[MIN9]])
+; VI-NEXT: [[MIN11:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT11]], i16 [[MIN10]])
+; VI-NEXT: [[MIN12:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT12]], i16 [[MIN11]])
+; VI-NEXT: [[MIN13:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT13]], i16 [[MIN12]])
+; VI-NEXT: [[MIN14:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT14]], i16 [[MIN13]])
+; VI-NEXT: [[MIN15:%.*]] = call i16 @llvm.smin.i16(i16 [[ELT15]], i16 [[MIN14]])
; VI-NEXT: ret i16 [[MIN15]]
;
entry:
@@ -430,45 +402,21 @@ entry:
%elt13 = extractelement <16 x i16> %vec16, i64 13
%elt14 = extractelement <16 x i16> %vec16, i64 14
%elt15 = extractelement <16 x i16> %vec16, i64 15
-
- %cmp0 = icmp slt i16 %elt1, %elt0
- %min1 = select i1 %cmp0, i16 %elt1, i16 %elt0
- %cmp1 = icmp slt i16 %elt2, %min1
- %min2 = select i1 %cmp1, i16 %elt2, i16 %min1
- %cmp2 = icmp slt i16 %elt3, %min2
- %min3 = select i1 %cmp2, i16 %elt3, i16 %min2
-
- %cmp3 = icmp slt i16 %elt4, %min3
- %min4 = select i1 %cmp3, i16 %elt4, i16 %min3
- %cmp4 = icmp slt i16 %elt5, %min4
- %min5 = select i1 %cmp4, i16 %elt5, i16 %min4
-
- %cmp5 = icmp slt i16 %elt6, %min5
- %min6 = select i1 %cmp5, i16 %elt6, i16 %min5
- %cmp6 = icmp slt i16 %elt7, %min6
- %min7 = select i1 %cmp6, i16 %elt7, i16 %min6
-
- %cmp7 = icmp slt i16 %elt8, %min7
- %min8 = select i1 %cmp7, i16 %elt8, i16 %min7
- %cmp8 = icmp slt i16 %elt9, %min8
- %min9 = select i1 %cmp8, i16 %elt9, i16 %min8
-
- %cmp9 = icmp slt i16 %elt10, %min9
- %min10 = select i1 %cmp9, i16 %elt10, i16 %min9
- %cmp10 = icmp slt i16 %elt11, %min10
- %min11 = select i1 %cmp10, i16 %elt11, i16 %min10
-
- %cmp11 = icmp slt i16 %elt12, %min11
- %min12 = select i1 %cmp11, i16 %elt12, i16 %min11
- %cmp12 = icmp slt i16 %elt13, %min12
- %min13 = select i1 %cmp12, i16 %elt13, i16 %min12
-
- %cmp13 = icmp slt i16 %elt14, %min13
- %min14 = select i1 %cmp13, i16 %elt14, i16 %min13
- %cmp14 = icmp slt i16 %elt15, %min14
- %min15 = select i1 %cmp14, i16 %elt15, i16 %min14
-
-
+ %min1 = call i16 @llvm.smin.i16(i16 %elt1, i16 %elt0)
+ %min2 = call i16 @llvm.smin.i16(i16 %elt2, i16 %min1)
+ %min3 = call i16 @llvm.smin.i16(i16 %elt3, i16 %min2)
+ %min4 = call i16 @llvm.smin.i16(i16 %elt4, i16 %min3)
+ %min5 = call i16 @llvm.smin.i16(i16 %elt5, i16 %min4)
+ %min6 = call i16 @llvm.smin.i16(i16 %elt6, i16 %min5)
+ %min7 = call i16 @llvm.smin.i16(i16 %elt7, i16 %min6)
+ %min8 = call i16 @llvm.smin.i16(i16 %elt8, i16 %min7)
+ %min9 = call i16 @llvm.smin.i16(i16 %elt9, i16 %min8)
+ %min10 = call i16 @llvm.smin.i16(i16 %elt10, i16 %min9)
+ %min11 = call i16 @llvm.smin.i16(i16 %elt11, i16 %min10)
+ %min12 = call i16 @llvm.smin.i16(i16 %elt12, i16 %min11)
+ %min13 = call i16 @llvm.smin.i16(i16 %elt13, i16 %min12)
+ %min14 = call i16 @llvm.smin.i16(i16 %elt14, i16 %min13)
+ %min15 = call i16 @llvm.smin.i16(i16 %elt15, i16 %min14)
ret i16 %min15
}
@@ -484,12 +432,9 @@ define i16 @reduction_umax_v4i16(<4 x i16> %vec4) {
; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1
; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2
; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3
-; VI-NEXT: [[CMP1:%.*]] = icmp ugt i16 [[ELT1]], [[ELT0]]
-; VI-NEXT: [[MAX1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]
-; VI-NEXT: [[CMP2:%.*]] = icmp ugt i16 [[ELT2]], [[MAX1]]
-; VI-NEXT: [[MAX2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MAX1]]
-; VI-NEXT: [[CMP3:%.*]] = icmp ugt i16 [[ELT3]], [[MAX2]]
-; VI-NEXT: [[MAX3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MAX2]]
+; VI-NEXT: [[MAX1:%.*]] = call i16 @llvm.umax.i16(i16 [[ELT1]], i16 [[ELT0]])
+; VI-NEXT: [[MAX2:%.*]] = call i16 @llvm.umax.i16(i16 [[ELT2]], i16 [[MAX1]])
+; VI-NEXT: [[MAX3:%.*]] = call i16 @llvm.umax.i16(i16 [[ELT3]], i16 [[MAX2]])
; VI-NEXT: ret i16 [[MAX3]]
;
entry:
@@ -497,14 +442,9 @@ entry:
%elt1 = extractelement <4 x i16> %vec4, i64 1
%elt2 = extractelement <4 x i16> %vec4, i64 2
%elt3 = extractelement <4 x i16> %vec4, i64 3
-
- %cmp1 = icmp ugt i16 %elt1, %elt0
- %max1 = select i1 %cmp1, i16 %elt1, i16 %elt0
- %cmp2 = icmp ugt i16 %elt2, %max1
- %max2 = select i1 %cmp2, i16 %elt2, i16 %max1
- %cmp3 = icmp ugt i16 %elt3, %max2
- %max3 = select i1 %cmp3, i16 %elt3, i16 %max2
-
+ %max1 = call i16 @llvm.umax.i16(i16 %elt1, i16 %elt0)
+ %max2 = call i16 @llvm.umax.i16(i16 %elt2, i16 %max1)
+ %max3 = call i16 @llvm.umax.i16(i16 %elt3, i16 %max2)
ret i16 %max3
}
@@ -520,12 +460,9 @@ define i16 @reduction_smax_v4i16(<4 x i16> %vec4) {
; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x i16> [[VEC4]], i64 1
; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x i16> [[VEC4]], i64 2
; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x i16> [[VEC4]], i64 3
-; VI-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[ELT1]], [[ELT0]]
-; VI-NEXT: [[MAX1:%.*]] = select i1 [[CMP1]], i16 [[ELT1]], i16 [[ELT0]]
-; VI-NEXT: [[CMP2:%.*]] = icmp sgt i16 [[ELT2]], [[MAX1]]
-; VI-NEXT: [[MAX2:%.*]] = select i1 [[CMP2]], i16 [[ELT2]], i16 [[MAX1]]
-; VI-NEXT: [[CMP3:%.*]] = icmp sgt i16 [[ELT3]], [[MAX2]]
-; VI-NEXT: [[MAX3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MAX2]]
+; VI-NEXT: [[MAX1:%.*]] = call i16 @llvm.smax.i16(i16 [[ELT1]], i16 [[ELT0]])
+; VI-NEXT: [[MAX2:%.*]] = call i16 @llvm.smax.i16(i16 [[ELT2]], i16 [[MAX1]])
+; VI-NEXT: [[MAX3:%.*]] = call i16 @llvm.smax.i16(i16 [[ELT3]], i16 [[MAX2]])
; VI-NEXT: ret i16 [[MAX3]]
;
entry:
@@ -533,14 +470,9 @@ entry:
%elt1 = extractelement <4 x i16> %vec4, i64 1
%elt2 = extractelement <4 x i16> %vec4, i64 2
%elt3 = extractelement <4 x i16> %vec4, i64 3
-
- %cmp1 = icmp sgt i16 %elt1, %elt0
- %max1 = select i1 %cmp1, i16 %elt1, i16 %elt0
- %cmp2 = icmp sgt i16 %elt2, %max1
- %max2 = select i1 %cmp2, i16 %elt2, i16 %max1
- %cmp3 = icmp sgt i16 %elt3, %max2
- %max3 = select i1 %cmp3, i16 %elt3, i16 %max2
-
+ %max1 = call i16 @llvm.smax.i16(i16 %elt1, i16 %elt0)
+ %max2 = call i16 @llvm.smax.i16(i16 %elt2, i16 %max1)
+ %max3 = call i16 @llvm.smax.i16(i16 %elt3, i16 %max2)
ret i16 %max3
}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
index 91ec61b275205..31e4feabd3582 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
@@ -33,8 +33,7 @@ define void @foo(double %i) {
; CHECK-NEXT: [[TMP29:%.*]] = fptosi <4 x double> [[TMP28]] to <4 x i32>
; CHECK-NEXT: [[TMP30:%.*]] = or <4 x i32> zeroinitializer, [[TMP29]]
; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP30]])
-; CHECK-NEXT: [[OP_RDX:%.*]] = icmp slt i32 [[TMP31]], 32000
-; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP31]], i32 32000
+; CHECK-NEXT: [[OP_RDX1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP31]], i32 32000)
; CHECK-NEXT: [[I163:%.*]] = fcmp ogt double [[I118]], 0.000000e+00
; CHECK-NEXT: [[I164:%.*]] = icmp slt i32 0, [[OP_RDX1]]
; CHECK-NEXT: ret void
@@ -105,29 +104,25 @@ bb115:
%i134 = fmul double %i133, 0.000000e+00
%i135 = fptosi double %i134 to i32
%i136 = or i32 0, %i135
- %i137 = icmp slt i32 %i136, 32000
- %i138 = select i1 %i137, i32 %i136, i32 32000
+ %i138 = call i32 @llvm.smin(i32 %i136, i32 32000)
%i139 = select i1 false, double 0.000000e+00, double %i130
%i140 = fmul double %i139, 0.000000e+00
%i141 = fmul double %i140, 0.000000e+00
%i142 = fptosi double %i141 to i32
%i143 = or i32 0, %i142
- %i144 = icmp slt i32 %i143, %i138
- %i145 = select i1 %i144, i32 %i143, i32 %i138
+ %i145 = call i32 @llvm.smin(i32 %i143, i32 %i138)
%i146 = select i1 false, double 0.000000e+00, double %i129
%i147 = fmul double %i146, 0.000000e+00
%i148 = fmul double %i147, 0.000000e+00
%i149 = fptosi double %i148 to i32
%i150 = or i32 0, %i149
- %i151 = icmp slt i32 %i150, %i145
- %i152 = select i1 %i151, i32 %i150, i32 %i145
+ %i152 = call i32 @llvm.smin(i32 %i150, i32 %i145)
%i153 = select i1 false, double 0.000000e+00, double %i126
%i154 = fmul double %i153, 0.000000e+00
%i155 = fmul double %i154, 0.000000e+00
%i156 = fptosi double %i155 to i32
%i157 = or i32 0, %i156
- %i158 = icmp slt i32 %i157, %i152
- %i159 = select i1 %i158, i32 %i157, i32 %i152
+ %i159 = call i32 @llvm.smin(i32 %i157, i32 %i152)
%i163 = fcmp ogt double %i118, 0.000000e+00
%i164 = icmp slt i32 0, %i159
ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
index b2b9363565277..a059c9bdbcbcd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
@@ -24,28 +24,21 @@ define i32 @maxi8(i32) {
; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- ret i32 %23
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %9 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %10 = call i32 @llvm.smax.i32(i32 %8, i32 %9)
+ %11 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %12 = call i32 @llvm.smax.i32(i32 %10, i32 %11)
+ %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %14 = call i32 @llvm.smax.i32(i32 %12, i32 %13)
+ %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %16 = call i32 @llvm.smax.i32(i32 %14, i32 %15)
+ ret i32 %16
}
define i32 @maxi8_store_in(i32) {
@@ -56,29 +49,22 @@ define i32 @maxi8_store_in(i32) {
; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %9 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %10 = call i32 @llvm.smax.i32(i32 %8, i32 %9)
store i32 0, ptr @var, align 8
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- ret i32 %23
+ %11 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %12 = call i32 @llvm.smax.i32(i32 %10, i32 %11)
+ %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %14 = call i32 @llvm.smax.i32(i32 %12, i32 %13)
+ %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %16 = call i32 @llvm.smax.i32(i32 %14, i32 %15)
+ ret i32 %16
}
define i32 @maxi16(i32) {
@@ -88,52 +74,37 @@ define i32 @maxi16(i32) {
; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- %24 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 8), align 16
- %25 = icmp sgt i32 %23, %24
- %26 = select i1 %25, i32 %23, i32 %24
- %27 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 9), align 4
- %28 = icmp sgt i32 %26, %27
- %29 = select i1 %28, i32 %26, i32 %27
- %30 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 10), align 8
- %31 = icmp sgt i32 %29, %30
- %32 = select i1 %31, i32 %29, i32 %30
- %33 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 11), align 4
- %34 = icmp sgt i32 %32, %33
- %35 = select i1 %34, i32 %32, i32 %33
- %36 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 12), align 16
- %37 = icmp sgt i32 %35, %36
- %38 = select i1 %37, i32 %35, i32 %36
- %39 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 13), align 4
- %40 = icmp sgt i32 %38, %39
- %41 = select i1 %40, i32 %38, i32 %39
- %42 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 14), align 8
- %43 = icmp sgt i32 %41, %42
- %44 = select i1 %43, i32 %41, i32 %42
- %45 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 15), align 4
- %46 = icmp sgt i32 %44, %45
- %47 = select i1 %46, i32 %44, i32 %45
- ret i32 %47
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %9 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %10 = call i32 @llvm.smax.i32(i32 %8, i32 %9)
+ %11 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %12 = call i32 @llvm.smax.i32(i32 %10, i32 %11)
+ %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %14 = call i32 @llvm.smax.i32(i32 %12, i32 %13)
+ %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %16 = call i32 @llvm.smax.i32(i32 %14, i32 %15)
+ %17 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 32), align 16
+ %18 = call i32 @llvm.smax.i32(i32 %16, i32 %17)
+ %19 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 36), align 4
+ %20 = call i32 @llvm.smax.i32(i32 %18, i32 %19)
+ %21 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 40), align 8
+ %22 = call i32 @llvm.smax.i32(i32 %20, i32 %21)
+ %23 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 44), align 4
+ %24 = call i32 @llvm.smax.i32(i32 %22, i32 %23)
+ %25 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 48), align 16
+ %26 = call i32 @llvm.smax.i32(i32 %24, i32 %25)
+ %27 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 52), align 4
+ %28 = call i32 @llvm.smax.i32(i32 %26, i32 %27)
+ %29 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 56), align 8
+ %30 = call i32 @llvm.smax.i32(i32 %28, i32 %29)
+ %31 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 60), align 4
+ %32 = call i32 @llvm.smax.i32(i32 %30, i32 %31)
+ ret i32 %32
}
define i32 @maxi32(i32) {
@@ -143,100 +114,69 @@ define i32 @maxi32(i32) {
; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- %24 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 8), align 16
- %25 = icmp sgt i32 %23, %24
- %26 = select i1 %25, i32 %23, i32 %24
- %27 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 9), align 4
- %28 = icmp sgt i32 %26, %27
- %29 = select i1 %28, i32 %26, i32 %27
- %30 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 10), align 8
- %31 = icmp sgt i32 %29, %30
- %32 = select i1 %31, i32 %29, i32 %30
- %33 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 11), align 4
- %34 = icmp sgt i32 %32, %33
- %35 = select i1 %34, i32 %32, i32 %33
- %36 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 12), align 16
- %37 = icmp sgt i32 %35, %36
- %38 = select i1 %37, i32 %35, i32 %36
- %39 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 13), align 4
- %40 = icmp sgt i32 %38, %39
- %41 = select i1 %40, i32 %38, i32 %39
- %42 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 14), align 8
- %43 = icmp sgt i32 %41, %42
- %44 = select i1 %43, i32 %41, i32 %42
- %45 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 15), align 4
- %46 = icmp sgt i32 %44, %45
- %47 = select i1 %46, i32 %44, i32 %45
- %48 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 16), align 16
- %49 = icmp sgt i32 %47, %48
- %50 = select i1 %49, i32 %47, i32 %48
- %51 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 17), align 4
- %52 = icmp sgt i32 %50, %51
- %53 = select i1 %52, i32 %50, i32 %51
- %54 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 18), align 8
- %55 = icmp sgt i32 %53, %54
- %56 = select i1 %55, i32 %53, i32 %54
- %57 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 19), align 4
- %58 = icmp sgt i32 %56, %57
- %59 = select i1 %58, i32 %56, i32 %57
- %60 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 20), align 16
- %61 = icmp sgt i32 %59, %60
- %62 = select i1 %61, i32 %59, i32 %60
- %63 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 21), align 4
- %64 = icmp sgt i32 %62, %63
- %65 = select i1 %64, i32 %62, i32 %63
- %66 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 22), align 8
- %67 = icmp sgt i32 %65, %66
- %68 = select i1 %67, i32 %65, i32 %66
- %69 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 23), align 4
- %70 = icmp sgt i32 %68, %69
- %71 = select i1 %70, i32 %68, i32 %69
- %72 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 24), align 16
- %73 = icmp sgt i32 %71, %72
- %74 = select i1 %73, i32 %71, i32 %72
- %75 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 25), align 4
- %76 = icmp sgt i32 %74, %75
- %77 = select i1 %76, i32 %74, i32 %75
- %78 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 26), align 8
- %79 = icmp sgt i32 %77, %78
- %80 = select i1 %79, i32 %77, i32 %78
- %81 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 27), align 4
- %82 = icmp sgt i32 %80, %81
- %83 = select i1 %82, i32 %80, i32 %81
- %84 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 28), align 16
- %85 = icmp sgt i32 %83, %84
- %86 = select i1 %85, i32 %83, i32 %84
- %87 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 29), align 4
- %88 = icmp sgt i32 %86, %87
- %89 = select i1 %88, i32 %86, i32 %87
- %90 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 30), align 8
- %91 = icmp sgt i32 %89, %90
- %92 = select i1 %91, i32 %89, i32 %90
- %93 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 31), align 4
- %94 = icmp sgt i32 %92, %93
- %95 = select i1 %94, i32 %92, i32 %93
- ret i32 %95
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %9 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %10 = call i32 @llvm.smax.i32(i32 %8, i32 %9)
+ %11 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %12 = call i32 @llvm.smax.i32(i32 %10, i32 %11)
+ %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %14 = call i32 @llvm.smax.i32(i32 %12, i32 %13)
+ %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %16 = call i32 @llvm.smax.i32(i32 %14, i32 %15)
+ %17 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 32), align 16
+ %18 = call i32 @llvm.smax.i32(i32 %16, i32 %17)
+ %19 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 36), align 4
+ %20 = call i32 @llvm.smax.i32(i32 %18, i32 %19)
+ %21 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 40), align 8
+ %22 = call i32 @llvm.smax.i32(i32 %20, i32 %21)
+ %23 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 44), align 4
+ %24 = call i32 @llvm.smax.i32(i32 %22, i32 %23)
+ %25 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 48), align 16
+ %26 = call i32 @llvm.smax.i32(i32 %24, i32 %25)
+ %27 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 52), align 4
+ %28 = call i32 @llvm.smax.i32(i32 %26, i32 %27)
+ %29 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 56), align 8
+ %30 = call i32 @llvm.smax.i32(i32 %28, i32 %29)
+ %31 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 60), align 4
+ %32 = call i32 @llvm.smax.i32(i32 %30, i32 %31)
+ %33 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 64), align 16
+ %34 = call i32 @llvm.smax.i32(i32 %32, i32 %33)
+ %35 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 68), align 4
+ %36 = call i32 @llvm.smax.i32(i32 %34, i32 %35)
+ %37 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 72), align 8
+ %38 = call i32 @llvm.smax.i32(i32 %36, i32 %37)
+ %39 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 76), align 4
+ %40 = call i32 @llvm.smax.i32(i32 %38, i32 %39)
+ %41 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 80), align 16
+ %42 = call i32 @llvm.smax.i32(i32 %40, i32 %41)
+ %43 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 84), align 4
+ %44 = call i32 @llvm.smax.i32(i32 %42, i32 %43)
+ %45 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 88), align 8
+ %46 = call i32 @llvm.smax.i32(i32 %44, i32 %45)
+ %47 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 92), align 4
+ %48 = call i32 @llvm.smax.i32(i32 %46, i32 %47)
+ %49 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 96), align 16
+ %50 = call i32 @llvm.smax.i32(i32 %48, i32 %49)
+ %51 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 100), align 4
+ %52 = call i32 @llvm.smax.i32(i32 %50, i32 %51)
+ %53 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 104), align 8
+ %54 = call i32 @llvm.smax.i32(i32 %52, i32 %53)
+ %55 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 108), align 4
+ %56 = call i32 @llvm.smax.i32(i32 %54, i32 %55)
+ %57 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 112), align 16
+ %58 = call i32 @llvm.smax.i32(i32 %56, i32 %57)
+ %59 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 116), align 4
+ %60 = call i32 @llvm.smax.i32(i32 %58, i32 %59)
+ %61 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 120), align 8
+ %62 = call i32 @llvm.smax.i32(i32 %60, i32 %61)
+ %63 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 124), align 4
+ %64 = call i32 @llvm.smax.i32(i32 %62, i32 %63)
+ ret i32 %64
}
; Note: legacy test - InstCombine creates maxnum intrinsics for fcmp+select with fastmath on the select.
@@ -764,181 +704,108 @@ define float @maxf32(float) {
ret float %95
}
-define i32 @maxi8_mutiple_uses(i32) {
-; DEFAULT-LABEL: @maxi8_mutiple_uses(
-; DEFAULT-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; DEFAULT-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; DEFAULT-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; DEFAULT-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; DEFAULT-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; DEFAULT-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; DEFAULT-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
-; DEFAULT-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP6]])
-; DEFAULT-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP9]], [[TMP7]]
-; DEFAULT-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP9]], i32 [[TMP7]]
-; DEFAULT-NEXT: [[OP_RDX2:%.*]] = icmp sgt i32 [[TMP8]], [[TMP5]]
-; DEFAULT-NEXT: [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[TMP8]], i32 [[TMP5]]
-; DEFAULT-NEXT: [[OP_RDX4:%.*]] = icmp sgt i32 [[OP_RDX1]], [[OP_RDX3]]
-; DEFAULT-NEXT: [[OP_RDX5:%.*]] = select i1 [[OP_RDX4]], i32 [[OP_RDX1]], i32 [[OP_RDX3]]
-; DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP4]], i32 3, i32 4
-; DEFAULT-NEXT: store i32 [[TMP10]], ptr @var, align 8
-; DEFAULT-NEXT: ret i32 [[OP_RDX5]]
-;
-; THRESH-LABEL: @maxi8_mutiple_uses(
-; THRESH-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
-; THRESH-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], [[TMP4]]
-; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i32 [[TMP3]], i32 [[TMP4]]
-; THRESH-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; THRESH-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP7]])
-; THRESH-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; THRESH-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP9]], i32 [[TMP8]], i32 0
-; THRESH-NEXT: [[TMP11:%.*]] = insertelement <2 x i32> [[TMP9]], i32 [[TMP6]], i32 1
-; THRESH-NEXT: [[TMP12:%.*]] = icmp sgt <2 x i32> [[TMP10]], [[TMP11]]
-; THRESH-NEXT: [[TMP13:%.*]] = select <2 x i1> [[TMP12]], <2 x i32> [[TMP10]], <2 x i32> [[TMP11]]
-; THRESH-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP13]], i32 0
-; THRESH-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP13]], i32 1
-; THRESH-NEXT: [[OP_RDX4:%.*]] = icmp sgt i32 [[TMP14]], [[TMP15]]
-; THRESH-NEXT: [[OP_RDX5:%.*]] = select i1 [[OP_RDX4]], i32 [[TMP14]], i32 [[TMP15]]
-; THRESH-NEXT: [[TMP16:%.*]] = select i1 [[TMP5]], i32 3, i32 4
-; THRESH-NEXT: store i32 [[TMP16]], ptr @var, align 8
-; THRESH-NEXT: ret i32 [[OP_RDX5]]
+define i32 @maxi8_mutiple_uses(i32 %0) {
+; CHECK-LABEL: @maxi8_mutiple_uses(
+; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr @arr, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP2]])
+; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 3, i32 4
+; CHECK-NEXT: store i32 [[TMP7]], ptr @var, align 8
+; CHECK-NEXT: ret i32 [[TMP6]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
%4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- %24 = select i1 %4, i32 3, i32 4
- store i32 %24, ptr @var, align 8
- ret i32 %23
+ %5 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %7 = call i32 @llvm.smax.i32(i32 %5, i32 %6)
+ %8 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %9 = call i32 @llvm.smax.i32(i32 %7, i32 %8)
+ %10 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %11 = call i32 @llvm.smax.i32(i32 %9, i32 %10)
+ %12 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %13 = call i32 @llvm.smax.i32(i32 %11, i32 %12)
+ %14 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %15 = call i32 @llvm.smax.i32(i32 %13, i32 %14)
+ %16 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %17 = call i32 @llvm.smax.i32(i32 %15, i32 %16)
+ %18 = select i1 %4, i32 3, i32 4
+ store i32 %18, ptr @var, align 8
+ ret i32 %17
}
-define i32 @maxi8_mutiple_uses2(i32) {
-; DEFAULT-LABEL: @maxi8_mutiple_uses2(
-; DEFAULT-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
-; DEFAULT-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
-; DEFAULT-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
-; DEFAULT-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP2]], i32 [[TMP3]]
-; DEFAULT-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; DEFAULT-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], [[TMP6]]
-; DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP5]], i32 [[TMP6]]
-; DEFAULT-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
-; DEFAULT-NEXT: [[TMP10:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]]
-; DEFAULT-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
-; DEFAULT-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
-; DEFAULT-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]]
-; DEFAULT-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP11]], i32 [[TMP12]]
-; DEFAULT-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
-; DEFAULT-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP14]], [[TMP15]]
-; DEFAULT-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP14]], i32 [[TMP15]]
-; DEFAULT-NEXT: [[TMP18:%.*]] = select i1 [[TMP10]], i32 3, i32 4
-; DEFAULT-NEXT: store i32 [[TMP18]], ptr @var, align 8
-; DEFAULT-NEXT: ret i32 [[TMP17]]
-;
-; THRESH-LABEL: @maxi8_mutiple_uses2(
-; THRESH-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @arr, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; THRESH-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], [[TMP4]]
-; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i32 [[TMP3]], i32 [[TMP4]]
-; THRESH-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; THRESH-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]]
-; THRESH-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP6]], i32 [[TMP7]]
-; THRESH-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
-; THRESH-NEXT: [[TMP11:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
-; THRESH-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 [[TMP9]], i32 [[TMP10]]
-; THRESH-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
-; THRESH-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]]
-; THRESH-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
-; THRESH-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
-; THRESH-NEXT: [[TMP17:%.*]] = icmp sgt i32 [[TMP15]], [[TMP16]]
-; THRESH-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], i32 [[TMP15]], i32 [[TMP16]]
-; THRESH-NEXT: [[TMP19:%.*]] = select i1 [[TMP11]], i32 3, i32 4
-; THRESH-NEXT: store i32 [[TMP19]], ptr @var, align 8
-; THRESH-NEXT: ret i32 [[TMP18]]
+define i32 @maxi8_mutiple_uses2(i32 %0) {
+; CHECK-LABEL: @maxi8_mutiple_uses2(
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @arr, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP4]], i32 [[TMP5]])
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP6]], i32 [[TMP7]])
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP9]], i32 [[TMP10]])
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP11]], i32 [[TMP12]])
+; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP8]], i32 3, i32 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr @var, align 8
+; CHECK-NEXT: ret i32 [[TMP13]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = select i1 %10, i32 3, i32 4
- store i32 %18, ptr @var, align 8
- ret i32 %17
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = icmp sgt i32 %6, %7
+ %9 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %10 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %11 = call i32 @llvm.smax.i32(i32 %9, i32 %10)
+ %12 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %13 = call i32 @llvm.smax.i32(i32 %11, i32 %12)
+ %14 = select i1 %8, i32 3, i32 4
+ store i32 %14, ptr @var, align 8
+ ret i32 %13
}
-define i32 @maxi8_wrong_parent(i32) {
+define i32 @maxi8_wrong_parent(i32 %0) {
; CHECK-LABEL: @maxi8_wrong_parent(
-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @arr, align 16
+; CHECK-NEXT: [[TMP10:%.*]] = load <2 x i32>, ptr @arr, align 16
; CHECK-NEXT: br label [[PP:%.*]]
; CHECK: pp:
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
-; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
-; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP7]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
-; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP10]])
-; CHECK-NEXT: ret i32 [[TMP11]]
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> [[TMP7]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP2]])
+; CHECK-NEXT: ret i32 [[TMP3]]
;
%2 = load i32, ptr @arr, align 16
- %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 1), align 4
- %4 = icmp sgt i32 %2, %3
+ %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 4), align 4
br label %pp
pp:
- %5 = select i1 %4, i32 %2, i32 %3
- %6 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 2), align 8
- %7 = icmp sgt i32 %5, %6
- %8 = select i1 %7, i32 %5, i32 %6
- %9 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 3), align 4
- %10 = icmp sgt i32 %8, %9
- %11 = select i1 %10, i32 %8, i32 %9
- %12 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 4), align 16
- %13 = icmp sgt i32 %11, %12
- %14 = select i1 %13, i32 %11, i32 %12
- %15 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 5), align 4
- %16 = icmp sgt i32 %14, %15
- %17 = select i1 %16, i32 %14, i32 %15
- %18 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 6), align 8
- %19 = icmp sgt i32 %17, %18
- %20 = select i1 %19, i32 %17, i32 %18
- %21 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr, i64 0, i64 7), align 4
- %22 = icmp sgt i32 %20, %21
- %23 = select i1 %22, i32 %20, i32 %21
- ret i32 %23
+ %4 = call i32 @llvm.smax.i32(i32 %2, i32 %3)
+ %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 8), align 8
+ %6 = call i32 @llvm.smax.i32(i32 %4, i32 %5)
+ %7 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 12), align 4
+ %8 = call i32 @llvm.smax.i32(i32 %6, i32 %7)
+ %9 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
+ %10 = call i32 @llvm.smax.i32(i32 %8, i32 %9)
+ %11 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
+ %12 = call i32 @llvm.smax.i32(i32 %10, i32 %11)
+ %13 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 24), align 8
+ %14 = call i32 @llvm.smax.i32(i32 %12, i32 %13)
+ %15 = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 28), align 4
+ %16 = call i32 @llvm.smax.i32(i32 %14, i32 %15)
+ ret i32 %16
}
; PR38191 - We don't handle array-of-pointer reductions.
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
index 35595b79cd708..2e7829a22613e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
@@ -75,16 +75,15 @@ define i32 @horiz_max_multiple_uses(ptr %x, ptr %p) {
; CHECK-NEXT: [[X4:%.*]] = getelementptr [32 x i32], ptr [[X:%.*]], i64 0, i64 4
; CHECK-NEXT: [[X5:%.*]] = getelementptr [32 x i32], ptr [[X]], i64 0, i64 5
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[X]], align 4
-; CHECK-NEXT: [[T4:%.*]] = load i32, ptr [[X4]], align 4
-; CHECK-NEXT: [[T5:%.*]] = load i32, ptr [[X5]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP1]])
-; CHECK-NEXT: [[MAX_ROOT_CMP:%.*]] = icmp sgt i32 [[TMP2]], [[T4]]
-; CHECK-NEXT: [[MAX_ROOT_SEL:%.*]] = select i1 [[MAX_ROOT_CMP]], i32 [[TMP2]], i32 [[T4]]
-; CHECK-NEXT: [[C012345:%.*]] = icmp sgt i32 [[MAX_ROOT_SEL]], [[T5]]
-; CHECK-NEXT: [[T17:%.*]] = select i1 [[C012345]], i32 [[MAX_ROOT_SEL]], i32 [[T5]]
-; CHECK-NEXT: [[THREE_OR_FOUR:%.*]] = select i1 [[MAX_ROOT_CMP]], i32 3, i32 4
+; CHECK-NEXT: [[T6:%.*]] = load i32, ptr [[X4]], align 4
+; CHECK-NEXT: [[T7:%.*]] = load i32, ptr [[X5]], align 4
+; CHECK-NEXT: [[RDX4:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: [[MAX_ROOT_CMP1:%.*]] = icmp sgt i32 [[RDX4]], [[T6]]
+; CHECK-NEXT: [[MAX_ROOT_SEL:%.*]] = select i1 [[MAX_ROOT_CMP1]], i32 [[RDX4]], i32 [[T6]]
+; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.smax.i32(i32 [[MAX_ROOT_SEL]], i32 [[T7]])
+; CHECK-NEXT: [[THREE_OR_FOUR:%.*]] = select i1 [[MAX_ROOT_CMP1]], i32 3, i32 4
; CHECK-NEXT: store i32 [[THREE_OR_FOUR]], ptr [[P:%.*]], align 8
-; CHECK-NEXT: ret i32 [[T17]]
+; CHECK-NEXT: ret i32 [[T18]]
;
%x1 = getelementptr [32 x i32], ptr %x, i64 0, i64 1
%x2 = getelementptr [32 x i32], ptr %x, i64 0, i64 2
@@ -99,16 +98,12 @@ define i32 @horiz_max_multiple_uses(ptr %x, ptr %p) {
%t4 = load i32, ptr %x4
%t5 = load i32, ptr %x5
- %c01 = icmp sgt i32 %t0, %t1
- %s5 = select i1 %c01, i32 %t0, i32 %t1
- %c012 = icmp sgt i32 %s5, %t2
- %t8 = select i1 %c012, i32 %s5, i32 %t2
- %c0123 = icmp sgt i32 %t8, %t3
- %rdx4 = select i1 %c0123, i32 %t8, i32 %t3
+ %s5 = call i32 @llvm.smax(i32 %t0, i32 %t1)
+ %t8 = call i32 @llvm.smax(i32 %s5, i32 %t2)
+ %rdx4 = call i32 @llvm.smax(i32 %t8, i32 %t3)
%MAX_ROOT_CMP = icmp sgt i32 %rdx4, %t4
%MAX_ROOT_SEL = select i1 %MAX_ROOT_CMP, i32 %rdx4, i32 %t4
- %c012345 = icmp sgt i32 %MAX_ROOT_SEL, %t5
- %t17 = select i1 %c012345, i32 %MAX_ROOT_SEL, i32 %t5
+ %t17 = call i32 @llvm.smax(i32 %MAX_ROOT_SEL, i32 %t5)
%three_or_four = select i1 %MAX_ROOT_CMP, i32 3, i32 4
store i32 %three_or_four, ptr %p, align 8
ret i32 %t17
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
index 583b992ff392a..9c00c368bf0bd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
@@ -7,10 +7,9 @@ define void @_Z2azv(ptr %p) local_unnamed_addr {
; CHECK-LABEL: @_Z2azv(
; CHECK-NEXT: for.body.lr.ph:
; CHECK-NEXT: [[DOTSROA_CAST_4:%.*]] = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr [[P:%.*]], i64 4, i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[DOTSROA_CAST_4]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP1]])
-; CHECK-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 0, [[TMP2]]
-; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[DOTSROA_CAST_4]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP0]])
+; CHECK-NEXT: [[OP_RDX1:%.*]] = call i32 @llvm.smax.i32(i32 0, i32 [[TMP2]])
; CHECK-NEXT: [[DOTSROA_SPECULATED_9:%.*]] = select i1 false, i32 0, i32 [[OP_RDX1]]
; CHECK-NEXT: [[CMP_I1_10:%.*]] = icmp slt i32 [[DOTSROA_SPECULATED_9]], 0
; CHECK-NEXT: ret void
@@ -20,36 +19,27 @@ for.body.lr.ph:
%retval.sroa.0.0.copyload.i5.4 = load i32, ptr %.sroa_cast.4, align 4
%.sroa_raw_idx.4 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 4, i32 1
%retval.sroa.0.0.copyload.i7.4 = load i32, ptr %.sroa_raw_idx.4, align 4
- %cmp.i2.4 = icmp slt i32 %retval.sroa.0.0.copyload.i5.4, %retval.sroa.0.0.copyload.i7.4
- %0 = select i1 %cmp.i2.4, i32 %retval.sroa.0.0.copyload.i7.4, i32 %retval.sroa.0.0.copyload.i5.4
- %cmp.i1.4 = icmp slt i32 0, %0
- %.sroa.speculated.4 = select i1 %cmp.i1.4, i32 %0, i32 0
+ %0 = call i32 @llvm.smax(i32 %retval.sroa.0.0.copyload.i7.4, i32 %retval.sroa.0.0.copyload.i5.4)
+ %.sroa.speculated.4 = call i32 @llvm.smax(i32 %0, i32 0)
%.sroa_cast.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 5, i32 0
%retval.sroa.0.0.copyload.i5.5 = load i32, ptr %.sroa_cast.5, align 4
%.sroa_raw_idx.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 5, i32 1
%retval.sroa.0.0.copyload.i7.5 = load i32, ptr %.sroa_raw_idx.5, align 4
- %cmp.i2.5 = icmp slt i32 %retval.sroa.0.0.copyload.i5.5, %retval.sroa.0.0.copyload.i7.5
- %1 = select i1 %cmp.i2.5, i32 %retval.sroa.0.0.copyload.i7.5, i32 %retval.sroa.0.0.copyload.i5.5
- %cmp.i1.5 = icmp slt i32 %.sroa.speculated.4, %1
- %.sroa.speculated.5 = select i1 %cmp.i1.5, i32 %1, i32 %.sroa.speculated.4
+ %1 = call i32 @llvm.smax(i32 %retval.sroa.0.0.copyload.i7.5, i32 %retval.sroa.0.0.copyload.i5.5)
+ %.sroa.speculated.5 = call i32 @llvm.smax(i32 %1, i32 %.sroa.speculated.4)
%.sroa_cast.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 6, i32 0
%retval.sroa.0.0.copyload.i5.6 = load i32, ptr %.sroa_cast.6, align 4
%.sroa_raw_idx.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 6, i32 1
%retval.sroa.0.0.copyload.i7.6 = load i32, ptr %.sroa_raw_idx.6, align 4
- %cmp.i2.6 = icmp slt i32 %retval.sroa.0.0.copyload.i5.6, %retval.sroa.0.0.copyload.i7.6
- %2 = select i1 %cmp.i2.6, i32 %retval.sroa.0.0.copyload.i7.6, i32 %retval.sroa.0.0.copyload.i5.6
- %cmp.i1.6 = icmp slt i32 %.sroa.speculated.5, %2
- %.sroa.speculated.6 = select i1 %cmp.i1.6, i32 %2, i32 %.sroa.speculated.5
+ %2 = call i32 @llvm.smax(i32 %retval.sroa.0.0.copyload.i7.6, i32 %retval.sroa.0.0.copyload.i5.6)
+ %.sroa.speculated.6 = call i32 @llvm.smax(i32 %2, i32 %.sroa.speculated.5)
%.sroa_cast.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 7, i32 0
%retval.sroa.0.0.copyload.i5.7 = load i32, ptr %.sroa_cast.7, align 4
%.sroa_raw_idx.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 7, i32 1
%retval.sroa.0.0.copyload.i7.7 = load i32, ptr %.sroa_raw_idx.7, align 4
- %cmp.i2.7 = icmp slt i32 %retval.sroa.0.0.copyload.i5.7, %retval.sroa.0.0.copyload.i7.7
- %3 = select i1 %cmp.i2.7, i32 %retval.sroa.0.0.copyload.i7.7, i32 %retval.sroa.0.0.copyload.i5.7
- %cmp.i1.7 = icmp slt i32 %.sroa.speculated.6, %3
- %.sroa.speculated.7 = select i1 %cmp.i1.7, i32 %3, i32 %.sroa.speculated.6
- %cmp.i1.8 = icmp slt i32 %.sroa.speculated.7, 0
- %.sroa.speculated.8 = select i1 %cmp.i1.8, i32 0, i32 %.sroa.speculated.7
+ %3 = call i32 @llvm.smax(i32 %retval.sroa.0.0.copyload.i7.7, i32 %retval.sroa.0.0.copyload.i5.7)
+ %.sroa.speculated.7 = call i32 @llvm.smax(i32 %3, i32 %.sroa.speculated.6)
+ %.sroa.speculated.8 = call i32 @llvm.smax(i32 0, i32 %.sroa.speculated.7)
%.sroa.speculated.9 = select i1 0, i32 0, i32 %.sroa.speculated.8
%cmp.i1.10 = icmp slt i32 %.sroa.speculated.9, 0
ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
index eef0e092200b3..e5fba188a5be3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
@@ -8,136 +8,146 @@
define void @n() local_unnamed_addr #0 {
; CHECK-LABEL: @n(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load <32 x i32>, ptr @k, align 16
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @k, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 1, i64 0), align 16
+; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 2, i64 0), align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 3, i64 0), align 16
+; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 4, i64 0), align 16
+; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 5, i64 0), align 16
+; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 6, i64 0), align 16
+; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x [4 x i32]], ptr @k, i64 0, i64 7, i64 0), align 16
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_COND]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[B_0:%.*]] = phi i32 [ [[SPEC_SELECT8_3_7:%.*]], [[FOR_COND]] ], [ undef, [[ENTRY]] ]
; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP29]], -183
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <32 x i32> poison, i32 [[TMP30]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <32 x i32> [[TMP3]], <32 x i32> poison, <32 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP5:%.*]] = sub <32 x i32> [[TMP4]], [[TMP0]]
-; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <32 x i32> [[TMP5]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <32 x i32> zeroinitializer, [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = select <32 x i1> [[TMP6]], <32 x i32> [[TMP7]], <32 x i32> [[TMP5]]
-; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <32 x i32> [[TMP8]], <32 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP30]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP12:%.*]] = sub <4 x i32> [[TMP11]], [[TMP0]]
+; CHECK-NEXT: [[TMP9:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP12]], i1 true)
; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP9]])
-; CHECK-NEXT: [[OP_RDX:%.*]] = icmp slt i32 [[TMP37]], [[B_0]]
-; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP37]], i32 [[B_0]]
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <32 x i32> [[TMP8]], i32 4
-; CHECK-NEXT: [[CMP12_118:%.*]] = icmp slt i32 [[TMP13]], [[OP_RDX1]]
-; CHECK-NEXT: [[SPEC_SELECT8_120:%.*]] = select i1 [[CMP12_118]], i32 [[TMP13]], i32 [[OP_RDX1]]
-; CHECK-NEXT: [[TMP41:%.*]] = extractelement <32 x i32> [[TMP8]], i32 5
-; CHECK-NEXT: [[CMP12_1_1:%.*]] = icmp slt i32 [[TMP41]], [[SPEC_SELECT8_120]]
-; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CMP12_1_1]], [[CMP12_118]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_1:%.*]] = select i1 [[CMP12_1_1]], i32 [[TMP41]], i32 [[SPEC_SELECT8_120]]
-; CHECK-NEXT: [[TMP43:%.*]] = extractelement <32 x i32> [[TMP8]], i32 6
-; CHECK-NEXT: [[CMP12_2_1:%.*]] = icmp slt i32 [[TMP43]], [[SPEC_SELECT8_1_1]]
-; CHECK-NEXT: [[NARROW34:%.*]] = or i1 [[CMP12_2_1]], [[NARROW]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_1:%.*]] = select i1 [[CMP12_2_1]], i32 [[TMP43]], i32 [[SPEC_SELECT8_1_1]]
-; CHECK-NEXT: [[TMP45:%.*]] = extractelement <32 x i32> [[TMP8]], i32 7
-; CHECK-NEXT: [[CMP12_3_1:%.*]] = icmp slt i32 [[TMP45]], [[SPEC_SELECT8_2_1]]
-; CHECK-NEXT: [[NARROW35:%.*]] = or i1 [[CMP12_3_1]], [[NARROW34]]
+; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP37]], i32 [[B_0]])
+; CHECK-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP11]], [[TMP1]]
+; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP16]], i1 true)
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[TMP17]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_120:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP18]], i32 [[TMP15]])
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP17]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP19]], i32 [[SPEC_SELECT8_120]])
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP17]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP20]], i32 [[SPEC_SELECT8_1_1]])
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> poison, i32 [[TMP15]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[SPEC_SELECT8_120]], i32 1
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[SPEC_SELECT8_1_1]], i32 2
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[SPEC_SELECT8_2_1]], i32 3
+; CHECK-NEXT: [[TMP25:%.*]] = icmp slt <4 x i32> [[TMP17]], [[TMP24]]
+; CHECK-NEXT: [[NARROW35:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP25]])
; CHECK-NEXT: [[SPEC_SELECT_3_1:%.*]] = zext i1 [[NARROW35]] to i32
-; CHECK-NEXT: [[SPEC_SELECT8_3_1:%.*]] = select i1 [[CMP12_3_1]], i32 [[TMP45]], i32 [[SPEC_SELECT8_2_1]]
-; CHECK-NEXT: [[TMP47:%.*]] = extractelement <32 x i32> [[TMP8]], i32 8
-; CHECK-NEXT: [[CMP12_224:%.*]] = icmp slt i32 [[TMP47]], [[SPEC_SELECT8_3_1]]
-; CHECK-NEXT: [[SPEC_SELECT8_226:%.*]] = select i1 [[CMP12_224]], i32 [[TMP47]], i32 [[SPEC_SELECT8_3_1]]
-; CHECK-NEXT: [[TMP49:%.*]] = extractelement <32 x i32> [[TMP8]], i32 9
-; CHECK-NEXT: [[CMP12_1_2:%.*]] = icmp slt i32 [[TMP49]], [[SPEC_SELECT8_226]]
-; CHECK-NEXT: [[TMP50:%.*]] = or i1 [[CMP12_1_2]], [[CMP12_224]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_2:%.*]] = select i1 [[CMP12_1_2]], i32 [[TMP49]], i32 [[SPEC_SELECT8_226]]
-; CHECK-NEXT: [[TMP52:%.*]] = extractelement <32 x i32> [[TMP8]], i32 10
-; CHECK-NEXT: [[CMP12_2_2:%.*]] = icmp slt i32 [[TMP52]], [[SPEC_SELECT8_1_2]]
-; CHECK-NEXT: [[TMP53:%.*]] = or i1 [[CMP12_2_2]], [[TMP50]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_2:%.*]] = select i1 [[CMP12_2_2]], i32 [[TMP52]], i32 [[SPEC_SELECT8_1_2]]
-; CHECK-NEXT: [[TMP55:%.*]] = extractelement <32 x i32> [[TMP8]], i32 11
-; CHECK-NEXT: [[CMP12_3_2:%.*]] = icmp slt i32 [[TMP55]], [[SPEC_SELECT8_2_2]]
-; CHECK-NEXT: [[TMP56:%.*]] = or i1 [[CMP12_3_2]], [[TMP53]]
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP17]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP27]], i32 [[SPEC_SELECT8_2_1]])
+; CHECK-NEXT: [[TMP28:%.*]] = sub <4 x i32> [[TMP11]], [[TMP2]]
+; CHECK-NEXT: [[TMP38:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP28]], i1 true)
+; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[TMP38]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_226:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP50]], i32 [[SPEC_SELECT8_3_1]])
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP38]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP31]], i32 [[SPEC_SELECT8_226]])
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP38]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP32]], i32 [[SPEC_SELECT8_1_2]])
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_1]], i32 0
+; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP33]], i32 [[SPEC_SELECT8_226]], i32 1
+; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[SPEC_SELECT8_1_2]], i32 2
+; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP35]], i32 [[SPEC_SELECT8_2_2]], i32 3
+; CHECK-NEXT: [[TMP62:%.*]] = icmp slt <4 x i32> [[TMP38]], [[TMP36]]
+; CHECK-NEXT: [[TMP56:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP62]])
; CHECK-NEXT: [[SPEC_SELECT_3_2:%.*]] = select i1 [[TMP56]], i32 2, i32 [[SPEC_SELECT_3_1]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_2:%.*]] = select i1 [[CMP12_3_2]], i32 [[TMP55]], i32 [[SPEC_SELECT8_2_2]]
-; CHECK-NEXT: [[TMP58:%.*]] = extractelement <32 x i32> [[TMP8]], i32 12
-; CHECK-NEXT: [[CMP12_330:%.*]] = icmp slt i32 [[TMP58]], [[SPEC_SELECT8_3_2]]
-; CHECK-NEXT: [[SPEC_SELECT8_332:%.*]] = select i1 [[CMP12_330]], i32 [[TMP58]], i32 [[SPEC_SELECT8_3_2]]
-; CHECK-NEXT: [[TMP60:%.*]] = extractelement <32 x i32> [[TMP8]], i32 13
-; CHECK-NEXT: [[CMP12_1_3:%.*]] = icmp slt i32 [[TMP60]], [[SPEC_SELECT8_332]]
-; CHECK-NEXT: [[TMP61:%.*]] = or i1 [[CMP12_1_3]], [[CMP12_330]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_3:%.*]] = select i1 [[CMP12_1_3]], i32 [[TMP60]], i32 [[SPEC_SELECT8_332]]
-; CHECK-NEXT: [[TMP63:%.*]] = extractelement <32 x i32> [[TMP8]], i32 14
-; CHECK-NEXT: [[CMP12_2_3:%.*]] = icmp slt i32 [[TMP63]], [[SPEC_SELECT8_1_3]]
-; CHECK-NEXT: [[TMP64:%.*]] = or i1 [[CMP12_2_3]], [[TMP61]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_3:%.*]] = select i1 [[CMP12_2_3]], i32 [[TMP63]], i32 [[SPEC_SELECT8_1_3]]
-; CHECK-NEXT: [[TMP66:%.*]] = extractelement <32 x i32> [[TMP8]], i32 15
-; CHECK-NEXT: [[CMP12_3_3:%.*]] = icmp slt i32 [[TMP66]], [[SPEC_SELECT8_2_3]]
-; CHECK-NEXT: [[TMP67:%.*]] = or i1 [[CMP12_3_3]], [[TMP64]]
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP38]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP39]], i32 [[SPEC_SELECT8_2_2]])
+; CHECK-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP11]], [[TMP3]]
+; CHECK-NEXT: [[TMP41:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP40]], i1 true)
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[TMP41]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_332:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP42]], i32 [[SPEC_SELECT8_3_2]])
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[TMP41]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP43]], i32 [[SPEC_SELECT8_332]])
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[TMP41]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP44]], i32 [[SPEC_SELECT8_1_3]])
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_2]], i32 0
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[SPEC_SELECT8_332]], i32 1
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[SPEC_SELECT8_1_3]], i32 2
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP47]], i32 [[SPEC_SELECT8_2_3]], i32 3
+; CHECK-NEXT: [[TMP49:%.*]] = icmp slt <4 x i32> [[TMP41]], [[TMP48]]
+; CHECK-NEXT: [[TMP67:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP49]])
; CHECK-NEXT: [[SPEC_SELECT_3_3:%.*]] = select i1 [[TMP67]], i32 3, i32 [[SPEC_SELECT_3_2]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_3:%.*]] = select i1 [[CMP12_3_3]], i32 [[TMP66]], i32 [[SPEC_SELECT8_2_3]]
-; CHECK-NEXT: [[TMP69:%.*]] = extractelement <32 x i32> [[TMP8]], i32 16
-; CHECK-NEXT: [[CMP12_4:%.*]] = icmp slt i32 [[TMP69]], [[SPEC_SELECT8_3_3]]
-; CHECK-NEXT: [[SPEC_SELECT8_4:%.*]] = select i1 [[CMP12_4]], i32 [[TMP69]], i32 [[SPEC_SELECT8_3_3]]
-; CHECK-NEXT: [[TMP71:%.*]] = extractelement <32 x i32> [[TMP8]], i32 17
-; CHECK-NEXT: [[CMP12_1_4:%.*]] = icmp slt i32 [[TMP71]], [[SPEC_SELECT8_4]]
-; CHECK-NEXT: [[TMP72:%.*]] = or i1 [[CMP12_1_4]], [[CMP12_4]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_4:%.*]] = select i1 [[CMP12_1_4]], i32 [[TMP71]], i32 [[SPEC_SELECT8_4]]
-; CHECK-NEXT: [[TMP74:%.*]] = extractelement <32 x i32> [[TMP8]], i32 18
-; CHECK-NEXT: [[CMP12_2_4:%.*]] = icmp slt i32 [[TMP74]], [[SPEC_SELECT8_1_4]]
-; CHECK-NEXT: [[TMP75:%.*]] = or i1 [[CMP12_2_4]], [[TMP72]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_4:%.*]] = select i1 [[CMP12_2_4]], i32 [[TMP74]], i32 [[SPEC_SELECT8_1_4]]
-; CHECK-NEXT: [[TMP77:%.*]] = extractelement <32 x i32> [[TMP8]], i32 19
-; CHECK-NEXT: [[CMP12_3_4:%.*]] = icmp slt i32 [[TMP77]], [[SPEC_SELECT8_2_4]]
-; CHECK-NEXT: [[TMP78:%.*]] = or i1 [[CMP12_3_4]], [[TMP75]]
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP41]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP51]], i32 [[SPEC_SELECT8_2_3]])
+; CHECK-NEXT: [[TMP52:%.*]] = sub <4 x i32> [[TMP11]], [[TMP4]]
+; CHECK-NEXT: [[TMP53:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP52]], i1 true)
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[TMP53]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP54]], i32 [[SPEC_SELECT8_3_3]])
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x i32> [[TMP53]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP55]], i32 [[SPEC_SELECT8_4]])
+; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i32> [[TMP53]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP74]], i32 [[SPEC_SELECT8_1_4]])
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_3]], i32 0
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <4 x i32> [[TMP57]], i32 [[SPEC_SELECT8_4]], i32 1
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x i32> [[TMP58]], i32 [[SPEC_SELECT8_1_4]], i32 2
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP59]], i32 [[SPEC_SELECT8_2_4]], i32 3
+; CHECK-NEXT: [[TMP61:%.*]] = icmp slt <4 x i32> [[TMP53]], [[TMP60]]
+; CHECK-NEXT: [[TMP78:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP61]])
; CHECK-NEXT: [[SPEC_SELECT_3_4:%.*]] = select i1 [[TMP78]], i32 4, i32 [[SPEC_SELECT_3_3]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_4:%.*]] = select i1 [[CMP12_3_4]], i32 [[TMP77]], i32 [[SPEC_SELECT8_2_4]]
-; CHECK-NEXT: [[TMP80:%.*]] = extractelement <32 x i32> [[TMP8]], i32 20
-; CHECK-NEXT: [[CMP12_5:%.*]] = icmp slt i32 [[TMP80]], [[SPEC_SELECT8_3_4]]
-; CHECK-NEXT: [[SPEC_SELECT8_5:%.*]] = select i1 [[CMP12_5]], i32 [[TMP80]], i32 [[SPEC_SELECT8_3_4]]
-; CHECK-NEXT: [[TMP82:%.*]] = extractelement <32 x i32> [[TMP8]], i32 21
-; CHECK-NEXT: [[CMP12_1_5:%.*]] = icmp slt i32 [[TMP82]], [[SPEC_SELECT8_5]]
-; CHECK-NEXT: [[TMP83:%.*]] = or i1 [[CMP12_1_5]], [[CMP12_5]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_5:%.*]] = select i1 [[CMP12_1_5]], i32 [[TMP82]], i32 [[SPEC_SELECT8_5]]
-; CHECK-NEXT: [[TMP85:%.*]] = extractelement <32 x i32> [[TMP8]], i32 22
-; CHECK-NEXT: [[CMP12_2_5:%.*]] = icmp slt i32 [[TMP85]], [[SPEC_SELECT8_1_5]]
-; CHECK-NEXT: [[TMP86:%.*]] = or i1 [[CMP12_2_5]], [[TMP83]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_5:%.*]] = select i1 [[CMP12_2_5]], i32 [[TMP85]], i32 [[SPEC_SELECT8_1_5]]
-; CHECK-NEXT: [[TMP88:%.*]] = extractelement <32 x i32> [[TMP8]], i32 23
-; CHECK-NEXT: [[CMP12_3_5:%.*]] = icmp slt i32 [[TMP88]], [[SPEC_SELECT8_2_5]]
-; CHECK-NEXT: [[TMP89:%.*]] = or i1 [[CMP12_3_5]], [[TMP86]]
+; CHECK-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP53]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP63]], i32 [[SPEC_SELECT8_2_4]])
+; CHECK-NEXT: [[TMP64:%.*]] = sub <4 x i32> [[TMP11]], [[TMP5]]
+; CHECK-NEXT: [[TMP65:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP64]], i1 true)
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <4 x i32> [[TMP65]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP66]], i32 [[SPEC_SELECT8_3_4]])
+; CHECK-NEXT: [[TMP86:%.*]] = extractelement <4 x i32> [[TMP65]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP86]], i32 [[SPEC_SELECT8_5]])
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <4 x i32> [[TMP65]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP68]], i32 [[SPEC_SELECT8_1_5]])
+; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_4]], i32 0
+; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i32> [[TMP69]], i32 [[SPEC_SELECT8_5]], i32 1
+; CHECK-NEXT: [[TMP71:%.*]] = insertelement <4 x i32> [[TMP70]], i32 [[SPEC_SELECT8_1_5]], i32 2
+; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP71]], i32 [[SPEC_SELECT8_2_5]], i32 3
+; CHECK-NEXT: [[TMP73:%.*]] = icmp slt <4 x i32> [[TMP65]], [[TMP72]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP73]])
; CHECK-NEXT: [[SPEC_SELECT_3_5:%.*]] = select i1 [[TMP89]], i32 5, i32 [[SPEC_SELECT_3_4]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_5:%.*]] = select i1 [[CMP12_3_5]], i32 [[TMP88]], i32 [[SPEC_SELECT8_2_5]]
-; CHECK-NEXT: [[TMP91:%.*]] = extractelement <32 x i32> [[TMP8]], i32 24
-; CHECK-NEXT: [[CMP12_6:%.*]] = icmp slt i32 [[TMP91]], [[SPEC_SELECT8_3_5]]
-; CHECK-NEXT: [[SPEC_SELECT8_6:%.*]] = select i1 [[CMP12_6]], i32 [[TMP91]], i32 [[SPEC_SELECT8_3_5]]
-; CHECK-NEXT: [[TMP93:%.*]] = extractelement <32 x i32> [[TMP8]], i32 25
-; CHECK-NEXT: [[CMP12_1_6:%.*]] = icmp slt i32 [[TMP93]], [[SPEC_SELECT8_6]]
-; CHECK-NEXT: [[TMP94:%.*]] = or i1 [[CMP12_1_6]], [[CMP12_6]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_6:%.*]] = select i1 [[CMP12_1_6]], i32 [[TMP93]], i32 [[SPEC_SELECT8_6]]
-; CHECK-NEXT: [[TMP96:%.*]] = extractelement <32 x i32> [[TMP8]], i32 26
-; CHECK-NEXT: [[CMP12_2_6:%.*]] = icmp slt i32 [[TMP96]], [[SPEC_SELECT8_1_6]]
-; CHECK-NEXT: [[TMP97:%.*]] = or i1 [[CMP12_2_6]], [[TMP94]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_6:%.*]] = select i1 [[CMP12_2_6]], i32 [[TMP96]], i32 [[SPEC_SELECT8_1_6]]
-; CHECK-NEXT: [[TMP99:%.*]] = extractelement <32 x i32> [[TMP8]], i32 27
-; CHECK-NEXT: [[CMP12_3_6:%.*]] = icmp slt i32 [[TMP99]], [[SPEC_SELECT8_2_6]]
-; CHECK-NEXT: [[TMP100:%.*]] = or i1 [[CMP12_3_6]], [[TMP97]]
+; CHECK-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP65]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP75]], i32 [[SPEC_SELECT8_2_5]])
+; CHECK-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP11]], [[TMP6]]
+; CHECK-NEXT: [[TMP77:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP76]], i1 true)
+; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[TMP77]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP98]], i32 [[SPEC_SELECT8_3_5]])
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i32> [[TMP77]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP79]], i32 [[SPEC_SELECT8_6]])
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <4 x i32> [[TMP77]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP80]], i32 [[SPEC_SELECT8_1_6]])
+; CHECK-NEXT: [[TMP81:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_5]], i32 0
+; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP81]], i32 [[SPEC_SELECT8_6]], i32 1
+; CHECK-NEXT: [[TMP83:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[SPEC_SELECT8_1_6]], i32 2
+; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP83]], i32 [[SPEC_SELECT8_2_6]], i32 3
+; CHECK-NEXT: [[TMP85:%.*]] = icmp slt <4 x i32> [[TMP77]], [[TMP84]]
+; CHECK-NEXT: [[TMP100:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP85]])
; CHECK-NEXT: [[SPEC_SELECT_3_6:%.*]] = select i1 [[TMP100]], i32 6, i32 [[SPEC_SELECT_3_5]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_6:%.*]] = select i1 [[CMP12_3_6]], i32 [[TMP99]], i32 [[SPEC_SELECT8_2_6]]
-; CHECK-NEXT: [[TMP102:%.*]] = extractelement <32 x i32> [[TMP8]], i32 28
-; CHECK-NEXT: [[CMP12_7:%.*]] = icmp slt i32 [[TMP102]], [[SPEC_SELECT8_3_6]]
-; CHECK-NEXT: [[SPEC_SELECT8_7:%.*]] = select i1 [[CMP12_7]], i32 [[TMP102]], i32 [[SPEC_SELECT8_3_6]]
-; CHECK-NEXT: [[TMP104:%.*]] = extractelement <32 x i32> [[TMP8]], i32 29
-; CHECK-NEXT: [[CMP12_1_7:%.*]] = icmp slt i32 [[TMP104]], [[SPEC_SELECT8_7]]
-; CHECK-NEXT: [[TMP105:%.*]] = or i1 [[CMP12_1_7]], [[CMP12_7]]
-; CHECK-NEXT: [[SPEC_SELECT8_1_7:%.*]] = select i1 [[CMP12_1_7]], i32 [[TMP104]], i32 [[SPEC_SELECT8_7]]
-; CHECK-NEXT: [[TMP107:%.*]] = extractelement <32 x i32> [[TMP8]], i32 30
-; CHECK-NEXT: [[CMP12_2_7:%.*]] = icmp slt i32 [[TMP107]], [[SPEC_SELECT8_1_7]]
-; CHECK-NEXT: [[TMP108:%.*]] = or i1 [[CMP12_2_7]], [[TMP105]]
-; CHECK-NEXT: [[SPEC_SELECT8_2_7:%.*]] = select i1 [[CMP12_2_7]], i32 [[TMP107]], i32 [[SPEC_SELECT8_1_7]]
-; CHECK-NEXT: [[TMP110:%.*]] = extractelement <32 x i32> [[TMP8]], i32 31
-; CHECK-NEXT: [[CMP12_3_7:%.*]] = icmp slt i32 [[TMP110]], [[SPEC_SELECT8_2_7]]
-; CHECK-NEXT: [[TMP111:%.*]] = or i1 [[CMP12_3_7]], [[TMP108]]
+; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP77]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP87]], i32 [[SPEC_SELECT8_2_6]])
+; CHECK-NEXT: [[TMP88:%.*]] = sub <4 x i32> [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP101:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP88]], i1 true)
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <4 x i32> [[TMP101]], i32 0
+; CHECK-NEXT: [[SPEC_SELECT8_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP90]], i32 [[SPEC_SELECT8_3_6]])
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <4 x i32> [[TMP101]], i32 1
+; CHECK-NEXT: [[SPEC_SELECT8_1_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP91]], i32 [[SPEC_SELECT8_7]])
+; CHECK-NEXT: [[TMP92:%.*]] = extractelement <4 x i32> [[TMP101]], i32 2
+; CHECK-NEXT: [[SPEC_SELECT8_2_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP92]], i32 [[SPEC_SELECT8_1_7]])
+; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_6]], i32 0
+; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[SPEC_SELECT8_7]], i32 1
+; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[SPEC_SELECT8_1_7]], i32 2
+; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP95]], i32 [[SPEC_SELECT8_2_7]], i32 3
+; CHECK-NEXT: [[TMP97:%.*]] = icmp slt <4 x i32> [[TMP101]], [[TMP96]]
+; CHECK-NEXT: [[TMP111:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP97]])
; CHECK-NEXT: [[SPEC_SELECT_3_7:%.*]] = select i1 [[TMP111]], i32 7, i32 [[SPEC_SELECT_3_6]]
-; CHECK-NEXT: [[SPEC_SELECT8_3_7]] = select i1 [[CMP12_3_7]], i32 [[TMP110]], i32 [[SPEC_SELECT8_2_7]]
-; CHECK-NEXT: [[K:%.*]] = getelementptr inbounds [366 x i32], ptr @l, i64 0, i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP101]], i32 3
+; CHECK-NEXT: [[SPEC_SELECT8_3_7]] = call i32 @llvm.smin.i32(i32 [[TMP99]], i32 [[SPEC_SELECT8_2_7]])
+; CHECK-NEXT: [[K:%.*]] = getelementptr inbounds [4 x i8], ptr @l, i64 [[INDVARS_IV]]
; CHECK-NEXT: store i32 [[SPEC_SELECT_3_7]], ptr [[K]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
; CHECK-NEXT: br label [[FOR_COND]]
@@ -183,228 +193,159 @@ for.cond: ; preds = %for.cond, %entry
%32 = trunc i64 %indvars.iv to i32
%33 = add i32 %32, -183
%sub = sub i32 %33, %0
- %34 = icmp slt i32 %sub, 0
- %neg = sub nsw i32 0, %sub
- %35 = select i1 %34, i32 %neg, i32 %sub
- %cmp12 = icmp slt i32 %35, %b.0
- %spec.select8 = select i1 %cmp12, i32 %35, i32 %b.0
+ %34 = call i32 @llvm.abs.i32(i32 %sub, i1 true)
+ %spec.select8 = call i32 @llvm.smin.i32(i32 %34, i32 %b.0)
%sub.1 = sub i32 %33, %1
- %36 = icmp slt i32 %sub.1, 0
- %neg.1 = sub nsw i32 0, %sub.1
- %37 = select i1 %36, i32 %neg.1, i32 %sub.1
- %cmp12.1 = icmp slt i32 %37, %spec.select8
- %spec.select8.1 = select i1 %cmp12.1, i32 %37, i32 %spec.select8
+ %35 = call i32 @llvm.abs.i32(i32 %sub.1, i1 true)
+ %spec.select8.1 = call i32 @llvm.smin.i32(i32 %35, i32 %spec.select8)
%sub.2 = sub i32 %33, %2
- %38 = icmp slt i32 %sub.2, 0
- %neg.2 = sub nsw i32 0, %sub.2
- %39 = select i1 %38, i32 %neg.2, i32 %sub.2
- %cmp12.2 = icmp slt i32 %39, %spec.select8.1
- %spec.select8.2 = select i1 %cmp12.2, i32 %39, i32 %spec.select8.1
+ %36 = call i32 @llvm.abs.i32(i32 %sub.2, i1 true)
+ %spec.select8.2 = call i32 @llvm.smin.i32(i32 %36, i32 %spec.select8.1)
%sub.3 = sub i32 %33, %3
- %40 = icmp slt i32 %sub.3, 0
- %neg.3 = sub nsw i32 0, %sub.3
- %41 = select i1 %40, i32 %neg.3, i32 %sub.3
- %cmp12.3 = icmp slt i32 %41, %spec.select8.2
- %spec.select8.3 = select i1 %cmp12.3, i32 %41, i32 %spec.select8.2
+ %37 = call i32 @llvm.abs.i32(i32 %sub.3, i1 true)
+ %spec.select8.3 = call i32 @llvm.smin.i32(i32 %37, i32 %spec.select8.2)
%sub.116 = sub i32 %33, %4
- %42 = icmp slt i32 %sub.116, 0
- %neg.117 = sub nsw i32 0, %sub.116
- %43 = select i1 %42, i32 %neg.117, i32 %sub.116
- %cmp12.118 = icmp slt i32 %43, %spec.select8.3
- %spec.select8.120 = select i1 %cmp12.118, i32 %43, i32 %spec.select8.3
+ %38 = call i32 @llvm.abs.i32(i32 %sub.116, i1 true)
+ %cmp12.118 = icmp slt i32 %38, %spec.select8.3
+ %spec.select8.120 = call i32 @llvm.smin.i32(i32 %38, i32 %spec.select8.3)
%sub.1.1 = sub i32 %33, %5
- %44 = icmp slt i32 %sub.1.1, 0
- %neg.1.1 = sub nsw i32 0, %sub.1.1
- %45 = select i1 %44, i32 %neg.1.1, i32 %sub.1.1
- %cmp12.1.1 = icmp slt i32 %45, %spec.select8.120
+ %39 = call i32 @llvm.abs.i32(i32 %sub.1.1, i1 true)
+ %cmp12.1.1 = icmp slt i32 %39, %spec.select8.120
%narrow = or i1 %cmp12.1.1, %cmp12.118
- %spec.select8.1.1 = select i1 %cmp12.1.1, i32 %45, i32 %spec.select8.120
+ %spec.select8.1.1 = call i32 @llvm.smin.i32(i32 %39, i32 %spec.select8.120)
%sub.2.1 = sub i32 %33, %6
- %46 = icmp slt i32 %sub.2.1, 0
- %neg.2.1 = sub nsw i32 0, %sub.2.1
- %47 = select i1 %46, i32 %neg.2.1, i32 %sub.2.1
- %cmp12.2.1 = icmp slt i32 %47, %spec.select8.1.1
+ %40 = call i32 @llvm.abs.i32(i32 %sub.2.1, i1 true)
+ %cmp12.2.1 = icmp slt i32 %40, %spec.select8.1.1
%narrow34 = or i1 %cmp12.2.1, %narrow
- %spec.select8.2.1 = select i1 %cmp12.2.1, i32 %47, i32 %spec.select8.1.1
+ %spec.select8.2.1 = call i32 @llvm.smin.i32(i32 %40, i32 %spec.select8.1.1)
%sub.3.1 = sub i32 %33, %7
- %48 = icmp slt i32 %sub.3.1, 0
- %neg.3.1 = sub nsw i32 0, %sub.3.1
- %49 = select i1 %48, i32 %neg.3.1, i32 %sub.3.1
- %cmp12.3.1 = icmp slt i32 %49, %spec.select8.2.1
+ %41 = call i32 @llvm.abs.i32(i32 %sub.3.1, i1 true)
+ %cmp12.3.1 = icmp slt i32 %41, %spec.select8.2.1
%narrow35 = or i1 %cmp12.3.1, %narrow34
%spec.select.3.1 = zext i1 %narrow35 to i32
- %spec.select8.3.1 = select i1 %cmp12.3.1, i32 %49, i32 %spec.select8.2.1
+ %spec.select8.3.1 = call i32 @llvm.smin.i32(i32 %41, i32 %spec.select8.2.1)
%sub.222 = sub i32 %33, %8
- %50 = icmp slt i32 %sub.222, 0
- %neg.223 = sub nsw i32 0, %sub.222
- %51 = select i1 %50, i32 %neg.223, i32 %sub.222
- %cmp12.224 = icmp slt i32 %51, %spec.select8.3.1
- %spec.select8.226 = select i1 %cmp12.224, i32 %51, i32 %spec.select8.3.1
+ %42 = call i32 @llvm.abs.i32(i32 %sub.222, i1 true)
+ %cmp12.224 = icmp slt i32 %42, %spec.select8.3.1
+ %spec.select8.226 = call i32 @llvm.smin.i32(i32 %42, i32 %spec.select8.3.1)
%sub.1.2 = sub i32 %33, %9
- %52 = icmp slt i32 %sub.1.2, 0
- %neg.1.2 = sub nsw i32 0, %sub.1.2
- %53 = select i1 %52, i32 %neg.1.2, i32 %sub.1.2
- %cmp12.1.2 = icmp slt i32 %53, %spec.select8.226
- %54 = or i1 %cmp12.1.2, %cmp12.224
- %spec.select8.1.2 = select i1 %cmp12.1.2, i32 %53, i32 %spec.select8.226
+ %43 = call i32 @llvm.abs.i32(i32 %sub.1.2, i1 true)
+ %cmp12.1.2 = icmp slt i32 %43, %spec.select8.226
+ %44 = or i1 %cmp12.1.2, %cmp12.224
+ %spec.select8.1.2 = call i32 @llvm.smin.i32(i32 %43, i32 %spec.select8.226)
%sub.2.2 = sub i32 %33, %10
- %55 = icmp slt i32 %sub.2.2, 0
- %neg.2.2 = sub nsw i32 0, %sub.2.2
- %56 = select i1 %55, i32 %neg.2.2, i32 %sub.2.2
- %cmp12.2.2 = icmp slt i32 %56, %spec.select8.1.2
- %57 = or i1 %cmp12.2.2, %54
- %spec.select8.2.2 = select i1 %cmp12.2.2, i32 %56, i32 %spec.select8.1.2
+ %45 = call i32 @llvm.abs.i32(i32 %sub.2.2, i1 true)
+ %cmp12.2.2 = icmp slt i32 %45, %spec.select8.1.2
+ %46 = or i1 %cmp12.2.2, %44
+ %spec.select8.2.2 = call i32 @llvm.smin.i32(i32 %45, i32 %spec.select8.1.2)
%sub.3.2 = sub i32 %33, %11
- %58 = icmp slt i32 %sub.3.2, 0
- %neg.3.2 = sub nsw i32 0, %sub.3.2
- %59 = select i1 %58, i32 %neg.3.2, i32 %sub.3.2
- %cmp12.3.2 = icmp slt i32 %59, %spec.select8.2.2
- %60 = or i1 %cmp12.3.2, %57
- %spec.select.3.2 = select i1 %60, i32 2, i32 %spec.select.3.1
- %spec.select8.3.2 = select i1 %cmp12.3.2, i32 %59, i32 %spec.select8.2.2
+ %47 = call i32 @llvm.abs.i32(i32 %sub.3.2, i1 true)
+ %cmp12.3.2 = icmp slt i32 %47, %spec.select8.2.2
+ %48 = or i1 %cmp12.3.2, %46
+ %spec.select.3.2 = select i1 %48, i32 2, i32 %spec.select.3.1
+ %spec.select8.3.2 = call i32 @llvm.smin.i32(i32 %47, i32 %spec.select8.2.2)
%sub.328 = sub i32 %33, %12
- %61 = icmp slt i32 %sub.328, 0
- %neg.329 = sub nsw i32 0, %sub.328
- %62 = select i1 %61, i32 %neg.329, i32 %sub.328
- %cmp12.330 = icmp slt i32 %62, %spec.select8.3.2
- %spec.select8.332 = select i1 %cmp12.330, i32 %62, i32 %spec.select8.3.2
+ %49 = call i32 @llvm.abs.i32(i32 %sub.328, i1 true)
+ %cmp12.330 = icmp slt i32 %49, %spec.select8.3.2
+ %spec.select8.332 = call i32 @llvm.smin.i32(i32 %49, i32 %spec.select8.3.2)
%sub.1.3 = sub i32 %33, %13
- %63 = icmp slt i32 %sub.1.3, 0
- %neg.1.3 = sub nsw i32 0, %sub.1.3
- %64 = select i1 %63, i32 %neg.1.3, i32 %sub.1.3
- %cmp12.1.3 = icmp slt i32 %64, %spec.select8.332
- %65 = or i1 %cmp12.1.3, %cmp12.330
- %spec.select8.1.3 = select i1 %cmp12.1.3, i32 %64, i32 %spec.select8.332
+ %50 = call i32 @llvm.abs.i32(i32 %sub.1.3, i1 true)
+ %cmp12.1.3 = icmp slt i32 %50, %spec.select8.332
+ %51 = or i1 %cmp12.1.3, %cmp12.330
+ %spec.select8.1.3 = call i32 @llvm.smin.i32(i32 %50, i32 %spec.select8.332)
%sub.2.3 = sub i32 %33, %14
- %66 = icmp slt i32 %sub.2.3, 0
- %neg.2.3 = sub nsw i32 0, %sub.2.3
- %67 = select i1 %66, i32 %neg.2.3, i32 %sub.2.3
- %cmp12.2.3 = icmp slt i32 %67, %spec.select8.1.3
- %68 = or i1 %cmp12.2.3, %65
- %spec.select8.2.3 = select i1 %cmp12.2.3, i32 %67, i32 %spec.select8.1.3
+ %52 = call i32 @llvm.abs.i32(i32 %sub.2.3, i1 true)
+ %cmp12.2.3 = icmp slt i32 %52, %spec.select8.1.3
+ %53 = or i1 %cmp12.2.3, %51
+ %spec.select8.2.3 = call i32 @llvm.smin.i32(i32 %52, i32 %spec.select8.1.3)
%sub.3.3 = sub i32 %33, %15
- %69 = icmp slt i32 %sub.3.3, 0
- %neg.3.3 = sub nsw i32 0, %sub.3.3
- %70 = select i1 %69, i32 %neg.3.3, i32 %sub.3.3
- %cmp12.3.3 = icmp slt i32 %70, %spec.select8.2.3
- %71 = or i1 %cmp12.3.3, %68
- %spec.select.3.3 = select i1 %71, i32 3, i32 %spec.select.3.2
- %spec.select8.3.3 = select i1 %cmp12.3.3, i32 %70, i32 %spec.select8.2.3
+ %54 = call i32 @llvm.abs.i32(i32 %sub.3.3, i1 true)
+ %cmp12.3.3 = icmp slt i32 %54, %spec.select8.2.3
+ %55 = or i1 %cmp12.3.3, %53
+ %spec.select.3.3 = select i1 %55, i32 3, i32 %spec.select.3.2
+ %spec.select8.3.3 = call i32 @llvm.smin.i32(i32 %54, i32 %spec.select8.2.3)
%sub.4 = sub i32 %33, %16
- %72 = icmp slt i32 %sub.4, 0
- %neg.4 = sub nsw i32 0, %sub.4
- %73 = select i1 %72, i32 %neg.4, i32 %sub.4
- %cmp12.4 = icmp slt i32 %73, %spec.select8.3.3
- %spec.select8.4 = select i1 %cmp12.4, i32 %73, i32 %spec.select8.3.3
+ %56 = call i32 @llvm.abs.i32(i32 %sub.4, i1 true)
+ %cmp12.4 = icmp slt i32 %56, %spec.select8.3.3
+ %spec.select8.4 = call i32 @llvm.smin.i32(i32 %56, i32 %spec.select8.3.3)
%sub.1.4 = sub i32 %33, %17
- %74 = icmp slt i32 %sub.1.4, 0
- %neg.1.4 = sub nsw i32 0, %sub.1.4
- %75 = select i1 %74, i32 %neg.1.4, i32 %sub.1.4
- %cmp12.1.4 = icmp slt i32 %75, %spec.select8.4
- %76 = or i1 %cmp12.1.4, %cmp12.4
- %spec.select8.1.4 = select i1 %cmp12.1.4, i32 %75, i32 %spec.select8.4
+ %57 = call i32 @llvm.abs.i32(i32 %sub.1.4, i1 true)
+ %cmp12.1.4 = icmp slt i32 %57, %spec.select8.4
+ %58 = or i1 %cmp12.1.4, %cmp12.4
+ %spec.select8.1.4 = call i32 @llvm.smin.i32(i32 %57, i32 %spec.select8.4)
%sub.2.4 = sub i32 %33, %18
- %77 = icmp slt i32 %sub.2.4, 0
- %neg.2.4 = sub nsw i32 0, %sub.2.4
- %78 = select i1 %77, i32 %neg.2.4, i32 %sub.2.4
- %cmp12.2.4 = icmp slt i32 %78, %spec.select8.1.4
- %79 = or i1 %cmp12.2.4, %76
- %spec.select8.2.4 = select i1 %cmp12.2.4, i32 %78, i32 %spec.select8.1.4
+ %59 = call i32 @llvm.abs.i32(i32 %sub.2.4, i1 true)
+ %cmp12.2.4 = icmp slt i32 %59, %spec.select8.1.4
+ %60 = or i1 %cmp12.2.4, %58
+ %spec.select8.2.4 = call i32 @llvm.smin.i32(i32 %59, i32 %spec.select8.1.4)
%sub.3.4 = sub i32 %33, %19
- %80 = icmp slt i32 %sub.3.4, 0
- %neg.3.4 = sub nsw i32 0, %sub.3.4
- %81 = select i1 %80, i32 %neg.3.4, i32 %sub.3.4
- %cmp12.3.4 = icmp slt i32 %81, %spec.select8.2.4
- %82 = or i1 %cmp12.3.4, %79
- %spec.select.3.4 = select i1 %82, i32 4, i32 %spec.select.3.3
- %spec.select8.3.4 = select i1 %cmp12.3.4, i32 %81, i32 %spec.select8.2.4
+ %61 = call i32 @llvm.abs.i32(i32 %sub.3.4, i1 true)
+ %cmp12.3.4 = icmp slt i32 %61, %spec.select8.2.4
+ %62 = or i1 %cmp12.3.4, %60
+ %spec.select.3.4 = select i1 %62, i32 4, i32 %spec.select.3.3
+ %spec.select8.3.4 = call i32 @llvm.smin.i32(i32 %61, i32 %spec.select8.2.4)
%sub.5 = sub i32 %33, %20
- %83 = icmp slt i32 %sub.5, 0
- %neg.5 = sub nsw i32 0, %sub.5
- %84 = select i1 %83, i32 %neg.5, i32 %sub.5
- %cmp12.5 = icmp slt i32 %84, %spec.select8.3.4
- %spec.select8.5 = select i1 %cmp12.5, i32 %84, i32 %spec.select8.3.4
+ %63 = call i32 @llvm.abs.i32(i32 %sub.5, i1 true)
+ %cmp12.5 = icmp slt i32 %63, %spec.select8.3.4
+ %spec.select8.5 = call i32 @llvm.smin.i32(i32 %63, i32 %spec.select8.3.4)
%sub.1.5 = sub i32 %33, %21
- %85 = icmp slt i32 %sub.1.5, 0
- %neg.1.5 = sub nsw i32 0, %sub.1.5
- %86 = select i1 %85, i32 %neg.1.5, i32 %sub.1.5
- %cmp12.1.5 = icmp slt i32 %86, %spec.select8.5
- %87 = or i1 %cmp12.1.5, %cmp12.5
- %spec.select8.1.5 = select i1 %cmp12.1.5, i32 %86, i32 %spec.select8.5
+ %64 = call i32 @llvm.abs.i32(i32 %sub.1.5, i1 true)
+ %cmp12.1.5 = icmp slt i32 %64, %spec.select8.5
+ %65 = or i1 %cmp12.1.5, %cmp12.5
+ %spec.select8.1.5 = call i32 @llvm.smin.i32(i32 %64, i32 %spec.select8.5)
%sub.2.5 = sub i32 %33, %22
- %88 = icmp slt i32 %sub.2.5, 0
- %neg.2.5 = sub nsw i32 0, %sub.2.5
- %89 = select i1 %88, i32 %neg.2.5, i32 %sub.2.5
- %cmp12.2.5 = icmp slt i32 %89, %spec.select8.1.5
- %90 = or i1 %cmp12.2.5, %87
- %spec.select8.2.5 = select i1 %cmp12.2.5, i32 %89, i32 %spec.select8.1.5
+ %66 = call i32 @llvm.abs.i32(i32 %sub.2.5, i1 true)
+ %cmp12.2.5 = icmp slt i32 %66, %spec.select8.1.5
+ %67 = or i1 %cmp12.2.5, %65
+ %spec.select8.2.5 = call i32 @llvm.smin.i32(i32 %66, i32 %spec.select8.1.5)
%sub.3.5 = sub i32 %33, %23
- %91 = icmp slt i32 %sub.3.5, 0
- %neg.3.5 = sub nsw i32 0, %sub.3.5
- %92 = select i1 %91, i32 %neg.3.5, i32 %sub.3.5
- %cmp12.3.5 = icmp slt i32 %92, %spec.select8.2.5
- %93 = or i1 %cmp12.3.5, %90
- %spec.select.3.5 = select i1 %93, i32 5, i32 %spec.select.3.4
- %spec.select8.3.5 = select i1 %cmp12.3.5, i32 %92, i32 %spec.select8.2.5
+ %68 = call i32 @llvm.abs.i32(i32 %sub.3.5, i1 true)
+ %cmp12.3.5 = icmp slt i32 %68, %spec.select8.2.5
+ %69 = or i1 %cmp12.3.5, %67
+ %spec.select.3.5 = select i1 %69, i32 5, i32 %spec.select.3.4
+ %spec.select8.3.5 = call i32 @llvm.smin.i32(i32 %68, i32 %spec.select8.2.5)
%sub.6 = sub i32 %33, %24
- %94 = icmp slt i32 %sub.6, 0
- %neg.6 = sub nsw i32 0, %sub.6
- %95 = select i1 %94, i32 %neg.6, i32 %sub.6
- %cmp12.6 = icmp slt i32 %95, %spec.select8.3.5
- %spec.select8.6 = select i1 %cmp12.6, i32 %95, i32 %spec.select8.3.5
+ %70 = call i32 @llvm.abs.i32(i32 %sub.6, i1 true)
+ %cmp12.6 = icmp slt i32 %70, %spec.select8.3.5
+ %spec.select8.6 = call i32 @llvm.smin.i32(i32 %70, i32 %spec.select8.3.5)
%sub.1.6 = sub i32 %33, %25
- %96 = icmp slt i32 %sub.1.6, 0
- %neg.1.6 = sub nsw i32 0, %sub.1.6
- %97 = select i1 %96, i32 %neg.1.6, i32 %sub.1.6
- %cmp12.1.6 = icmp slt i32 %97, %spec.select8.6
- %98 = or i1 %cmp12.1.6, %cmp12.6
- %spec.select8.1.6 = select i1 %cmp12.1.6, i32 %97, i32 %spec.select8.6
+ %71 = call i32 @llvm.abs.i32(i32 %sub.1.6, i1 true)
+ %cmp12.1.6 = icmp slt i32 %71, %spec.select8.6
+ %72 = or i1 %cmp12.1.6, %cmp12.6
+ %spec.select8.1.6 = call i32 @llvm.smin.i32(i32 %71, i32 %spec.select8.6)
%sub.2.6 = sub i32 %33, %26
- %99 = icmp slt i32 %sub.2.6, 0
- %neg.2.6 = sub nsw i32 0, %sub.2.6
- %100 = select i1 %99, i32 %neg.2.6, i32 %sub.2.6
- %cmp12.2.6 = icmp slt i32 %100, %spec.select8.1.6
- %101 = or i1 %cmp12.2.6, %98
- %spec.select8.2.6 = select i1 %cmp12.2.6, i32 %100, i32 %spec.select8.1.6
+ %73 = call i32 @llvm.abs.i32(i32 %sub.2.6, i1 true)
+ %cmp12.2.6 = icmp slt i32 %73, %spec.select8.1.6
+ %74 = or i1 %cmp12.2.6, %72
+ %spec.select8.2.6 = call i32 @llvm.smin.i32(i32 %73, i32 %spec.select8.1.6)
%sub.3.6 = sub i32 %33, %27
- %102 = icmp slt i32 %sub.3.6, 0
- %neg.3.6 = sub nsw i32 0, %sub.3.6
- %103 = select i1 %102, i32 %neg.3.6, i32 %sub.3.6
- %cmp12.3.6 = icmp slt i32 %103, %spec.select8.2.6
- %104 = or i1 %cmp12.3.6, %101
- %spec.select.3.6 = select i1 %104, i32 6, i32 %spec.select.3.5
- %spec.select8.3.6 = select i1 %cmp12.3.6, i32 %103, i32 %spec.select8.2.6
+ %75 = call i32 @llvm.abs.i32(i32 %sub.3.6, i1 true)
+ %cmp12.3.6 = icmp slt i32 %75, %spec.select8.2.6
+ %76 = or i1 %cmp12.3.6, %74
+ %spec.select.3.6 = select i1 %76, i32 6, i32 %spec.select.3.5
+ %spec.select8.3.6 = call i32 @llvm.smin.i32(i32 %75, i32 %spec.select8.2.6)
%sub.7 = sub i32 %33, %28
- %105 = icmp slt i32 %sub.7, 0
- %neg.7 = sub nsw i32 0, %sub.7
- %106 = select i1 %105, i32 %neg.7, i32 %sub.7
- %cmp12.7 = icmp slt i32 %106, %spec.select8.3.6
- %spec.select8.7 = select i1 %cmp12.7, i32 %106, i32 %spec.select8.3.6
+ %77 = call i32 @llvm.abs.i32(i32 %sub.7, i1 true)
+ %cmp12.7 = icmp slt i32 %77, %spec.select8.3.6
+ %spec.select8.7 = call i32 @llvm.smin.i32(i32 %77, i32 %spec.select8.3.6)
%sub.1.7 = sub i32 %33, %29
- %107 = icmp slt i32 %sub.1.7, 0
- %neg.1.7 = sub nsw i32 0, %sub.1.7
- %108 = select i1 %107, i32 %neg.1.7, i32 %sub.1.7
- %cmp12.1.7 = icmp slt i32 %108, %spec.select8.7
- %109 = or i1 %cmp12.1.7, %cmp12.7
- %spec.select8.1.7 = select i1 %cmp12.1.7, i32 %108, i32 %spec.select8.7
+ %78 = call i32 @llvm.abs.i32(i32 %sub.1.7, i1 true)
+ %cmp12.1.7 = icmp slt i32 %78, %spec.select8.7
+ %79 = or i1 %cmp12.1.7, %cmp12.7
+ %spec.select8.1.7 = call i32 @llvm.smin.i32(i32 %78, i32 %spec.select8.7)
%sub.2.7 = sub i32 %33, %30
- %110 = icmp slt i32 %sub.2.7, 0
- %neg.2.7 = sub nsw i32 0, %sub.2.7
- %111 = select i1 %110, i32 %neg.2.7, i32 %sub.2.7
- %cmp12.2.7 = icmp slt i32 %111, %spec.select8.1.7
- %112 = or i1 %cmp12.2.7, %109
- %spec.select8.2.7 = select i1 %cmp12.2.7, i32 %111, i32 %spec.select8.1.7
+ %80 = call i32 @llvm.abs.i32(i32 %sub.2.7, i1 true)
+ %cmp12.2.7 = icmp slt i32 %80, %spec.select8.1.7
+ %81 = or i1 %cmp12.2.7, %79
+ %spec.select8.2.7 = call i32 @llvm.smin.i32(i32 %80, i32 %spec.select8.1.7)
%sub.3.7 = sub i32 %33, %31
- %113 = icmp slt i32 %sub.3.7, 0
- %neg.3.7 = sub nsw i32 0, %sub.3.7
- %114 = select i1 %113, i32 %neg.3.7, i32 %sub.3.7
- %cmp12.3.7 = icmp slt i32 %114, %spec.select8.2.7
- %115 = or i1 %cmp12.3.7, %112
- %spec.select.3.7 = select i1 %115, i32 7, i32 %spec.select.3.6
- %spec.select8.3.7 = select i1 %cmp12.3.7, i32 %114, i32 %spec.select8.2.7
- %k = getelementptr inbounds [366 x i32], ptr @l, i64 0, i64 %indvars.iv
+ %82 = call i32 @llvm.abs.i32(i32 %sub.3.7, i1 true)
+ %cmp12.3.7 = icmp slt i32 %82, %spec.select8.2.7
+ %83 = or i1 %cmp12.3.7, %81
+ %spec.select.3.7 = select i1 %83, i32 7, i32 %spec.select.3.6
+ %spec.select8.3.7 = call i32 @llvm.smin.i32(i32 %82, i32 %spec.select8.2.7)
+ %k = getelementptr inbounds [4 x i8], ptr @l, i64 %indvars.iv
store i32 %spec.select.3.7, ptr %k, align 4
%indvars.iv.next = add i64 %indvars.iv, 1
br label %for.cond
}
-
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