[llvm] [RISCV][XCV] Add LLVM intrinsics and patterns for XCVsimd (PR #204880)

[via llvm-commits]

VittorioBurani wrote:

Thanks, and sorry for the slow turnaround. Following @lukel97's
suggestion I have split the SelectionDAG/codegen part out of this PR, so
this one is now scoped down to just the LLVM intrinsics for the XCVsimd
operations that have no generic-IR form (dot products, complex multiply,
shuffle, pack, extract/insert). The element-wise operations no longer get
intrinsics at all — they are selected from native packed-vector IR in the
split-out codegen PR #205836, where I have addressed both of your
points:

- The hand-written Expand list is gone. That block now iterates every
  opcode marking it `Expand` and then re-enables the supported ones, the
  same way the P and V extensions do, so it can't silently go wrong when
  new ISD nodes are added.

- On misaligned access: CORE-V (CV32E40P) does not support misaligned
  accesses. Since the packed value lives in a GPR, the access is just a
  word `lw`/`sw`, so rather than a dedicated custom lowering I route
  `v2i16`/`v4i8` through the scalar misalignment rule in
  `allowsMisalignedMemoryAccesses` — the same branch you take for the P
  extension via `hasStdExtP()`. An under-aligned access then splits into
  element loads/stores instead of a single trapping word access, and
  `LOAD`/`STORE` can stay `Legal`. It's covered by `load_align{4,2}` /
  `store_align2` in the new PR. If you'd prefer an explicit custom
  lowering to match the P extension, I'm happy to switch.


https://github.com/llvm/llvm-project/pull/204880