[llvm] [AArch64] Preserve SDNode flags when lowering fixed vectors to scalable operations (PR #204616)
Harry Ramsey via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 25 07:11:43 PDT 2026
https://github.com/Harry-Ramsey updated https://github.com/llvm/llvm-project/pull/204616
>From 3127cf5280a2f13239afb8c11b9ae1eedb35b6a6 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Wed, 17 Jun 2026 15:03:42 +0000
Subject: [PATCH 1/2] [AArch64] Preserve SDNode flags when lowering fixed
vectors to scalable operations
Preserve the original SDNode flags when LowerToScalableOp rebuilds
fixed-length vector operations using their scalable container type. This
allows combines to use flag information generated before the scalable
was created.
---
.../CodeGen/AArch64/sve2-fixed-length-sra.ll | 832 ++++++++++++++++++
1 file changed, 832 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/sve2-fixed-length-sra.ll
diff --git a/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra.ll b/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra.ll
new file mode 100644
index 0000000000000..602de94cb47ba
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra.ll
@@ -0,0 +1,832 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; USRA disjoint OR
+;
+
+define <8 x i8> @usra_disjoint_or8xi8(<8 x i8> %a, <8 x i8> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.8b, v1.8b, #4
+; CHECK-NEXT: ret
+ %shift = lshr <8 x i8> %b, splat(i8 4)
+ %res = or disjoint <8 x i8> %a, %shift
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @usra_disjoint_or16xi8(<16 x i8> %a, <16 x i8> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.16b, v1.16b, #4
+; CHECK-NEXT: ret
+ %shift = lshr <16 x i8> %b, splat(i8 4)
+ %res = or disjoint <16 x i8> %a, %shift
+ ret <16 x i8> %res
+}
+
+define void @usra_disjoint_or32xi8(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or32xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl32
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: usra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i8>, ptr %a
+ %vb = load <32 x i8>, ptr %b
+ %shift = lshr <32 x i8> %vb, splat(i8 4)
+ %res = or disjoint <32 x i8> %va, %shift
+ store <32 x i8> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or64xi8(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: usra_disjoint_or64xi8:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.b, vl32
+; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
+; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
+; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]
+; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]
+; VBITS_GE_256-NEXT: usra z0.b, z1.b, #4
+; VBITS_GE_256-NEXT: usra z2.b, z3.b, #4
+; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]
+; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: usra_disjoint_or64xi8:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.b, vl64
+; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]
+; VBITS_GE_512-NEXT: usra z0.b, z1.b, #4
+; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <64 x i8>, ptr %a
+ %vb = load <64 x i8>, ptr %b
+ %shift = lshr <64 x i8> %vb, splat(i8 4)
+ %res = or disjoint <64 x i8> %va, %shift
+ store <64 x i8> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or128xi8(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: usra_disjoint_or128xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl128
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: usra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <128 x i8>, ptr %a
+ %vb = load <128 x i8>, ptr %b
+ %shift = lshr <128 x i8> %vb, splat(i8 4)
+ %res = or disjoint <128 x i8> %va, %shift
+ store <128 x i8> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or256xi8(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: usra_disjoint_or256xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl256
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: usra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <256 x i8>, ptr %a
+ %vb = load <256 x i8>, ptr %b
+ %shift = lshr <256 x i8> %vb, splat(i8 4)
+ %res = or disjoint <256 x i8> %va, %shift
+ store <256 x i8> %res, ptr %a
+ ret void
+}
+
+define <4 x i16> @usra_disjoint_or4xi16(<4 x i16> %a, <4 x i16> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.4h, v1.4h, #4
+; CHECK-NEXT: ret
+ %shift = lshr <4 x i16> %b, splat(i16 4)
+ %res = or disjoint <4 x i16> %a, %shift
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @usra_disjoint_or8xi16(<8 x i16> %a, <8 x i16> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.8h, v1.8h, #4
+; CHECK-NEXT: ret
+ %shift = lshr <8 x i16> %b, splat(i16 4)
+ %res = or disjoint <8 x i16> %a, %shift
+ ret <8 x i16> %res
+}
+
+define void @usra_disjoint_or16xi16(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or16xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: usra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <16 x i16>, ptr %a
+ %vb = load <16 x i16>, ptr %b
+ %shift = lshr <16 x i16> %vb, splat(i16 4)
+ %res = or disjoint <16 x i16> %va, %shift
+ store <16 x i16> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or32xi16(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: usra_disjoint_or32xi16:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.h, vl16
+; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
+; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
+; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]
+; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]
+; VBITS_GE_256-NEXT: usra z0.h, z1.h, #4
+; VBITS_GE_256-NEXT: usra z2.h, z3.h, #4
+; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]
+; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: usra_disjoint_or32xi16:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.h, vl32
+; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]
+; VBITS_GE_512-NEXT: usra z0.h, z1.h, #4
+; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <32 x i16>, ptr %a
+ %vb = load <32 x i16>, ptr %b
+ %shift = lshr <32 x i16> %vb, splat(i16 4)
+ %res = or disjoint <32 x i16> %va, %shift
+ store <32 x i16> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or64xi16(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: usra_disjoint_or64xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl64
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: usra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <64 x i16>, ptr %a
+ %vb = load <64 x i16>, ptr %b
+ %shift = lshr <64 x i16> %vb, splat(i16 4)
+ %res = or disjoint <64 x i16> %va, %shift
+ store <64 x i16> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or128xi16(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: usra_disjoint_or128xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl128
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: usra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <128 x i16>, ptr %a
+ %vb = load <128 x i16>, ptr %b
+ %shift = lshr <128 x i16> %vb, splat(i16 4)
+ %res = or disjoint <128 x i16> %va, %shift
+ store <128 x i16> %res, ptr %a
+ ret void
+}
+
+define <2 x i32> @usra_disjoint_or2xi32(<2 x i32> %a, <2 x i32> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.2s, v1.2s, #4
+; CHECK-NEXT: ret
+ %shift = lshr <2 x i32> %b, splat(i32 4)
+ %res = or disjoint <2 x i32> %a, %shift
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @usra_disjoint_or4xi32(<4 x i32> %a, <4 x i32> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.4s, v1.4s, #4
+; CHECK-NEXT: ret
+ %shift = lshr <4 x i32> %b, splat(i32 4)
+ %res = or disjoint <4 x i32> %a, %shift
+ ret <4 x i32> %res
+}
+
+define void @usra_disjoint_or8xi32(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or8xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: usra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <8 x i32>, ptr %a
+ %vb = load <8 x i32>, ptr %b
+ %shift = lshr <8 x i32> %vb, splat(i32 4)
+ %res = or disjoint <8 x i32> %va, %shift
+ store <8 x i32> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or16xi32(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: usra_disjoint_or16xi32:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.s, vl8
+; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
+; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]
+; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]
+; VBITS_GE_256-NEXT: usra z0.s, z1.s, #4
+; VBITS_GE_256-NEXT: usra z2.s, z3.s, #4
+; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
+; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: usra_disjoint_or16xi32:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.s, vl16
+; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]
+; VBITS_GE_512-NEXT: usra z0.s, z1.s, #4
+; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <16 x i32>, ptr %a
+ %vb = load <16 x i32>, ptr %b
+ %shift = lshr <16 x i32> %vb, splat(i32 4)
+ %res = or disjoint <16 x i32> %va, %shift
+ store <16 x i32> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or32xi32(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: usra_disjoint_or32xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl32
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: usra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i32>, ptr %a
+ %vb = load <32 x i32>, ptr %b
+ %shift = lshr <32 x i32> %vb, splat(i32 4)
+ %res = or disjoint <32 x i32> %va, %shift
+ store <32 x i32> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or64xi32(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: usra_disjoint_or64xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl64
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: usra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <64 x i32>, ptr %a
+ %vb = load <64 x i32>, ptr %b
+ %shift = lshr <64 x i32> %vb, splat(i32 4)
+ %res = or disjoint <64 x i32> %va, %shift
+ store <64 x i32> %res, ptr %a
+ ret void
+}
+
+define <1 x i64> @usra_disjoint_or1xi64(<1 x i64> %a, <1 x i64> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or1xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra d0, d1, #4
+; CHECK-NEXT: ret
+ %shift = lshr <1 x i64> %b, splat(i64 4)
+ %res = or disjoint <1 x i64> %a, %shift
+ ret <1 x i64> %res
+}
+
+define <2 x i64> @usra_disjoint_or2xi64(<2 x i64> %a, <2 x i64> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: usra v0.2d, v1.2d, #4
+; CHECK-NEXT: ret
+ %shift = lshr <2 x i64> %b, splat(i64 4)
+ %res = or disjoint <2 x i64> %a, %shift
+ ret <2 x i64> %res
+}
+
+define void @usra_disjoint_or4xi64(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or4xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: usra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <4 x i64>, ptr %a
+ %vb = load <4 x i64>, ptr %b
+ %shift = lshr <4 x i64> %vb, splat(i64 4)
+ %res = or disjoint <4 x i64> %va, %shift
+ store <4 x i64> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or8xi64(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: usra_disjoint_or8xi64:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.d, vl4
+; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
+; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
+; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]
+; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]
+; VBITS_GE_256-NEXT: usra z0.d, z1.d, #4
+; VBITS_GE_256-NEXT: usra z2.d, z3.d, #4
+; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]
+; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: usra_disjoint_or8xi64:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.d, vl8
+; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]
+; VBITS_GE_512-NEXT: usra z0.d, z1.d, #4
+; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <8 x i64>, ptr %a
+ %vb = load <8 x i64>, ptr %b
+ %shift = lshr <8 x i64> %vb, splat(i64 4)
+ %res = or disjoint <8 x i64> %va, %shift
+ store <8 x i64> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or16xi64(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: usra_disjoint_or16xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl16
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: usra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <16 x i64>, ptr %a
+ %vb = load <16 x i64>, ptr %b
+ %shift = lshr <16 x i64> %vb, splat(i64 4)
+ %res = or disjoint <16 x i64> %va, %shift
+ store <16 x i64> %res, ptr %a
+ ret void
+}
+
+define void @usra_disjoint_or32xi64(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: usra_disjoint_or32xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl32
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: usra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i64>, ptr %a
+ %vb = load <32 x i64>, ptr %b
+ %shift = lshr <32 x i64> %vb, splat(i64 4)
+ %res = or disjoint <32 x i64> %va, %shift
+ store <32 x i64> %res, ptr %a
+ ret void
+}
+
+;
+; SSRA disjoint OR
+;
+
+define <8 x i8> @ssra_disjoint_or8xi8(<8 x i8> %a, <8 x i8> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.8b, v1.8b, #4
+; CHECK-NEXT: ret
+ %shift = ashr <8 x i8> %b, splat(i8 4)
+ %res = or disjoint <8 x i8> %a, %shift
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @ssra_disjoint_or16xi8(<16 x i8> %a, <16 x i8> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.16b, v1.16b, #4
+; CHECK-NEXT: ret
+ %shift = ashr <16 x i8> %b, splat(i8 4)
+ %res = or disjoint <16 x i8> %a, %shift
+ ret <16 x i8> %res
+}
+
+define void @ssra_disjoint_or32xi8(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or32xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl32
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i8>, ptr %a
+ %vb = load <32 x i8>, ptr %b
+ %shift = ashr <32 x i8> %vb, splat(i8 4)
+ %res = or disjoint <32 x i8> %va, %shift
+ store <32 x i8> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or64xi8(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: ssra_disjoint_or64xi8:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.b, vl32
+; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
+; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
+; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]
+; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]
+; VBITS_GE_256-NEXT: ssra z0.b, z1.b, #4
+; VBITS_GE_256-NEXT: ssra z2.b, z3.b, #4
+; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]
+; VBITS_GE_256-NEXT: st1b { z2.b }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: ssra_disjoint_or64xi8:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.b, vl64
+; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]
+; VBITS_GE_512-NEXT: ssra z0.b, z1.b, #4
+; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <64 x i8>, ptr %a
+ %vb = load <64 x i8>, ptr %b
+ %shift = ashr <64 x i8> %vb, splat(i8 4)
+ %res = or disjoint <64 x i8> %va, %shift
+ store <64 x i8> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or128xi8(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or128xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl128
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <128 x i8>, ptr %a
+ %vb = load <128 x i8>, ptr %b
+ %shift = ashr <128 x i8> %vb, splat(i8 4)
+ %res = or disjoint <128 x i8> %va, %shift
+ store <128 x i8> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or256xi8(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or256xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b, vl256
+; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.b, z1.b, #4
+; CHECK-NEXT: st1b { z0.b }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <256 x i8>, ptr %a
+ %vb = load <256 x i8>, ptr %b
+ %shift = ashr <256 x i8> %vb, splat(i8 4)
+ %res = or disjoint <256 x i8> %va, %shift
+ store <256 x i8> %res, ptr %a
+ ret void
+}
+
+define <4 x i16> @ssra_disjoint_or4xi16(<4 x i16> %a, <4 x i16> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.4h, v1.4h, #4
+; CHECK-NEXT: ret
+ %shift = ashr <4 x i16> %b, splat(i16 4)
+ %res = or disjoint <4 x i16> %a, %shift
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @ssra_disjoint_or8xi16(<8 x i16> %a, <8 x i16> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.8h, v1.8h, #4
+; CHECK-NEXT: ret
+ %shift = ashr <8 x i16> %b, splat(i16 4)
+ %res = or disjoint <8 x i16> %a, %shift
+ ret <8 x i16> %res
+}
+
+define void @ssra_disjoint_or16xi16(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or16xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <16 x i16>, ptr %a
+ %vb = load <16 x i16>, ptr %b
+ %shift = ashr <16 x i16> %vb, splat(i16 4)
+ %res = or disjoint <16 x i16> %va, %shift
+ store <16 x i16> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or32xi16(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: ssra_disjoint_or32xi16:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.h, vl16
+; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
+; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
+; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]
+; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]
+; VBITS_GE_256-NEXT: ssra z0.h, z1.h, #4
+; VBITS_GE_256-NEXT: ssra z2.h, z3.h, #4
+; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]
+; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: ssra_disjoint_or32xi16:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.h, vl32
+; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]
+; VBITS_GE_512-NEXT: ssra z0.h, z1.h, #4
+; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <32 x i16>, ptr %a
+ %vb = load <32 x i16>, ptr %b
+ %shift = ashr <32 x i16> %vb, splat(i16 4)
+ %res = or disjoint <32 x i16> %va, %shift
+ store <32 x i16> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or64xi16(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or64xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl64
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <64 x i16>, ptr %a
+ %vb = load <64 x i16>, ptr %b
+ %shift = ashr <64 x i16> %vb, splat(i16 4)
+ %res = or disjoint <64 x i16> %va, %shift
+ store <64 x i16> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or128xi16(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or128xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h, vl128
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.h, z1.h, #4
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <128 x i16>, ptr %a
+ %vb = load <128 x i16>, ptr %b
+ %shift = ashr <128 x i16> %vb, splat(i16 4)
+ %res = or disjoint <128 x i16> %va, %shift
+ store <128 x i16> %res, ptr %a
+ ret void
+}
+
+define <2 x i32> @ssra_disjoint_or2xi32(<2 x i32> %a, <2 x i32> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.2s, v1.2s, #4
+; CHECK-NEXT: ret
+ %shift = ashr <2 x i32> %b, splat(i32 4)
+ %res = or disjoint <2 x i32> %a, %shift
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @ssra_disjoint_or4xi32(<4 x i32> %a, <4 x i32> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.4s, v1.4s, #4
+; CHECK-NEXT: ret
+ %shift = ashr <4 x i32> %b, splat(i32 4)
+ %res = or disjoint <4 x i32> %a, %shift
+ ret <4 x i32> %res
+}
+
+define void @ssra_disjoint_or8xi32(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or8xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <8 x i32>, ptr %a
+ %vb = load <8 x i32>, ptr %b
+ %shift = ashr <8 x i32> %vb, splat(i32 4)
+ %res = or disjoint <8 x i32> %va, %shift
+ store <8 x i32> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or16xi32(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: ssra_disjoint_or16xi32:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.s, vl8
+; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
+; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]
+; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]
+; VBITS_GE_256-NEXT: ssra z0.s, z1.s, #4
+; VBITS_GE_256-NEXT: ssra z2.s, z3.s, #4
+; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
+; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: ssra_disjoint_or16xi32:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.s, vl16
+; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]
+; VBITS_GE_512-NEXT: ssra z0.s, z1.s, #4
+; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <16 x i32>, ptr %a
+ %vb = load <16 x i32>, ptr %b
+ %shift = ashr <16 x i32> %vb, splat(i32 4)
+ %res = or disjoint <16 x i32> %va, %shift
+ store <16 x i32> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or32xi32(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or32xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl32
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i32>, ptr %a
+ %vb = load <32 x i32>, ptr %b
+ %shift = ashr <32 x i32> %vb, splat(i32 4)
+ %res = or disjoint <32 x i32> %va, %shift
+ store <32 x i32> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or64xi32(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or64xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s, vl64
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.s, z1.s, #4
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <64 x i32>, ptr %a
+ %vb = load <64 x i32>, ptr %b
+ %shift = ashr <64 x i32> %vb, splat(i32 4)
+ %res = or disjoint <64 x i32> %va, %shift
+ store <64 x i32> %res, ptr %a
+ ret void
+}
+
+define <1 x i64> @ssra_disjoint_or1xi64(<1 x i64> %a, <1 x i64> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or1xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra d0, d1, #4
+; CHECK-NEXT: ret
+ %shift = ashr <1 x i64> %b, splat(i64 4)
+ %res = or disjoint <1 x i64> %a, %shift
+ ret <1 x i64> %res
+}
+
+define <2 x i64> @ssra_disjoint_or2xi64(<2 x i64> %a, <2 x i64> %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ssra v0.2d, v1.2d, #4
+; CHECK-NEXT: ret
+ %shift = ashr <2 x i64> %b, splat(i64 4)
+ %res = or disjoint <2 x i64> %a, %shift
+ ret <2 x i64> %res
+}
+
+define void @ssra_disjoint_or4xi64(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or4xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <4 x i64>, ptr %a
+ %vb = load <4 x i64>, ptr %b
+ %shift = ashr <4 x i64> %vb, splat(i64 4)
+ %res = or disjoint <4 x i64> %va, %shift
+ store <4 x i64> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or8xi64(ptr %a, ptr %b) #0 {
+; VBITS_GE_256-LABEL: ssra_disjoint_or8xi64:
+; VBITS_GE_256: // %bb.0:
+; VBITS_GE_256-NEXT: ptrue p0.d, vl4
+; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
+; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
+; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]
+; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]
+; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]
+; VBITS_GE_256-NEXT: ssra z0.d, z1.d, #4
+; VBITS_GE_256-NEXT: ssra z2.d, z3.d, #4
+; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]
+; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0]
+; VBITS_GE_256-NEXT: ret
+;
+; VBITS_GE_512-LABEL: ssra_disjoint_or8xi64:
+; VBITS_GE_512: // %bb.0:
+; VBITS_GE_512-NEXT: ptrue p0.d, vl8
+; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
+; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]
+; VBITS_GE_512-NEXT: ssra z0.d, z1.d, #4
+; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]
+; VBITS_GE_512-NEXT: ret
+ %va = load <8 x i64>, ptr %a
+ %vb = load <8 x i64>, ptr %b
+ %shift = ashr <8 x i64> %vb, splat(i64 4)
+ %res = or disjoint <8 x i64> %va, %shift
+ store <8 x i64> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or16xi64(ptr %a, ptr %b) vscale_range(8,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or16xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl16
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <16 x i64>, ptr %a
+ %vb = load <16 x i64>, ptr %b
+ %shift = ashr <16 x i64> %vb, splat(i64 4)
+ %res = or disjoint <16 x i64> %va, %shift
+ store <16 x i64> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or32xi64(ptr %a, ptr %b) vscale_range(16,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or32xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl32
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
+; CHECK-NEXT: ssra z0.d, z1.d, #4
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %va = load <32 x i64>, ptr %a
+ %vb = load <32 x i64>, ptr %b
+ %shift = ashr <32 x i64> %vb, splat(i64 4)
+ %res = or disjoint <32 x i64> %va, %shift
+ store <32 x i64> %res, ptr %a
+ ret void
+}
+
+attributes #0 = { "target-features"="+sve,+sve2" }
>From 5c01d586fcb8d00969d5a48e97caaef0db8f5e42 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Wed, 17 Jun 2026 15:18:17 +0000
Subject: [PATCH 2/2] fixup! [AArch64] Preserve SDNode flags when lowering
fixed vectors to scalable operations
---
.../Target/AArch64/AArch64ISelLowering.cpp | 3 +-
.../AArch64/sve2-fixed-length-sra-flag.ll | 28 +++++++++++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/sve2-fixed-length-sra-flag.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 411ccc3fb21d0..730112f95084f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -33080,7 +33080,8 @@ SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,
Ops.push_back(convertToScalableVector(DAG, ContainerVT, V));
}
- auto ScalableRes = DAG.getNode(Op.getOpcode(), SDLoc(Op), ContainerVT, Ops);
+ auto ScalableRes =
+ DAG.getNode(Op.getOpcode(), SDLoc(Op), ContainerVT, Ops, Op->getFlags());
return convertFromScalableVector(DAG, VT, ScalableRes);
}
diff --git a/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra-flag.ll b/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra-flag.ll
new file mode 100644
index 0000000000000..5bf9b5490e1cd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve2-fixed-length-sra-flag.ll
@@ -0,0 +1,28 @@
+; REQUIRES: asserts
+; RUN: llc -debug-only=isel < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define void @usra_disjoint_or32xi8(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: usra_disjoint_or32xi8:
+; CHECK: nxv16i8 = USRA_ZZI_B disjoint {{.*}}, {{.*}}, TargetConstant:i32<4>
+ %va = load <32 x i8>, ptr %a
+ %vb = load <32 x i8>, ptr %b
+ %shift = lshr <32 x i8> %vb, splat(i8 4)
+ %res = or disjoint <32 x i8> %va, %shift
+ store <32 x i8> %res, ptr %a
+ ret void
+}
+
+define void @ssra_disjoint_or32xi8(ptr %a, ptr %b) vscale_range(2,0) #0 {
+; CHECK-LABEL: ssra_disjoint_or32xi8:
+ ; CHECK: nxv16i8 = SSRA_ZZI_B disjoint {{.*}}, {{.*}}, TargetConstant:i32<4>
+ %va = load <32 x i8>, ptr %a
+ %vb = load <32 x i8>, ptr %b
+ %shift = ashr <32 x i8> %vb, splat(i8 4)
+ %res = or disjoint <32 x i8> %va, %shift
+ store <32 x i8> %res, ptr %a
+ ret void
+}
+
+attributes #0 = { "target-features"="+sve,+sve2" }
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