[llvm] 647c298 - [AArch64] Correct A510 scheduling information for LDn instructions (#205518)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 25 06:52:55 PDT 2026
Author: John Brawn
Date: 2026-06-25T14:52:48+01:00
New Revision: 647c29886973c7111a32702e3c7a5ccc33a9feeb
URL: https://github.com/llvm/llvm-project/commit/647c29886973c7111a32702e3c7a5ccc33a9feeb
DIFF: https://github.com/llvm/llvm-project/commit/647c29886973c7111a32702e3c7a5ccc33a9feeb.diff
LOG: [AArch64] Correct A510 scheduling information for LDn instructions (#205518)
The latency and throughput for these instructions don't match what's in
the A510 Software Optimization Guide, so adjust them so that they do
match. Also rearrange the definitions to match how they're structured in
the optimization guide and rename things in a similar manner to how the
C1 CPUs do things, as it's much clearer.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SchedA510.td
llvm/test/CodeGen/AArch64/zext-to-tbl.ll
llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index 8a13067ca197b..56ac7141be30f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -124,18 +124,16 @@ def : WriteRes<WriteLD, [CortexA510UnitLd]> { let Latency = 2; }
def : WriteRes<WriteLDIdx, [CortexA510UnitLd]> { let Latency = 2; }
def : WriteRes<WriteLDHi, [CortexA510UnitLd]> { let Latency = 2; }
+def CortexA510Write_3c_1Ld : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
+def CortexA510Write_3c_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 3; }
+def CortexA510Write_4c_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 4; }
+def CortexA510Write_4c_2r_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 4; let ReleaseAtCycles = [2,2]; }
+def CortexA510Write_5c_3r_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 5; let ReleaseAtCycles = [3,3]; }
+def CortexA510Write_5c_4r_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 5; let ReleaseAtCycles = [4,4]; }
+def CortexA510Write_6c_4r_2Ld : SchedWriteRes<[CortexA510UnitLd, CortexA510UnitLd]> { let Latency = 6; let ReleaseAtCycles = [4,4]; }
+
def CortexA510WriteVLD1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteVLD1SI : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; let SingleIssue = 1; }
-def CortexA510WriteVLD2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 4;
- let ReleaseAtCycles = [2]; }
-def CortexA510WriteVLD3 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
-def CortexA510WriteVLD4 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [4]; }
-def CortexA510WriteVLD6 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
- let ReleaseAtCycles = [3]; }
-def CortexA510WriteVLD8 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
- let ReleaseAtCycles = [4]; }
def CortexA510WriteLDP1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteLDP2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
@@ -284,60 +282,64 @@ def : InstRW<[WriteI], (instrs COPY)>;
// Vector Loads - 128-bit per cycle
//---
// 1-element structures
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; // single element
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // replicate
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1Twov(8b|4h|2s|1d)$")>; // multiple structures
-def : InstRW<[CortexA510WriteVLD1], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
-
-def : InstRW<[WriteAdr, CortexA510WriteVLD1], (instregex "LD1i(8|16|32|64)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[CortexA510Write_3c_1Ld], (instregex "LD1Onev(8b|4h|2s|1d)$")>; // 1 element, multiple, 1 reg, D-form
+def : InstRW<[CortexA510Write_3c_1Ld], (instregex "LD1Onev(16b|8h|4s|2d)$")>; // 1 element, multiple, 1 reg, Q-form
+def : InstRW<[CortexA510Write_3c_2Ld], (instregex "LD1Twov(8b|4h|2s|1d)$")>; // 1 element, multiple, 2 reg, D-form
+def : InstRW<[CortexA510Write_3c_2Ld], (instregex "LD1Twov(16b|8h|4s|2d)$")>; // 1 element, multiple, 2 reg, Q-form
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD1Threev(8b|4h|2s|1d)$")>; // 1 element, multiple, 3 reg, D-form
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD1Threev(16b|8h|4s|2d)$")>; // 1 element, multiple, 3 reg, Q-form
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; // 1 element, multiple, 4 reg, D-form
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; // 1 element, multiple, 4 reg, Q-form
+def : InstRW<[CortexA510Write_3c_1Ld], (instregex "LD1i(8|16|32|64)$")>; // 1 element, one lane
+def : InstRW<[CortexA510Write_3c_1Ld], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // 1 element, all lanes
+
+def : InstRW<[WriteAdr, CortexA510Write_3c_1Ld], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_1Ld], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_2Ld], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_2Ld], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_1Ld], (instregex "LD1i(8|16|32|64)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_1Ld], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
// 2-element structures
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD2i(8|16|32|64)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
-def : InstRW<[CortexA510WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
-
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
+def : InstRW<[CortexA510Write_4c_2Ld], (instregex "LD2Twov(8b|4h|2s)$")>; // 2 element, multiple, D-form
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD2Twov(16b|8h|4s)$")>; // 2 element, multiple, Q-form, B/H/S
+def : InstRW<[CortexA510Write_4c_2Ld], (instregex "LD2Twov(2d)$")>; // 2 element, multiple, Q-form, D
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD2i(8|16|32|64)$")>; // 2 element, one lane
+def : InstRW<[CortexA510Write_3c_2Ld], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // 2 element, all lanes
+
+def : InstRW<[WriteAdr, CortexA510Write_4c_2Ld], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2Ld], (instregex "LD2Twov(2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD2i(8|16|32|64)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_3c_2Ld], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
// 3-element structures
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
-def : InstRW<[CortexA510WriteVLD3], (instregex "LD3Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[CortexA510WriteVLD6], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[CortexA510Write_5c_3r_2Ld], (instregex "LD3Threev(8b|4h|2s|1d)$")>; // 3 element, multiple, D-form
+def : InstRW<[CortexA510Write_5c_3r_2Ld], (instregex "LD3Threev(16b|8h|4s|2d)$")>; // 3 element, multiple, Q-form
+def : InstRW<[CortexA510Write_5c_3r_2Ld], (instregex "LD3i(8|16|32|64)$")>; // 3 element, one lane
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // 3 element, all lanes
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD3i(8|16|32|64)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD3], (instregex "LD3Threev(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD6], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_5c_3r_2Ld], (instregex "LD3Threev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_5c_3r_2Ld], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_5c_3r_2Ld], (instregex "LD3i(8|16|32|64)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
// 4-element structures
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; // load single 4-el structure to one lane of 4 regs.
-def : InstRW<[CortexA510WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // load single 4-el structure, replicate to all lanes of 4 regs.
-def : InstRW<[CortexA510WriteVLD4], (instregex "LD4Fourv(8b|4h|2s|1d)$")>; // load multiple 4-el structures to 4 regs.
-def : InstRW<[CortexA510WriteVLD8], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
-
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD4i(8|16|32|64)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD4], (instregex "LD4Fourv(8b|4h|2s|1d)_POST$")>;
-def : InstRW<[WriteAdr, CortexA510WriteVLD8], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[CortexA510Write_5c_3r_2Ld], (instregex "LD4Fourv(8b|4h|2s|1d)$")>; // 4 element, multiple, D-form
+def : InstRW<[CortexA510Write_5c_3r_2Ld], (instregex "LD4Fourv(16b|8h|4s)$")>; // 4 element, multiple, D-form, B/H/S
+def : InstRW<[CortexA510Write_5c_4r_2Ld], (instregex "LD4Fourv(2d)$")>; // 4 element, multiple, D-form, D
+def : InstRW<[CortexA510Write_6c_4r_2Ld], (instregex "LD4i(8|16|32|64)$")>; // 4 element, one lane
+def : InstRW<[CortexA510Write_4c_2r_2Ld], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // 4 element, all lanes
+
+def : InstRW<[WriteAdr, CortexA510Write_5c_3r_2Ld], (instregex "LD4Fourv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_5c_3r_2Ld], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_5c_4r_2Ld], (instregex "LD4Fourv(2d)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_6c_4r_2Ld], (instregex "LD4i(8|16|32|64)_POST$")>;
+def : InstRW<[WriteAdr, CortexA510Write_4c_2r_2Ld], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
//---
// Vector Stores
diff --git a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
index 26c814ba4f621..3871d970ff578 100644
--- a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
@@ -2833,11 +2833,11 @@ define i32 @test_widening_instr_mull(ptr %p1, ptr %p2, i32 %h) {
; CHECK-BE-NEXT: .LBB24_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v0.16b }, [x1], #16
-; CHECK-BE-NEXT: add x8, x0, #16
; CHECK-BE-NEXT: ld1 { v1.8h }, [x0]
-; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
+; CHECK-BE-NEXT: add x8, x0, #16
; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: add x10, x0, #32
+; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: ushll v2.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v0.8h, v0.16b, #0
@@ -3098,11 +3098,11 @@ define i32 @test_widening_instr_mull_2(ptr %p1, ptr %p2, i32 %h) {
; CHECK-BE-NEXT: ld1 { v17.4s }, [x8]
; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
; CHECK-BE-NEXT: ld1 { v19.4s }, [x10]
-; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v1.16b
; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v3.16b
; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v2.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
+; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: rev32 v5.16b, v5.16b
; CHECK-BE-NEXT: rev32 v6.16b, v6.16b
; CHECK-BE-NEXT: rev32 v7.16b, v7.16b
@@ -3170,18 +3170,18 @@ define i32 @mul_zext_16i8_sext_16i8(ptr %p1, ptr %p2, i32 %h) {
; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: .LBB27_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-BE-NEXT: ld1 { v0.16b }, [x1], #16
+; CHECK-BE-NEXT: ld1 { v0.16b }, [x0]
+; CHECK-BE-NEXT: ld1 { v1.16b }, [x1], #16
; CHECK-BE-NEXT: add x8, x0, #48
-; CHECK-BE-NEXT: ld1 { v1.16b }, [x0]
; CHECK-BE-NEXT: subs w2, w2, #1
-; CHECK-BE-NEXT: sshll2 v2.8h, v1.16b, #0
-; CHECK-BE-NEXT: ushll2 v3.8h, v0.16b, #0
-; CHECK-BE-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-BE-NEXT: sshll2 v2.8h, v0.16b, #0
+; CHECK-BE-NEXT: ushll2 v3.8h, v1.16b, #0
+; CHECK-BE-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-BE-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-BE-NEXT: smull2 v4.4s, v2.8h, v3.8h
; CHECK-BE-NEXT: smull v2.4s, v2.4h, v3.4h
-; CHECK-BE-NEXT: smull v3.4s, v1.4h, v0.4h
-; CHECK-BE-NEXT: smull2 v0.4s, v1.8h, v0.8h
+; CHECK-BE-NEXT: smull v3.4s, v0.4h, v1.4h
+; CHECK-BE-NEXT: smull2 v0.4s, v0.8h, v1.8h
; CHECK-BE-NEXT: st1 { v4.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #32
; CHECK-BE-NEXT: st1 { v3.4s }, [x0]
@@ -3244,11 +3244,11 @@ define i32 @mul_zext_16i8_sext_16i16(ptr %p1, ptr %p2, i32 %h) {
; CHECK-BE-NEXT: .LBB28_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v0.16b }, [x1], #16
-; CHECK-BE-NEXT: add x8, x0, #16
; CHECK-BE-NEXT: ld1 { v1.8h }, [x0]
-; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
+; CHECK-BE-NEXT: add x8, x0, #16
; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: add x10, x0, #32
+; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: ushll v2.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v0.8h, v0.16b, #0
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
index 9417ee208a1fe..b5aa217ed3144 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
@@ -1385,44 +1385,44 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 8 5.00 fsqrt v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fsub v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 3 0.50 * ld1 { v0.16b }, [x0]
-# CHECK-NEXT: 2 4 1.00 * ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
-# CHECK-NEXT: 1 4 1.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
-# CHECK-NEXT: 2 4 1.00 * ld1 { v0.4s, v1.4s }, [sp], #32
-# CHECK-NEXT: 1 4 1.00 * ld1 { v0.4s, v1.4s, v2.4s }, [sp]
-# CHECK-NEXT: 2 4 1.00 * ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
-# CHECK-NEXT: 2 4 1.00 * ld1 { v0.8h }, [x15], x2
-# CHECK-NEXT: 1 3 0.50 * ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 2 4 2.00 * ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: 1 4 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: 2 3 1.00 * ld1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 1 4 2.00 * ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: 2 4 2.00 * ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: 2 3 0.50 * ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 1 3 1.00 * ld1 { v0.8h, v1.8h }, [x15]
# CHECK-NEXT: 1 3 0.50 * ld1 { v0.b }[9], [x0]
# CHECK-NEXT: 2 3 0.50 * ld1 { v0.b }[9], [x0], #1
# CHECK-NEXT: 1 3 0.50 * ld1r { v0.16b }, [x0]
# CHECK-NEXT: 2 3 0.50 * ld1r { v0.16b }, [x0], #1
# CHECK-NEXT: 1 3 0.50 * ld1r { v0.8h }, [x15]
# CHECK-NEXT: 2 3 0.50 * ld1r { v0.8h }, [x15], #2
-# CHECK-NEXT: 2 6 2.00 * ld2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: 2 4 2.00 * ld2 { v0.16b, v1.16b }, [x0], x1
# CHECK-NEXT: 1 4 1.00 * ld2 { v0.8b, v1.8b }, [x0]
-# CHECK-NEXT: 1 4 1.00 * ld2 { v0.h, v1.h }[7], [x15]
-# CHECK-NEXT: 2 4 1.00 * ld2 { v0.h, v1.h }[7], [x15], #4
-# CHECK-NEXT: 1 4 1.00 * ld2r { v0.2d, v1.2d }, [x0]
-# CHECK-NEXT: 2 4 1.00 * ld2r { v0.2d, v1.2d }, [x0], #16
-# CHECK-NEXT: 1 4 1.00 * ld2r { v0.4s, v1.4s }, [sp]
-# CHECK-NEXT: 2 4 1.00 * ld2r { v0.4s, v1.4s }, [sp], #8
-# CHECK-NEXT: 1 5 1.50 * ld3 { v0.4h, v1.4h, v2.4h }, [x15]
-# CHECK-NEXT: 2 5 1.50 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
-# CHECK-NEXT: 1 4 1.00 * ld3 { v0.s, v1.s, v2.s }[3], [sp]
-# CHECK-NEXT: 2 4 1.00 * ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
-# CHECK-NEXT: 1 4 1.00 * ld3r { v0.4h, v1.4h, v2.4h }, [x15]
-# CHECK-NEXT: 2 4 1.00 * ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
-# CHECK-NEXT: 1 4 1.00 * ld3r { v0.8b, v1.8b, v2.8b }, [x0]
-# CHECK-NEXT: 2 4 1.00 * ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
-# CHECK-NEXT: 1 6 2.00 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
-# CHECK-NEXT: 2 6 2.00 * ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
-# CHECK-NEXT: 1 4 1.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
-# CHECK-NEXT: 2 4 1.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
-# CHECK-NEXT: 2 4 1.00 * ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
-# CHECK-NEXT: 1 4 1.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
-# CHECK-NEXT: 2 4 1.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
-# CHECK-NEXT: 1 4 1.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
-# CHECK-NEXT: 2 4 1.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: 1 4 2.00 * ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: 2 4 2.00 * ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: 1 3 1.00 * ld2r { v0.2d, v1.2d }, [x0]
+# CHECK-NEXT: 2 3 1.00 * ld2r { v0.2d, v1.2d }, [x0], #16
+# CHECK-NEXT: 1 3 1.00 * ld2r { v0.4s, v1.4s }, [sp]
+# CHECK-NEXT: 2 3 1.00 * ld2r { v0.4s, v1.4s }, [sp], #8
+# CHECK-NEXT: 1 5 3.00 * ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 2 5 3.00 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: 1 5 3.00 * ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: 2 5 3.00 * ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: 1 4 2.00 * ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 2 4 2.00 * ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: 1 4 2.00 * ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: 2 4 2.00 * ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: 1 5 3.00 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 2 5 3.00 * ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: 1 6 4.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: 2 6 4.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: 2 6 4.00 * ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: 1 4 2.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: 2 4 2.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: 1 4 2.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 2 4 2.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
# CHECK-NEXT: 1 4 0.50 mla v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 0.50 mls v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 0.50 mov b0, v0.b[15]
@@ -2148,7 +2148,7 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
-# CHECK-NEXT: - - - - - 39.00 91.00 - - 501.00 501.00 3.00 3.00 197.00
+# CHECK-NEXT: - - - - - 71.00 123.00 - - 501.00 501.00 3.00 3.00 197.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
@@ -2467,13 +2467,13 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: - - - - - - - - - - - - - 5.00 fsqrt v0.8h, v0.8h
# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - fsub v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1 { v0.16b }, [x0]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.4s, v1.4s }, [sp], #32
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [sp]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.8h }, [x15], x2
-# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld1 { v0.8h, v1.8h }, [x15]
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1 { v0.b }[9], [x0]
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1 { v0.b }[9], [x0], #1
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1r { v0.16b }, [x0]
@@ -2482,29 +2482,29 @@ zip2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - ld1r { v0.8h }, [x15], #2
# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld2 { v0.16b, v1.16b }, [x0], x1
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2 { v0.8b, v1.8b }, [x0]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2 { v0.h, v1.h }[7], [x15]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld2 { v0.h, v1.h }[7], [x15], #4
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2r { v0.2d, v1.2d }, [x0]
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2r { v0.2d, v1.2d }, [x0], #16
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2r { v0.4s, v1.4s }, [sp]
# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld2r { v0.4s, v1.4s }, [sp], #8
-# CHECK-NEXT: - - - - - 1.50 1.50 - - - - - - - ld3 { v0.4h, v1.4h, v2.4h }, [x15]
-# CHECK-NEXT: - - - - - 1.50 1.50 - - - - - - - ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3 { v0.s, v1.s, v2.s }[3], [sp]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3r { v0.4h, v1.4h, v2.4h }, [x15]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3r { v0.8b, v1.8b, v2.8b }, [x0]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
-# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
-# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
-# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - 3.00 3.00 - - - - - - - ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: - - - - - 4.00 4.00 - - - - - - - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: - - - - - 4.00 4.00 - - - - - - - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: - - - - - 4.00 4.00 - - - - - - - ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - - - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - mla v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - mls v0.4h, v0.4h, v0.4h
# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - mov b0, v0.b[15]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
index fa87b28bfc02a..762240768cf9f 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
@@ -1162,28 +1162,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 1701
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.88
-# CHECK-NEXT: IPC: 0.59
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 01234567
+# CHECK-NEXT: 012345
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeE . . . . ld1 { v1.1d }, [x27], #8
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.2d }, [x27], #16
-# CHECK-NEXT: [0,3] . .DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeE . . ld1 { v1.2s }, [x27], #8
-# CHECK-NEXT: [0,5] . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . DeeE . . ld1 { v1.4h }, [x27], #8
-# CHECK-NEXT: [0,7] . . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . DeeeE ld1 { v1.4s }, [x27], #16
-# CHECK-NEXT: [0,9] . . . .DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.1d }, [x27], #8
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.2d }, [x27], #16
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.2s }, [x27], #8
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.4h }, [x27], #8
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.4s }, [x27], #16
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1208,28 +1208,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 1801
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.83
-# CHECK-NEXT: IPC: 0.56
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345678
+# CHECK-NEXT: 012345
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeE . . . . ld1 { v1.8b }, [x27], #8
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.8h }, [x27], #16
-# CHECK-NEXT: [0,3] . .DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld1 { v1.16b }, [x27], #16
-# CHECK-NEXT: [0,5] . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . .DeeE. . ld1 { v1.1d }, [x27], x28
-# CHECK-NEXT: [0,7] . . . DE. . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . DeeeE ld1 { v1.2d }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.8b }, [x27], #8
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.8h }, [x27], #16
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.16b }, [x27], #16
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.1d }, [x27], x28
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.2d }, [x27], x28
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1254,28 +1254,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 1701
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.88
-# CHECK-NEXT: IPC: 0.59
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 01234567
+# CHECK-NEXT: 012345
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeE . . . . ld1 { v1.2s }, [x27], x28
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeE . . . ld1 { v1.4h }, [x27], x28
-# CHECK-NEXT: [0,3] . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . .DeeeE . . ld1 { v1.4s }, [x27], x28
-# CHECK-NEXT: [0,5] . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . DeeE . . ld1 { v1.8b }, [x27], x28
-# CHECK-NEXT: [0,7] . . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . DeeeE ld1 { v1.8h }, [x27], x28
-# CHECK-NEXT: [0,9] . . . .DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.2s }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.4h }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.4s }, [x27], x28
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.8b }, [x27], x28
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.8h }, [x27], x28
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1300,28 +1300,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld1 { v1.16b }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.1d, v2.1d }, [x27], #16
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld1 { v1.2d, v2.2d }, [x27], #32
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld1 { v1.2s, v2.2s }, [x27], #16
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld1 { v1.4h, v2.4h }, [x27], #16
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.16b }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1346,28 +1346,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld1 { v1.4s, v2.4s }, [x27], #32
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.8b, v2.8b }, [x27], #16
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld1 { v1.8h, v2.8h }, [x27], #32
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld1 { v1.16b, v2.16b }, [x27], #32
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld1 { v1.1d, v2.1d }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1392,28 +1392,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld1 { v1.2d, v2.2d }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.2s, v2.2s }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld1 { v1.4h, v2.4h }, [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld1 { v1.4s, v2.4s }, [x27], x28
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld1 { v1.8b, v2.8b }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld1 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld1 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld1 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld1 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld1 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1438,28 +1438,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1801
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.56
+# CHECK-NEXT: Block RThroughput: 8.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld1 { v1.8h, v2.8h }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld1 { v1.16b, v2.16b }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld1 { v1.1d, v2.1d, v3.1d }, [x27], #24
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld1 { v1.2d, v2.2d, v3.2d }, [x27], #48
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld1 { v1.2s, v2.2s, v3.2s }, [x27], #24
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . . ld1 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . . ld1 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeeE . . ld1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: [0,5] . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeeE. . ld1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,7] . . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeeE ld1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -1490,7 +1490,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1536,7 +1536,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1582,7 +1582,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1628,7 +1628,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1674,7 +1674,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1720,7 +1720,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.79
# CHECK-NEXT: IPC: 0.53
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 8.5
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -1990,28 +1990,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1801
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.56
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeE . . . . ld1r { v1.8h }, [x27], x28
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeE . . . ld1r { v1.16b }, [x27], x28
-# CHECK-NEXT: [0,3] . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . .DeeeeeE . . ld2 { v1.2d, v2.2d }, [x27], #32
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld2 { v1.2s, v2.2s }, [x27], #16
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld2 { v1.4h, v2.4h }, [x27], #16
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . . ld1r { v1.8h }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . . ld1r { v1.16b }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeeE . . ld2 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,5] . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeeE. . ld2 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,7] . . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeeE ld2 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2036,28 +2036,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2801
+# CHECK-NEXT: Total Cycles: 2001
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.54
-# CHECK-NEXT: IPC: 0.36
-# CHECK-NEXT: Block RThroughput: 9.0
+# CHECK-NEXT: uOps Per Cycle: 0.75
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 8.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 012345678
-
-# CHECK: [0,0] DeeeeeE . . . . . ld2 { v1.4s, v2.4s }, [x27], #32
-# CHECK-NEXT: [0,1] . DE . . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . .DeeeE . . . . ld2 { v1.8b, v2.8b }, [x27], #16
-# CHECK-NEXT: [0,3] . . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeeeE . . . ld2 { v1.8h, v2.8h }, [x27], #32
-# CHECK-NEXT: [0,5] . . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . .DeeeeeE . . ld2 { v1.16b, v2.16b }, [x27], #32
-# CHECK-NEXT: [0,7] . . . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld2 { v1.2d, v2.2d }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeE. . . . ld2 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeE . . . ld2 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeE . . ld2 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeE . ld2 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . .DeeeE ld2 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2082,28 +2082,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2401
+# CHECK-NEXT: Total Cycles: 2001
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.62
-# CHECK-NEXT: IPC: 0.42
+# CHECK-NEXT: uOps Per Cycle: 0.75
+# CHECK-NEXT: IPC: 0.50
# CHECK-NEXT: Block RThroughput: 7.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 01234
+# CHECK-NEXT: Index 0123456789 0
-# CHECK: [0,0] DeeeE. . . . . ld2 { v1.2s, v2.2s }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . . ld2 { v1.4h, v2.4h }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeeeE. . . ld2 { v1.4s, v2.4s }, [x27], x28
-# CHECK-NEXT: [0,5] . . . DE. . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . . ld2 { v1.8b, v2.8b }, [x27], x28
-# CHECK-NEXT: [0,7] . . . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . DeeeeeE ld2 { v1.8h, v2.8h }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeE. . . . ld2 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeE . . . ld2 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeE . . ld2 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeE . ld2 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . .DeeeE ld2 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2128,28 +2128,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2201
+# CHECK-NEXT: Total Cycles: 2001
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.68
-# CHECK-NEXT: IPC: 0.45
-# CHECK-NEXT: Block RThroughput: 6.0
+# CHECK-NEXT: uOps Per Cycle: 0.75
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 012
+# CHECK-NEXT: Index 0123456789 0
-# CHECK: [0,0] DeeeeeE . . . . ld2 { v1.16b, v2.16b }, [x27], x28
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . .DeeeE . . . ld2 { v1.b, v2.b }[0], [x27], #2
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE. . . ld2 { v1.b, v2.b }[8], [x27], #2
-# CHECK-NEXT: [0,5] . . . DE. . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . . ld2 { v1.b, v2.b }[0], [x27], x28
-# CHECK-NEXT: [0,7] . . . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . DeeeE ld2 { v1.b, v2.b }[8], [x27], x28
-# CHECK-NEXT: [0,9] . . . . .DE add x0, x27, #1
+# CHECK: [0,0] DeeeE. . . . ld2 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeE . . . ld2 { v1.b, v2.b }[0], [x27], #2
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeE . . ld2 { v1.b, v2.b }[8], [x27], #2
+# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeE . ld2 { v1.b, v2.b }[0], [x27], x28
+# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . .DeeeE ld2 { v1.b, v2.b }[8], [x27], x28
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2180,7 +2180,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2220,28 +2220,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1801
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.56
+# CHECK-NEXT: Block RThroughput: 8.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld2 { v1.s, v2.s }[0], [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld2 { v1.d, v2.d }[0], [x27], #16
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld2 { v1.d, v2.d }[0], [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld2r { v1.1d, v2.1d }, [x27], #16
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld2r { v1.2d, v2.2d }, [x27], #16
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeE. . . . ld2 { v1.s, v2.s }[0], [x27], x28
+# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeE . . . ld2 { v1.d, v2.d }[0], [x27], #16
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeE . . ld2 { v1.d, v2.d }[0], [x27], x28
+# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeE . ld2r { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld2r { v1.2d, v2.2d }, [x27], #16
+# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2266,28 +2266,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld2r { v1.2s, v2.2s }, [x27], #8
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld2r { v1.4h, v2.4h }, [x27], #4
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld2r { v1.4s, v2.4s }, [x27], #8
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld2r { v1.8b, v2.8b }, [x27], #2
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld2r { v1.8h, v2.8h }, [x27], #4
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld2r { v1.2s, v2.2s }, [x27], #8
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld2r { v1.4h, v2.4h }, [x27], #4
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld2r { v1.4s, v2.4s }, [x27], #8
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld2r { v1.8b, v2.8b }, [x27], #2
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld2r { v1.8h, v2.8h }, [x27], #4
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2312,28 +2312,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 1501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 0.67
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . . ld2r { v1.16b, v2.16b }, [x27], #2
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld2r { v1.1d, v2.1d }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld2r { v1.2d, v2.2d }, [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld2r { v1.2s, v2.2s }, [x27], x28
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld2r { v1.4h, v2.4h }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . ld2r { v1.16b, v2.16b }, [x27], #2
+# CHECK-NEXT: [0,1] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . ld2r { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . ld2r { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,5] . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . ld2r { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,7] . . .DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeE ld2r { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,9] . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2358,28 +2358,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2101
+# CHECK-NEXT: Total Cycles: 1701
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.71
-# CHECK-NEXT: IPC: 0.48
-# CHECK-NEXT: Block RThroughput: 5.5
+# CHECK-NEXT: uOps Per Cycle: 0.88
+# CHECK-NEXT: IPC: 0.59
+# CHECK-NEXT: Block RThroughput: 7.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 01
+# CHECK-NEXT: 01234567
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeE. . . .. ld2r { v1.4s, v2.4s }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . .. add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . .. ld2r { v1.8b, v2.8b }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . .. add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . .. ld2r { v1.8h, v2.8h }, [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . .. add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE .. ld2r { v1.16b, v2.16b }, [x27], x28
-# CHECK-NEXT: [0,7] . . . DE .. add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeeE ld3 { v1.2d, v2.2d, v3.2d }, [x27], #48
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeE . . . . ld2r { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeE . . . ld2r { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,3] . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . .DeeE. . . ld2r { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,5] . . DE. . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . DeeE . . ld2r { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,7] . . .DE . . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . DeeeeE ld3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,9] . . . .DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2410,7 +2410,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.60
# CHECK-NEXT: IPC: 0.40
-# CHECK-NEXT: Block RThroughput: 7.5
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2456,7 +2456,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.60
# CHECK-NEXT: IPC: 0.40
-# CHECK-NEXT: Block RThroughput: 7.5
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2496,28 +2496,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2301
+# CHECK-NEXT: Total Cycles: 2501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.65
-# CHECK-NEXT: IPC: 0.43
-# CHECK-NEXT: Block RThroughput: 6.5
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0123
-
-# CHECK: [0,0] DeeeeE . . . . ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
-# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeeE . . . ld3 { v1.8h, v2.8h, v3.8h }, [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeeE . . ld3 { v1.16b, v2.16b, v3.16b }, [x27], x28
-# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE. . ld3 { v1.b, v2.b, v3.b }[0], [x27], #3
-# CHECK-NEXT: [0,7] . . . . DE. . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . DeeeE ld3 { v1.b, v2.b, v3.b }[8], [x27], #3
-# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
+# CHECK-NEXT: Index 0123456789 012345
+
+# CHECK: [0,0] DeeeeE . . . . ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE . . . ld3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE . . ld3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE . ld3 { v1.b, v2.b, v3.b }[0], [x27], #3
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld3 { v1.b, v2.b, v3.b }[8], [x27], #3
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2542,28 +2542,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 2501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: Index 0123456789 012345
-# CHECK: [0,0] DeeeE. . . . ld3 { v1.b, v2.b, v3.b }[0], [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld3 { v1.b, v2.b, v3.b }[8], [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld3 { v1.h, v2.h, v3.h }[0], [x27], #6
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld3 { v1.h, v2.h, v3.h }[4], [x27], #6
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld3 { v1.h, v2.h, v3.h }[0], [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeE . . . . ld3 { v1.b, v2.b, v3.b }[0], [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE . . . ld3 { v1.b, v2.b, v3.b }[8], [x27], x28
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE . . ld3 { v1.h, v2.h, v3.h }[0], [x27], #6
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE . ld3 { v1.h, v2.h, v3.h }[4], [x27], #6
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld3 { v1.h, v2.h, v3.h }[0], [x27], x28
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2588,28 +2588,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 2501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: Index 0123456789 012345
-# CHECK: [0,0] DeeeE. . . . ld3 { v1.h, v2.h, v3.h }[4], [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld3 { v1.s, v2.s, v3.s }[0], [x27], #12
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld3 { v1.s, v2.s, v3.s }[0], [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld3 { v1.d, v2.d, v3.d }[0], [x27], #24
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld3 { v1.d, v2.d, v3.d }[0], [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeE . . . . ld3 { v1.h, v2.h, v3.h }[4], [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE . . . ld3 { v1.s, v2.s, v3.s }[0], [x27], #12
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE . . ld3 { v1.s, v2.s, v3.s }[0], [x27], x28
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE . ld3 { v1.d, v2.d, v3.d }[0], [x27], #24
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld3 { v1.d, v2.d, v3.d }[0], [x27], x28
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2640,7 +2640,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2686,7 +2686,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2732,7 +2732,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -2772,28 +2772,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2801
+# CHECK-NEXT: Total Cycles: 2401
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.54
-# CHECK-NEXT: IPC: 0.36
-# CHECK-NEXT: Block RThroughput: 9.0
+# CHECK-NEXT: uOps Per Cycle: 0.62
+# CHECK-NEXT: IPC: 0.42
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 012345678
-
-# CHECK: [0,0] DeeeE. . . . . . ld3r { v1.16b, v2.16b, v3.16b }, [x27], x28
-# CHECK-NEXT: [0,1] . DE. . . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeeeE . . . . ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
-# CHECK-NEXT: [0,3] . . DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeeeE . . . ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
-# CHECK-NEXT: [0,5] . . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . .DeeeeeE . . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
-# CHECK-NEXT: [0,7] . . . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
-# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeE. . . . . ld3r { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,1] . DE. . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE. . . . ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: [0,3] . . DE. . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE. . . ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: [0,5] . . . DE. . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE. . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: [0,7] . . . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2818,28 +2818,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 3001
+# CHECK-NEXT: Total Cycles: 2501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.50
-# CHECK-NEXT: IPC: 0.33
-# CHECK-NEXT: Block RThroughput: 10.0
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 16.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789 0
-# CHECK-NEXT: Index 0123456789 0123456789
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012345
-# CHECK: [0,0] DeeeeeE . . . . . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
-# CHECK-NEXT: [0,1] . DE . . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . .DeeeeeE . . . . ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
-# CHECK-NEXT: [0,3] . . .DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . . DeeeeeE . . . ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
-# CHECK-NEXT: [0,5] . . . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . . DeeeeeE. . ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
-# CHECK-NEXT: [0,7] . . . . . DE. . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeE . . . . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE . . . ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE . . ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE . ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2864,28 +2864,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 3001
+# CHECK-NEXT: Total Cycles: 2501
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.50
-# CHECK-NEXT: IPC: 0.33
-# CHECK-NEXT: Block RThroughput: 10.0
+# CHECK-NEXT: uOps Per Cycle: 0.60
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 15.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789 0
-# CHECK-NEXT: Index 0123456789 0123456789
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012345
-# CHECK: [0,0] DeeeeeE . . . . . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
-# CHECK-NEXT: [0,1] . DE . . . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . .DeeeeeE . . . . ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
-# CHECK-NEXT: [0,3] . . .DE . . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . . DeeeeeE . . . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
-# CHECK-NEXT: [0,5] . . . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . . DeeeeeE. . ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
-# CHECK-NEXT: [0,7] . . . . . DE. . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
-# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeE . . . . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . DeeeeE . . . ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . DeeeeE . . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . DeeeeE . ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeeE ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2910,28 +2910,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 3001
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 20.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 0123456789 0
+# CHECK-NEXT: Index 0123456789 0123456789
-# CHECK: [0,0] DeeeE. . . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeeE . . . . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+# CHECK-NEXT: [0,1] . DE . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . .DeeeeeE . . . . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+# CHECK-NEXT: [0,3] . . .DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . . DeeeeeE . . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+# CHECK-NEXT: [0,5] . . . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . . DeeeeeE. . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+# CHECK-NEXT: [0,7] . . . . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -2956,28 +2956,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 3001
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 20.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: 0123456789 0
+# CHECK-NEXT: Index 0123456789 0123456789
-# CHECK: [0,0] DeeeE. . . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeeE . . . . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+# CHECK-NEXT: [0,1] . DE . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . .DeeeeeE . . . . ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+# CHECK-NEXT: [0,3] . . .DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . . DeeeeeE . . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+# CHECK-NEXT: [0,5] . . . . DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . . DeeeeeE. . ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+# CHECK-NEXT: [0,7] . . . . . DE. . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . . DeeeeeE ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+# CHECK-NEXT: [0,9] . . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -3002,28 +3002,28 @@ add x0, x27, 1
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 1000
-# CHECK-NEXT: Total Cycles: 2001
+# CHECK-NEXT: Total Cycles: 2401
# CHECK-NEXT: Total uOps: 1500
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.75
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: uOps Per Cycle: 0.62
+# CHECK-NEXT: IPC: 0.42
+# CHECK-NEXT: Block RThroughput: 14.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
+# CHECK-NEXT: Index 0123456789 01234
-# CHECK: [0,0] DeeeE. . . . ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
-# CHECK-NEXT: [0,1] . DE. . . . add x0, x27, #1
-# CHECK-NEXT: [0,2] . DeeeE . . . ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
-# CHECK-NEXT: [0,3] . . DE . . . add x0, x27, #1
-# CHECK-NEXT: [0,4] . . DeeeE . . ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
-# CHECK-NEXT: [0,5] . . .DE . . add x0, x27, #1
-# CHECK-NEXT: [0,6] . . . DeeeE . ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #32
-# CHECK-NEXT: [0,7] . . . DE . add x0, x27, #1
-# CHECK-NEXT: [0,8] . . . .DeeeE ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #16
-# CHECK-NEXT: [0,9] . . . . DE add x0, x27, #1
+# CHECK: [0,0] DeeeeeE . . . . ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+# CHECK-NEXT: [0,1] . DE . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] . .DeeeeeE . . . ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+# CHECK-NEXT: [0,3] . . .DE . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] . . . DeeeE . . ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: [0,5] . . . DE . . add x0, x27, #1
+# CHECK-NEXT: [0,6] . . . .DeeeE . ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #32
+# CHECK-NEXT: [0,7] . . . . DE . add x0, x27, #1
+# CHECK-NEXT: [0,8] . . . . DeeeE ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #16
+# CHECK-NEXT: [0,9] . . . . . DE add x0, x27, #1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -3054,7 +3054,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -3100,7 +3100,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.75
# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 5.0
+# CHECK-NEXT: Block RThroughput: 10.0
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
@@ -3146,7 +3146,7 @@ add x0, x27, 1
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.94
# CHECK-NEXT: IPC: 0.56
-# CHECK-NEXT: Block RThroughput: 5.7
+# CHECK-NEXT: Block RThroughput: 8.0
# CHECK: Timeline view:
# CHECK-NEXT: 012345678
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