[llvm] [MachineScheduler] Don't add redundant dependencies (PR #205613)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 10:59:12 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Arthur Eubanks (aeubanks)
<details>
<summary>Changes</summary>
In addChainDependencies(), we'd run into quadratic behavior trying to add dependencies from every SUnit to all other SUnits.
We don't need to add a dependency if the dependency already exists transitively.
Reduces runtime with an arbitrarily large -dag-maps-huge-region from 6.4s to 2s on a case I'm looking at with lots of dependencies.
---
Patch is 743.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/205613.diff
9 Files Affected:
- (modified) llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h (+2-6)
- (modified) llvm/lib/CodeGen/ScheduleDAGInstrs.cpp (+35-3)
- (modified) llvm/test/CodeGen/AArch64/misched-bundle.mir (+7-19)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll (+70-70)
- (modified) llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll (+9-8)
- (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll (+3320-3340)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll (+794-808)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll (+395-397)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index 85613c072dc76..aa4ed4c94a331 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -221,14 +221,10 @@ namespace llvm {
/// Adds a chain edge between SUa and SUb, but only if both
/// AAResults and Target fail to deny the dependency.
- void addChainDependency(SUnit *SUa, SUnit *SUb,
- unsigned Latency = 0);
+ bool addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency = 0);
/// Adds dependencies as needed from all SUs in list to SU.
- void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) {
- for (SUnit *Entry : SUs)
- addChainDependency(SU, Entry, Latency);
- }
+ void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency);
/// Adds dependencies as needed from all SUs in map, to SU.
void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 6f42de464cb5b..52a6ee208d4d6 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -15,6 +15,7 @@
#include "llvm/ADT/IntEqClasses.h"
#include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/ADT/iterator_range.h"
@@ -556,14 +557,15 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
}
}
-
-void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
- unsigned Latency) {
+bool ScheduleDAGInstrs::addChainDependency(SUnit *SUa, SUnit *SUb,
+ unsigned Latency) {
if (SUa->getInstr()->mayAlias(getAAForDep(), *SUb->getInstr(), UseTBAA)) {
SDep Dep(SUa, SDep::MayAliasMem);
Dep.setLatency(Latency);
SUb->addPred(Dep);
+ return true;
}
+ return false;
}
/// Creates an SUnit for each real instruction, numbered in top-down
@@ -680,6 +682,36 @@ class ScheduleDAGInstrs::Value2SUsMap
void dump();
};
+static void collectTransitiveSuccessors(SUnit *SU,
+ SmallPtrSetImpl<SUnit *> &Res) {
+ SmallVector<SUnit *, 16> WorkList;
+ WorkList.push_back(SU);
+ while (!WorkList.empty()) {
+ SUnit *Curr = WorkList.pop_back_val();
+ for (const SDep &SuccDep : Curr->Succs) {
+ SUnit *Succ = SuccDep.getSUnit();
+ if (Res.insert(Succ).second)
+ WorkList.push_back(Succ);
+ }
+ }
+}
+
+void ScheduleDAGInstrs::addChainDependencies(SUnit *SU, SUList &SUs,
+ unsigned Latency) {
+ // Skip adding transitive dependencies, as addChainDependency() can be
+ // expensive. SUs begins with instructions later in the block, so iterate
+ // backwards to get as many transitive successors as possible in the first
+ // couple iterations.
+ SmallPtrSet<SUnit *, 16> RedundantSUs;
+ for (auto I = SUs.rbegin(), E = SUs.rend(); I != E; ++I) {
+ SUnit *Entry = *I;
+ if (RedundantSUs.count(Entry))
+ continue;
+ if (addChainDependency(SU, Entry, Latency))
+ collectTransitiveSuccessors(Entry, RedundantSUs);
+ }
+}
+
void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
Value2SUsMap &Val2SUsMap) {
for (auto &I : Val2SUsMap)
diff --git a/llvm/test/CodeGen/AArch64/misched-bundle.mir b/llvm/test/CodeGen/AArch64/misched-bundle.mir
index 8463cb038a3bc..a6d218783b87f 100644
--- a/llvm/test/CodeGen/AArch64/misched-bundle.mir
+++ b/llvm/test/CodeGen/AArch64/misched-bundle.mir
@@ -5,7 +5,7 @@
# CHECK: SU(0): renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 4
+# CHECK-NEXT: # succs left : 3
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
@@ -13,12 +13,11 @@
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(6): Out Latency=1
# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z0
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(1): renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 9
+# CHECK-NEXT: # succs left : 8
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
@@ -31,55 +30,50 @@
# CHECK-NEXT: SU(7): Out Latency=1
# CHECK-NEXT: SU(7): Out Latency=1
# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z1
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(2): renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 3
+# CHECK-NEXT: # succs left : 2
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 7
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z2
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(3): renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 3
+# CHECK-NEXT: # succs left : 2
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 7
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(7): Data Latency=3 Reg=$z3
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(4): renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 3
+# CHECK-NEXT: # succs left : 2
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 7
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(7): Data Latency=3 Reg=$z4
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(5): renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 3
+# CHECK-NEXT: # succs left : 2
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 7
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(7): Data Latency=3 Reg=$z5
-# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(6): $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0(tied-def 0), killed renamable $z1, killed renamable $z2
@@ -148,7 +142,7 @@
# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(9): ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
-# CHECK-NEXT: # preds left : 8
+# CHECK-NEXT: # preds left : 2
# CHECK-NEXT: # succs left : 0
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 1
@@ -157,12 +151,6 @@
# CHECK-NEXT: Predecessors:
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
# CHECK-NEXT: SU(7): Data Latency=4 Reg=$z1
-# CHECK-NEXT: SU(5): Ord Latency=0 Memory
-# CHECK-NEXT: SU(4): Ord Latency=0 Memory
-# CHECK-NEXT: SU(3): Ord Latency=0 Memory
-# CHECK-NEXT: SU(2): Ord Latency=0 Memory
-# CHECK-NEXT: SU(1): Ord Latency=0 Memory
-# CHECK-NEXT: SU(0): Ord Latency=0 Memory
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: ExitSU: RET_ReallyLR
# CHECK-NEXT: # preds left : 0
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
index e3f35f86ec92a..004f6e22303e1 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
@@ -609,51 +609,51 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #560]
; NONEON-NOSVE-NEXT: str w8, [sp, #400] // 4-byte Spill
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #436]
-; NONEON-NOSVE-NEXT: str q5, [sp, #544]
+; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #608]
; NONEON-NOSVE-NEXT: str w8, [sp, #396] // 4-byte Spill
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #438]
-; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #608]
-; NONEON-NOSVE-NEXT: str w8, [sp, #392] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #440]
; NONEON-NOSVE-NEXT: ldrh w15, [sp, #638]
; NONEON-NOSVE-NEXT: stp q7, q21, [sp, #640]
; NONEON-NOSVE-NEXT: ldrh w16, [sp, #636]
; NONEON-NOSVE-NEXT: ldrh w17, [sp, #634]
-; NONEON-NOSVE-NEXT: str w8, [sp, #388] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #442]
+; NONEON-NOSVE-NEXT: str w8, [sp, #392] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #440]
; NONEON-NOSVE-NEXT: ldrh w9, [sp, #666]
-; NONEON-NOSVE-NEXT: str q3, [sp, #416]
+; NONEON-NOSVE-NEXT: str q5, [sp, #544]
; NONEON-NOSVE-NEXT: ldrh w18, [sp, #632]
; NONEON-NOSVE-NEXT: ldrh w0, [sp, #630]
-; NONEON-NOSVE-NEXT: str w8, [sp, #384] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #444]
+; NONEON-NOSVE-NEXT: str w8, [sp, #388] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #442]
; NONEON-NOSVE-NEXT: ldrh w1, [sp, #628]
+; NONEON-NOSVE-NEXT: str q3, [sp, #416]
; NONEON-NOSVE-NEXT: ldrh w2, [sp, #626]
; NONEON-NOSVE-NEXT: ldrh w3, [sp, #624]
+; NONEON-NOSVE-NEXT: str w8, [sp, #384] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #444]
; NONEON-NOSVE-NEXT: ldrh w4, [sp, #622]
-; NONEON-NOSVE-NEXT: str w8, [sp, #380] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #446]
; NONEON-NOSVE-NEXT: ldrh w5, [sp, #620]
; NONEON-NOSVE-NEXT: ldrh w6, [sp, #618]
; NONEON-NOSVE-NEXT: ldrh w7, [sp, #616]
+; NONEON-NOSVE-NEXT: str w8, [sp, #380] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #446]
; NONEON-NOSVE-NEXT: ldrh w19, [sp, #614]
-; NONEON-NOSVE-NEXT: str w8, [sp, #376] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #480]
; NONEON-NOSVE-NEXT: ldrh w20, [sp, #612]
; NONEON-NOSVE-NEXT: ldrh w21, [sp, #610]
; NONEON-NOSVE-NEXT: ldrh w22, [sp, #608]
+; NONEON-NOSVE-NEXT: str w8, [sp, #376] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #480]
; NONEON-NOSVE-NEXT: ldrh w23, [sp, #430]
-; NONEON-NOSVE-NEXT: str w8, [sp, #372] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #482]
; NONEON-NOSVE-NEXT: ldrh w24, [sp, #428]
; NONEON-NOSVE-NEXT: ldrh w25, [sp, #426]
; NONEON-NOSVE-NEXT: ldrh w26, [sp, #424]
+; NONEON-NOSVE-NEXT: str w8, [sp, #372] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #482]
; NONEON-NOSVE-NEXT: ldrh w27, [sp, #422]
-; NONEON-NOSVE-NEXT: str w8, [sp, #368] // 4-byte Spill
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #484]
; NONEON-NOSVE-NEXT: ldrh w28, [sp, #420]
; NONEON-NOSVE-NEXT: ldrh w29, [sp, #418]
; NONEON-NOSVE-NEXT: strb w30, [sp, #767]
+; NONEON-NOSVE-NEXT: str w8, [sp, #368] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #484]
; NONEON-NOSVE-NEXT: str w8, [sp, #364] // 4-byte Spill
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #486]
; NONEON-NOSVE-NEXT: str w8, [sp, #360] // 4-byte Spill
@@ -2101,30 +2101,30 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: ldr w30, [sp, #376]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #136] // 8-byte Folded Spill
; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #168]
-; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #288]
; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #336]
-; NONEON-NOSVE-NEXT: ldr w3, [sp, #300]
-; NONEON-NOSVE-NEXT: ldr w4, [sp, #296]
-; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #128] // 8-byte Folded Spill
; NONEON-NOSVE-NEXT: ldr w11, [sp, #360]
; NONEON-NOSVE-NEXT: ldr w12, [sp, #356]
-; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #208]
; NONEON-NOSVE-NEXT: ldr w13, [sp, #352]
+; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #128] // 8-byte Folded Spill
; NONEON-NOSVE-NEXT: ldr w14, [sp, #348]
; NONEON-NOSVE-NEXT: ldr w15, [sp, #344]
+; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #208]
; NONEON-NOSVE-NEXT: str q3, [sp, #144]
; NONEON-NOSVE-NEXT: ldr w16, [sp, #340]
; NONEON-NOSVE-NEXT: ldr w17, [sp, #336]
+; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #288]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120] // 8-byte Folded Spill
+; NONEON-NOSVE-NEXT: ldr w3, [sp, #300]
+; NONEON-NOSVE-NEXT: ldr w4, [sp, #296]
; NONEON-NOSVE-NEXT: ldr w6, [sp, #292]
-; NONEON-NOSVE-NEXT: ldr w7, [sp, #288]
; NONEON-NOSVE-NEXT: str q5, [sp, #272]
-; NONEON-NOSVE-NEXT: ldr w25, [sp, #316]
-; NONEON-NOSVE-NEXT: ldr w26, [sp, #312]
+; NONEON-NOSVE-NEXT: ldr w7, [sp, #288]
; NONEON-NOSVE-NEXT: ldr w19, [sp, #284]
; NONEON-NOSVE-NEXT: ldr w20, [sp, #280]
; NONEON-NOSVE-NEXT: ldr w22, [sp, #276]
; NONEON-NOSVE-NEXT: ldr w24, [sp, #272]
+; NONEON-NOSVE-NEXT: ldr w25, [sp, #316]
+; NONEON-NOSVE-NEXT: ldr w26, [sp, #312]
; NONEON-NOSVE-NEXT: ldr w27, [sp, #308]
; NONEON-NOSVE-NEXT: ldr w28, [sp, #304]
; NONEON-NOSVE-NEXT: strh w21, [sp, #494]
@@ -2990,10 +2990,19 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: ldr w3, [sp, #56]
; NONEON-NOSVE-NEXT: add w9, w9, w9
; NONEON-NOSVE-NEXT: ldr w18, [sp, #80]
-; NONEON-NOSVE-NEXT: stp q22, q16, [sp, #112]
-; NONEON-NOSVE-NEXT: stp q6, q5, [sp, #208]
; NONEON-NOSVE-NEXT: ldr w0, [sp, #88]
+; NONEON-NOSVE-NEXT: strh w9, [sp, #308]
; NONEON-NOSVE-NEXT: ldr w16, [sp, #32]
+; NONEON-NOSVE-NEXT: ldr w17, [sp, #40]
+; NONEON-NOSVE-NEXT: str q7, [sp, #16]
+; NONEON-NOSVE-NEXT: ldr w12, [sp, #96]
+; NONEON-NOSVE-NEXT: ldr w13, [sp, #104]
+; NONEON-NOSVE-NEXT: ldr w20, [sp, #24]
+; NONEON-NOSVE-NEXT: stp q22, q16, [sp, #112]
+; NONEON-NOSVE-NEXT: ldr w19, [sp, #16]
+; NONEON-NOSVE-NEXT: stp q6, q5, [sp, #208]
+; NONEON-NOSVE-NEXT: ldr w14, [sp, #112]
+; NONEON-NOSVE-NEXT: ldr w15, [sp, #120]
; NONEON-NOSVE-NEXT: stp q3, q17, [sp, #240]
; NONEON-NOSVE-NEXT: ldr w23, [sp, #224]
; NONEON-NOSVE-NEXT: ldr w24, [sp, #232]
@@ -3001,50 +3010,41 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: ldr w8, [sp, #264]
; NONEON-NOSVE-NEXT: ldr w27, [sp, #240]
; NONEON-NOSVE-NEXT: ldr w28, [sp, #248]
-; NONEON-NOSVE-NEXT: strh w9, [sp, #308]
; NONEON-NOSVE-NEXT: ldr w21, [sp, #208]
+; NONEON-NOSVE-NEXT: ldr w22, [sp, #216]
; NONEON-NOSVE-NEXT: add w9, w27, w27
; NONEON-NOSVE-NEXT: stp w8, w10, [sp, #8] // 8-byte Folded Spill
; NONEON-NOSVE-NEXT: ldr w8, [sp, #184]
-; NONEON-NOSVE-NEXT: str q7, [sp, #16]
-; NONEON-NOSVE-NEXT: ldr w22, [sp, #216]
-; NONEON-NOSVE-NEXT: ldr w17, [sp, #40]
-; NONEON-NOSVE-NEXT: add w8, w8, w8
; NONEON-NOSVE-NEXT: strh w9, [sp, #304]
; NONEON-NOSVE-NEXT: add w9, w25, w25
+; NONEON-NOSVE-NEXT: ldr w10, [sp, #128]
+; NONEON-NOSVE-NEXT: add w8, w8, w8
+; NONEON-NOSVE-NEXT: str q18, [sp, #64]
+; NONEON-NOSVE-NEXT: ldr w11, [sp, #136]
; NONEON-NOSVE-NEXT: strh w8, [sp, #310]
; NONEON-NOSVE-NEXT: add w8, w28, w28
-; NONEON-NOSVE-NEXT: ldr w19, [sp, #16]
+; NONEON-NOSVE-NEXT: ldr w4, [sp, #64]
; NONEON-NOSVE-NEXT: strh w8, [sp, #306]
; NONEON-NOSVE-NEXT: add w8, w26, w26
-; NONEON-NOSVE-NEXT: ldr w20, [sp, #24]
-; NONEON-NOSVE-NEXT: str q18, [sp, #64]
-; NONEON-NOSVE-NEXT: ldr w14, [sp, #112]
-; NONEON-NOSVE-NEXT: ldr w15, [sp, #120]
+; NONEON-NOSVE-NEXT: ldr w7, [sp, #72]
; NONEON-NOSVE-NEXT: strh w8, [sp, #302]
; NONEON-NOSVE-NEXT: add w8, w24, w24
-; NONEON-NOSVE-NEXT: ldr w4, [sp, #64]
+; NONEON-NOSVE-NEXT: ldr w29, [sp, #144]
; NONEON-NOSVE-NEXT: strh w9, [sp, #300]
; NONEON-NOSVE-NEXT: add w9, w23, w23
-; NONEON-NOSVE-NEXT: ldr w7, [sp, #72]
+; NONEON-NOSVE-NEXT: ldr w30, [sp, #152]
; NONEON-NOSVE-NEXT: strh w8, [sp, #298]
; NONEON-NOSVE-NEXT: add w8, w22, w22
-; NONEON-NOSVE-NEXT: ldr w12, [sp, #96]
; NONEON-NOSVE-NEXT: strh w9, [sp, #296]
; NONEON-NOSVE-NEXT: add w9, w21, w21
-; NONEON-NOSVE-NEXT: ldr w13, [sp, #104]
; NONEON-NOSVE-NEXT: strh w8, [sp, #294]
; NONEON-NOSVE-NEXT: add w8, w20, w20
-; NONEON-NOSVE-NEXT: ldr w10, [sp, #128]
; NONEON-NOSVE-NEXT: strh w9, [sp, #292]
; NONEON-NOSVE-NEXT: add w9, w19, w19
-; NONEON-NOSVE-NEXT: ldr w11, [sp, #136]
; NONEON-NOSVE-NEXT: strh w8, [sp, #290]
; NONEON-NOSVE-NEXT: add w8, w7, w7
-; NONEON-NOSVE-NEXT: ldr w29, [sp, #144]
; NONEON-NOSVE-NEXT: strh w9, [sp, #288]
; NONEON-NOSVE-NEXT: add w9, w4, w4
-; NONEON-NOSVE-NEXT: ldr w30, [sp, #152]
; NONEON-NOSVE-NEXT: strh w8, [sp, #286]
; NONEON-NOSVE-NEXT: add w8, w3, w3
; NONEON-NOSVE-NEXT: strh w9, [sp, #284]
@@ -3073,9 +3073,9 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: ldr w8, [sp, #8] // 4-byte Reload
; NONEON-NOSVE-NEXT: strh w9, [sp, #324]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #12] // 4-byte Reload
-; NONEON-NOSVE-NEXT: add w8, w8, w8
; NONEON-NOSVE-NEXT: strh w5, [sp, #318]
; NONEON-NOSVE-NEXT: add w5, w30, w30
+; NONEON-NOSVE-NEXT: add w8, w8, w8
; NONEON-NOSVE-NEXT: strh w6, [sp, #316]
; NONEON-NOSVE-NEXT: add w6, w29, w29
; NONEON-NOSVE-NEXT: add w9, w9, w9
@@ -3090,8 +3090,8 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: ldp q2, q0, [sp, #304]
; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #368] // 16-byte Folded Reload
; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #352] // 16-byte Folded Reload
-; NONEON-NOSVE-NEXT: stp q3, q2, [x1]
; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #336] // 16-byte Folded Reload
+; NONEON-NOSVE-NEXT: stp q3, q2, [x1]
; NONEON-NOSVE-NEXT: stp q0, q1, [x1, #32]
; NONEON-NOSVE-NEXT: add sp, sp, #432
; NONEON-NOSVE-NEXT: ret
@@ -3354,38 +3354,41 @@ define void @trunc_v32i64_v32i32(ptr %in, ptr %out) nounwind {
; NONEON-NOSVE-NEXT: stp q17, q23, [sp, #32]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #200]
; NONEON-NOSVE-NEXT: ldr w10, [sp, #32]
-; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #160]
+; NONEON-NOSVE-NEXT: stp q22, q16, [sp, #64]
; NONEON-NOSVE-NEXT: ldr w12, [sp, #48]
; NONEON-NOSVE-NEXT: add w6, w8, w8
; NONEON-NOSVE-NEXT: add w5, w9, w9
; NONEON-NOSVE-NEXT: ldr w8, [sp, #40]
; NONEON-NOSVE-NEXT: stp q18, q20, [sp, #112]
-; NONEON-NOSVE-NEXT: ldr w25, [sp, #160]
-; NONEON-NOSVE-NEXT: ldr w26, [sp, #168]
-; NONEON-NOSVE-NEXT: str q5, [sp, #144]
-; NONEON-NOSVE-NEXT: ldr w21, [sp, #176]
-; NONEON-NOSVE-NEXT: ldr w22, [sp, #184]
+; NONEON-NOSVE-NEXT: ldr w14, [sp, #64]
+; NONEON-NOSVE-NEXT: ldr w15, [sp, #72]
; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #208]
-; NONEON-NOSVE-NEXT: ldr w23, [sp, #144]
-; NONEON-NOSVE-NEXT: ldr w24, [sp, #152]
+; NONEON-NOSVE-NEXT: ldr w4, [sp, #112]
+; NONEON-NOSVE-NEXT: ldr w7, [sp, #120]
; NONEON-NOSVE-NEXT: str q3, [sp, #16]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #208]
-; NONEON-NOSVE-NEXT: ldr w4, [sp, #112]
+; NONEON-NOSVE-NEXT: ldr w18, [sp, #128]
; NONEO...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205613
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