[clang] [compiler-rt] [llvm] [X86] Add AVX512BMM support for AMD Zen 6 (znver6) (PR #182556)

[via llvm-commits]

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@@ -2355,6 +2355,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
         setOperationAction(ISD::CTPOP, VT, Legal);
     }
+
+    if (Subtarget.hasBMM()) {
+      for (auto VT : {MVT::v16i8, MVT::v32i8, MVT::v64i8})
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ganeshgit wrote:

Yes, patterns exist for v16i8 and v32i8 without VLX. The setOperationAction(ISD::BITREVERSE, {v16i8,v32i8,v64i8}, Legal) relies on avx512_unary_lowering<"VPBITREVB", …>, whose [HasBMM, NoVLX] patterns widen the 128/256-bit ops to 512-bit zmm. Added the tests with VLX, NO-VLX checks!

https://github.com/llvm/llvm-project/pull/182556