[llvm] [GlobalISel] Don't push `freeze`s post-legalizer when that creates illegal instruction (PR #204785)
Ömer Sinan Ağacan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 04:06:30 PDT 2026
https://github.com/osa1 updated https://github.com/llvm/llvm-project/pull/204785
>From ef5b92b509ee94bd56d7b44f16cfbbf3020c00c5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Fri, 19 Jun 2026 09:55:53 +0100
Subject: [PATCH 1/8] [GlobalISel] Don't push `freeze`s post-legalizer when
that makes the operand illegal
---
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 6 ++
.../CodeGen/AArch64/GlobalISel/freeze-push.ll | 73 +++++++++++++++++++
2 files changed, 79 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 8853a941e137f..217074d54f46c 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -252,6 +252,8 @@ void CombinerHelper::applyCombineCopy(MachineInstr &MI) const {
bool CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(
MachineInstr &MI, BuildFnTy &MatchInfo) const {
+ assert(MI.getOpcode() == TargetOpcode::G_FREEZE && "Invalid instruction");
+
// Ported from InstCombinerImpl::pushFreezeToPreventPoisonFromPropagating.
Register DstOp = MI.getOperand(0).getReg();
Register OrigOp = MI.getOperand(1).getReg();
@@ -306,6 +308,10 @@ bool CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(
Register MaybePoisonOperandReg = MaybePoisonOperand->getReg();
LLT MaybePoisonOperandRegTy = MRI.getType(MaybePoisonOperandReg);
+ if (!isLegalOrBeforeLegalizer(
+ {TargetOpcode::G_FREEZE, {MaybePoisonOperandRegTy}}))
+ return false;
+
MatchInfo = [=](MachineIRBuilder &B) mutable {
Observer.changingInstr(*OrigDef);
cast<GenericMachineInstr>(OrigDef)->dropPoisonGeneratingFlags();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
new file mode 100644
index 0000000000000..dd84eb2e27a31
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm64-apple-macosx -global-isel < %s | FileCheck %s
+
+; In the combine rule
+;
+; // Convert freeze(Op(Op0, NonPoisonOps...)) to Op(freeze(Op0), NonPoisonOps...)
+; // when Op0 is not guaranteed non-poison
+; def push_freeze_to_prevent_poison_from_propagating ...
+;
+; Don't push the `freeze` if `freeze(Op0)` is illegal and we've already ; run
+; the legalizer.
+;
+; On AArch64, in the functions below, `freeze`s would be pushed all the way to
+; the `load`, which would then cause the crash:
+;
+; LLVM ERROR: instruction is not legal: %14:_(i128) = G_FREEZE %0:_ (in function: _0)
+
+define <4 x i32> @_0() {
+; CHECK-LABEL: _0:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: ldr q0, [x8]
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: mov.s v0[1], wzr
+; CHECK-NEXT: mov.s v0[2], wzr
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: ret
+entry:
+ %0 = load i128, ptr null, align 16
+ %1 = freeze i128 %0
+ %2 = insertelement <4 x i128> zeroinitializer, i128 %1, i64 0
+ %3 = trunc <4 x i128> %2 to <4 x i32>
+ ret <4 x i32> %3
+}
+
+define <4 x i32> @_1() {
+; CHECK-LABEL: _1:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: ldr q0, [x8]
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: mov.s v0[1], wzr
+; CHECK-NEXT: mov.s v0[2], wzr
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: ret
+entry:
+ %0 = load i128, ptr null, align 16
+ %1 = insertelement <4 x i128> zeroinitializer, i128 %0, i64 0
+ %2 = freeze <4 x i128> %1
+ %3 = trunc <4 x i128> %2 to <4 x i32>
+ ret <4 x i32> %3
+}
+
+define <4 x i32> @_2() {
+; CHECK-LABEL: _2:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: ldr q0, [x8]
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: mov.s v0[1], wzr
+; CHECK-NEXT: mov.s v0[2], wzr
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: ret
+entry:
+ %0 = load i128, ptr null, align 16
+ %1 = insertelement <4 x i128> zeroinitializer, i128 %0, i64 0
+ %2 = trunc <4 x i128> %1 to <4 x i32>
+ %3 = freeze <4 x i32> %2
+ ret <4 x i32> %3
+}
>From 6dc24688ac021e79941c2028539fd7390800bdc2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Fri, 19 Jun 2026 10:09:44 +0100
Subject: [PATCH 2/8] Formatting fix
---
llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
index dd84eb2e27a31..dd6e6d172ed5e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
@@ -7,7 +7,7 @@
; // when Op0 is not guaranteed non-poison
; def push_freeze_to_prevent_poison_from_propagating ...
;
-; Don't push the `freeze` if `freeze(Op0)` is illegal and we've already ; run
+; Don't push the `freeze` if `freeze(Op0)` is illegal and we've already run
; the legalizer.
;
; On AArch64, in the functions below, `freeze`s would be pushed all the way to
>From 4cf3636f715d0dfc0cca99862af48e39848a58fd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Fri, 19 Jun 2026 15:25:30 +0100
Subject: [PATCH 3/8] Simplify test
---
.../CodeGen/AArch64/GlobalISel/freeze-push.ll | 63 ++++---------------
1 file changed, 11 insertions(+), 52 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
index dd6e6d172ed5e..e9204ca17c8f0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
@@ -1,73 +1,32 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-apple-macosx -global-isel < %s | FileCheck %s
-; In the combine rule
-;
-; // Convert freeze(Op(Op0, NonPoisonOps...)) to Op(freeze(Op0), NonPoisonOps...)
-; // when Op0 is not guaranteed non-poison
-; def push_freeze_to_prevent_poison_from_propagating ...
-;
-; Don't push the `freeze` if `freeze(Op0)` is illegal and we've already run
-; the legalizer.
-;
-; On AArch64, in the functions below, `freeze`s would be pushed all the way to
-; the `load`, which would then cause the crash:
-;
-; LLVM ERROR: instruction is not legal: %14:_(i128) = G_FREEZE %0:_ (in function: _0)
-
-define <4 x i32> @_0() {
+define i32 @_0() {
; CHECK-LABEL: _0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: ldr q0, [x8]
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov.s v0[1], wzr
-; CHECK-NEXT: mov.s v0[2], wzr
-; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret
entry:
%0 = load i128, ptr null, align 16
%1 = freeze i128 %0
- %2 = insertelement <4 x i128> zeroinitializer, i128 %1, i64 0
- %3 = trunc <4 x i128> %2 to <4 x i32>
- ret <4 x i32> %3
+ %2 = trunc i128 %1 to i32
+ ret i32 %2
}
-define <4 x i32> @_1() {
+define i32 @_1() {
; CHECK-LABEL: _1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: ldr q0, [x8]
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov.s v0[1], wzr
-; CHECK-NEXT: mov.s v0[2], wzr
-; CHECK-NEXT: mov.s v0[3], wzr
-; CHECK-NEXT: ret
-entry:
- %0 = load i128, ptr null, align 16
- %1 = insertelement <4 x i128> zeroinitializer, i128 %0, i64 0
- %2 = freeze <4 x i128> %1
- %3 = trunc <4 x i128> %2 to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <4 x i32> @_2() {
-; CHECK-LABEL: _2:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: ldr q0, [x8]
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov.s v0[1], wzr
-; CHECK-NEXT: mov.s v0[2], wzr
-; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret
entry:
%0 = load i128, ptr null, align 16
- %1 = insertelement <4 x i128> zeroinitializer, i128 %0, i64 0
- %2 = trunc <4 x i128> %1 to <4 x i32>
- %3 = freeze <4 x i32> %2
- ret <4 x i32> %3
+ %1 = trunc i128 %0 to i32
+ %2 = freeze i32 %1
+ ret i32 %2
}
>From fede6acd327ac878eef111b129cd6045f69fec3e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Mon, 22 Jun 2026 09:12:40 +0100
Subject: [PATCH 4/8] Remove load from null
---
.../CodeGen/AArch64/GlobalISel/freeze-push.ll | 26 +++++++++----------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
index e9204ca17c8f0..807cae78ed549 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
@@ -1,32 +1,30 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-apple-macosx -global-isel < %s | FileCheck %s
-define i32 @_0() {
+define i32 @_0(ptr %0) {
; CHECK-LABEL: _0:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: ldr q0, [x8]
+; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret
entry:
- %0 = load i128, ptr null, align 16
- %1 = freeze i128 %0
- %2 = trunc i128 %1 to i32
- ret i32 %2
+ %1 = load i128, ptr %0, align 16
+ %2 = freeze i128 %1
+ %3 = trunc i128 %2 to i32
+ ret i32 %3
}
-define i32 @_1() {
+define i32 @_1(ptr %0) {
; CHECK-LABEL: _1:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: ldr q0, [x8]
+; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret
entry:
- %0 = load i128, ptr null, align 16
- %1 = trunc i128 %0 to i32
- %2 = freeze i32 %1
- ret i32 %2
+ %1 = load i128, ptr %0, align 16
+ %2 = trunc i128 %1 to i32
+ %3 = freeze i32 %2
+ ret i32 %3
}
>From 61b89a48350bc049d1b7757db622adbdabe7c82c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Mon, 22 Jun 2026 10:35:22 +0100
Subject: [PATCH 5/8] Convert test to mir
---
.../CodeGen/AArch64/GlobalISel/freeze-push.ll | 30 ---------
.../AArch64/GlobalISel/freeze-push.mir | 63 +++++++++++++++++++
2 files changed, 63 insertions(+), 30 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
deleted file mode 100644
index 807cae78ed549..0000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.ll
+++ /dev/null
@@ -1,30 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-apple-macosx -global-isel < %s | FileCheck %s
-
-define i32 @_0(ptr %0) {
-; CHECK-LABEL: _0:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
-; CHECK-NEXT: ret
-entry:
- %1 = load i128, ptr %0, align 16
- %2 = freeze i128 %1
- %3 = trunc i128 %2 to i32
- ret i32 %3
-}
-
-define i32 @_1(ptr %0) {
-; CHECK-LABEL: _1:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
-; CHECK-NEXT: ret
-entry:
- %1 = load i128, ptr %0, align 16
- %2 = trunc i128 %1 to i32
- %3 = freeze i32 %2
- ret i32 %3
-}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
new file mode 100644
index 0000000000000..4f03b1427b5a7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple=arm64-apple-macosx -global-isel -start-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+ define i32 @_0(ptr %0) {
+ ; CHECK-LABEL: _0:
+ ; CHECK: ; %bb.0: ; %entry
+ ; CHECK-NEXT: ldr q0, [x0]
+ ; CHECK-NEXT: fmov x0, d0
+ ; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
+ ; CHECK-NEXT: ret
+ entry:
+ %1 = load i128, ptr %0, align 16
+ %2 = freeze i128 %1
+ %3 = trunc i128 %2 to i32
+ ret i32 %3
+ }
+
+ define i32 @_1(ptr %0) {
+ ; CHECK-LABEL: _1:
+ ; CHECK: ; %bb.0: ; %entry
+ ; CHECK-NEXT: ldr q0, [x0]
+ ; CHECK-NEXT: fmov x0, d0
+ ; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
+ ; CHECK-NEXT: ret
+ entry:
+ %1 = load i128, ptr %0, align 16
+ %2 = trunc i128 %1 to i32
+ %3 = freeze i32 %2
+ ret i32 %3
+ }
+...
+---
+name: _0
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ %0:_(p0) = COPY $x0
+ %1:_(i128) = G_LOAD %0(p0) :: (load (i128) from %ir.0)
+ %2:_(i128) = G_FREEZE %1
+ %3:_(i32) = G_TRUNC %2(i128)
+ $w0 = COPY %3(i32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: _1
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ %0:_(p0) = COPY $x0
+ %1:_(i128) = G_LOAD %0(p0) :: (load (i128) from %ir.0)
+ %2:_(i32) = G_TRUNC %1(i128)
+ %3:_(i32) = G_FREEZE %2
+ $w0 = COPY %3(i32)
+ RET_ReallyLR implicit $w0
+...
>From f3e054b64666c852aa5a792565ed7caa46851932 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Wed, 24 Jun 2026 10:08:22 +0100
Subject: [PATCH 6/8] Simplify test
---
.../AArch64/GlobalISel/freeze-push.mir | 66 ++++++-------------
1 file changed, 21 insertions(+), 45 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
index 4f03b1427b5a7..819975e5847eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
@@ -1,63 +1,39 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple=arm64-apple-macosx -global-isel -start-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=arm64-apple-macosx -global-isel -run-pass=aarch64-postlegalizer-combiner %s -o - | FileCheck %s
--- |
+ ; ModuleID = 'llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir'
+ source_filename = "llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir"
+ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+
define i32 @_0(ptr %0) {
- ; CHECK-LABEL: _0:
- ; CHECK: ; %bb.0: ; %entry
- ; CHECK-NEXT: ldr q0, [x0]
- ; CHECK-NEXT: fmov x0, d0
- ; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
- ; CHECK-NEXT: ret
entry:
%1 = load i128, ptr %0, align 16
%2 = freeze i128 %1
%3 = trunc i128 %2 to i32
ret i32 %3
}
-
- define i32 @_1(ptr %0) {
- ; CHECK-LABEL: _1:
- ; CHECK: ; %bb.0: ; %entry
- ; CHECK-NEXT: ldr q0, [x0]
- ; CHECK-NEXT: fmov x0, d0
- ; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
- ; CHECK-NEXT: ret
- entry:
- %1 = load i128, ptr %0, align 16
- %2 = trunc i128 %1 to i32
- %3 = freeze i32 %2
- ret i32 %3
- }
...
---
name: _0
-tracksRegLiveness: true
-liveins:
- - { reg: '$x0' }
-body: |
- bb.1.entry:
- liveins: $x0
-
- %0:_(p0) = COPY $x0
- %1:_(i128) = G_LOAD %0(p0) :: (load (i128) from %ir.0)
- %2:_(i128) = G_FREEZE %1
- %3:_(i32) = G_TRUNC %2(i128)
- $w0 = COPY %3(i32)
- RET_ReallyLR implicit $w0
-...
----
-name: _1
-tracksRegLiveness: true
-liveins:
- - { reg: '$x0' }
+legalized: true
body: |
- bb.1.entry:
+ bb.0.entry:
liveins: $x0
-
+ ; CHECK-LABEL: name: _0
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[LOAD]](i128)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i64) = G_FREEZE [[TRUNC]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[FREEZE]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC1]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(i128) = G_LOAD %0(p0) :: (load (i128) from %ir.0)
- %2:_(i32) = G_TRUNC %1(i128)
- %3:_(i32) = G_FREEZE %2
+ %4:_(i64), %5:_(i64) = G_UNMERGE_VALUES %1(i128)
+ %6:_(i64) = G_FREEZE %4
+ %3:_(i32) = G_TRUNC %6(i64)
$w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
>From 7fc2cb78a31230821d62ed03c2ffa6ea60a07778 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Wed, 24 Jun 2026 11:24:38 +0100
Subject: [PATCH 7/8] Remove IR
---
.../CodeGen/AArch64/GlobalISel/freeze-push.mir | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
index 819975e5847eb..61b304c24ad5f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
@@ -1,18 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=arm64-apple-macosx -global-isel -run-pass=aarch64-postlegalizer-combiner %s -o - | FileCheck %s
---- |
- ; ModuleID = 'llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir'
- source_filename = "llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir"
- target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
-
- define i32 @_0(ptr %0) {
- entry:
- %1 = load i128, ptr %0, align 16
- %2 = freeze i128 %1
- %3 = trunc i128 %2 to i32
- ret i32 %3
- }
-...
---
name: _0
legalized: true
@@ -23,14 +10,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.0)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128))
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[LOAD]](i128)
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i64) = G_FREEZE [[TRUNC]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[FREEZE]](i64)
; CHECK-NEXT: $w0 = COPY [[TRUNC1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
- %1:_(i128) = G_LOAD %0(p0) :: (load (i128) from %ir.0)
+ %1:_(i128) = G_LOAD %0(p0) :: (load (i128))
%4:_(i64), %5:_(i64) = G_UNMERGE_VALUES %1(i128)
%6:_(i64) = G_FREEZE %4
%3:_(i32) = G_TRUNC %6(i64)
>From 279ba892ad606d524e8b57eea21d4a4d7db4164b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Wed, 24 Jun 2026 12:05:23 +0100
Subject: [PATCH 8/8] Address comments
---
llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
index 61b304c24ad5f..5542c4bb23e0a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/freeze-push.mir
@@ -1,12 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=arm64-apple-macosx -global-isel -run-pass=aarch64-postlegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-macosx -run-pass=aarch64-postlegalizer-combiner %s -o - | FileCheck %s
---
-name: _0
+name: freeze_illegal_push
legalized: true
body: |
bb.0.entry:
liveins: $x0
- ; CHECK-LABEL: name: _0
+ ; CHECK-LABEL: name: freeze_illegal_push
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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