[llvm] [AMDGPU] Select S_CSELECT_B32/64 for uniform extensions from i1 (PR #204238)

[Matt Arsenault via llvm-commits]

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@@ -8687,14 +8687,30 @@ void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
   Register CondReg = Cond.getReg();
   bool IsSCC = (CondReg == AMDGPU::SCC);
 
-  // If this is a trivial select where the condition is effectively not SCC
-  // (CondReg is a source of copy to SCC), then the select is semantically
-  // equivalent to copying CondReg. Hence, there is no need to create
-  // V_CNDMASK, we can just use that and bail out.
+  // Remove S_CSELECT instructions that we previously inserted to feed the SCC
+  // condition output from S_CMP into the SGPR condition input of V_CNDMASK. If
+  // the S_CMP has been promoted to V_CMP then we can feed its SGPR condition
+  // output directly into the V_CNDMASK.
   if (!IsSCC && Src0.isImm() && (Src0.getImm() == -1) && Src1.isImm() &&
       (Src1.getImm() == 0)) {
-    MRI.replaceRegWith(Dest.getReg(), CondReg);
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arsenm wrote:

This whole special casing of SCC copies is really broken. This code simply doesn't have the context to guess at how to interpret them. Trying to avoid this busted path was what we were trying to get at with the InstrEmitter changes in #174539

https://github.com/llvm/llvm-project/pull/204238