[llvm] [AArch64][SVE] add missing MLA commute instcombine (PR #205526)
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 03:49:29 PDT 2026
https://github.com/tommat01 created https://github.com/llvm/llvm-project/pull/205526
Split from https://github.com/llvm/llvm-project/pull/198566
>From 096bfdd5ef40e21b007525fcd61698806bf474bd Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Tue, 16 Jun 2026 18:03:40 +0100
Subject: [PATCH 1/2] [AArch64][SVE] Add baseline mul imm InstCombine test
---
.../AArch64/sve-intrinsic-mul-imm-add-adr.ll | 153 ++++++++++++++++++
1 file changed, 153 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
new file mode 100644
index 0000000000000..cc6641d35eaae
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
@@ -0,0 +1,153 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=instcombine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 2 x i64> @mul_i64_by_2_commuted(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mul_i64_by_2_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = shl <vscale x 2 x i64> [[X]], splat (i64 1)
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = mul <vscale x 2 x i64> splat(i64 2), %x
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mul_i64_by_3_commuted(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mul_i64_by_3_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = mul <vscale x 2 x i64> [[X]], splat (i64 3)
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = mul <vscale x 2 x i64> splat(i64 3), %x
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mul_i64_by_5_commuted(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mul_i64_by_5_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = mul <vscale x 2 x i64> [[X]], splat (i64 5)
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = mul <vscale x 2 x i64> splat(i64 5), %x
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mul_i64_by_9_commuted(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mul_i64_by_9_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = mul <vscale x 2 x i64> [[X]], splat (i64 9)
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = mul <vscale x 2 x i64> splat(i64 9), %x
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mla_i64_by_2_commuted(<vscale x 2 x i64> %a, <vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mla_i64_by_2_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[MUL:%.*]] = shl <vscale x 2 x i64> [[X]], splat (i64 1)
+; CHECK-NEXT: [[OUT:%.*]] = add <vscale x 2 x i64> [[A]], [[MUL]]
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %mul = mul <vscale x 2 x i64> splat(i64 2), %x
+ %out = add <vscale x 2 x i64> %a, %mul
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mla_i64_by_4_commuted(<vscale x 2 x i64> %a, <vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mla_i64_by_4_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[MUL:%.*]] = shl <vscale x 2 x i64> [[X]], splat (i64 2)
+; CHECK-NEXT: [[OUT:%.*]] = add <vscale x 2 x i64> [[A]], [[MUL]]
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %mul = mul <vscale x 2 x i64> splat(i64 4), %x
+ %out = add <vscale x 2 x i64> %a, %mul
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @mla_i64_by_8_commuted(<vscale x 2 x i64> %a, <vscale x 2 x i64> %x) {
+; CHECK-LABEL: define <vscale x 2 x i64> @mla_i64_by_8_commuted(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[X:%.*]]) {
+; CHECK-NEXT: [[MUL:%.*]] = shl <vscale x 2 x i64> [[X]], splat (i64 3)
+; CHECK-NEXT: [[OUT:%.*]] = add <vscale x 2 x i64> [[A]], [[MUL]]
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %mul = mul <vscale x 2 x i64> splat(i64 8), %x
+ %out = add <vscale x 2 x i64> %a, %mul
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 4 x i32> @svmul_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmul_u_i32_by_2_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 2))
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat(i32 2), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmul_u_i32_by_3_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmul_u_i32_by_3_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat(i32 3), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmul_u_i32_by_5_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmul_u_i32_by_5_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 5))
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat(i32 5), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmul_u_i32_by_9_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmul_u_i32_by_9_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 9))
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat(i32 9), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 2), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 4), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @svmla_u_i32_by_8_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
+; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_8_commuted(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 8), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 8), <vscale x 4 x i32> %x)
+ ret <vscale x 4 x i32> %out
+}
+
+declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
>From 402f7ae5d87f02ecc4d836e38e1a80eb2aa4b6bc Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Wed, 17 Jun 2026 09:07:30 +0100
Subject: [PATCH 2/2] [AArch64][SVE] add missing MLA commute instcombine
---
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 11 -----------
.../Target/AArch64/AArch64TargetTransformInfo.cpp | 10 ++++++----
llvm/test/CodeGen/AArch64/sve-mul-imm-add-adr.ll | 9 ++++++---
.../InstCombine/AArch64/sve-intrinsic-mla-one.ll | 14 +++++++-------
.../AArch64/sve-intrinsic-mul-imm-add-adr.ll | 6 +++---
5 files changed, 22 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 64dab3296dddd..9011752c88e33 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1977,17 +1977,6 @@ let Predicates = [HasSVE] in {
def : Pat<(Ty (AArch64mla_p (PredTy (SVEAnyPredicate)), Ty:$Acc, Ty:$Op,
(Ty (splat_vector (ScalarTy 8))))),
(Adr3 $Acc, $Op)>;
-
- // MLA commuted. These can be removed if the commuted forms are canonicalized.
- def : Pat<(Ty (AArch64mla_p (PredTy (SVEAnyPredicate)), Ty:$Acc,
- (Ty (splat_vector (ScalarTy 2))), Ty:$Op)),
- (Adr1 $Acc, $Op)>;
- def : Pat<(Ty (AArch64mla_p (PredTy (SVEAnyPredicate)), Ty:$Acc,
- (Ty (splat_vector (ScalarTy 4))), Ty:$Op)),
- (Adr2 $Acc, $Op)>;
- def : Pat<(Ty (AArch64mla_p (PredTy (SVEAnyPredicate)), Ty:$Acc,
- (Ty (splat_vector (ScalarTy 8))), Ty:$Op)),
- (Adr3 $Acc, $Op)>;
}
let AddedComplexity = 10 in {
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index f8d2006cbd7de..6bd1d27094071 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2589,17 +2589,19 @@ instCombineSVEVectorMlaU(InstCombiner &IC, IntrinsicInst &II) {
Value *MulOp0 = II.getArgOperand(2);
Value *MulOp1 = II.getArgOperand(3);
+ if (isa<Constant>(MulOp0) && !isa<Constant>(MulOp1)) {
+ II.setArgOperand(2, MulOp1);
+ II.setArgOperand(3, MulOp0);
+ return &II;
+ }
+
// For mla_u, inactive lanes are undefined, so it is valid to drop the
// predicate when replacing mla_u(acc, x, 1) with add(acc, x) or
// mla_u(acc, x, -1) with sub(acc, x).
if (match(MulOp0, m_One()))
return IC.replaceInstUsesWith(II, IC.Builder.CreateAdd(Acc, MulOp1));
- if (match(MulOp1, m_One()))
- return IC.replaceInstUsesWith(II, IC.Builder.CreateAdd(Acc, MulOp0));
if (match(MulOp0, m_AllOnes()))
return IC.replaceInstUsesWith(II, IC.Builder.CreateSub(Acc, MulOp1));
- if (match(MulOp1, m_AllOnes()))
- return IC.replaceInstUsesWith(II, IC.Builder.CreateSub(Acc, MulOp0));
return std::nullopt;
}
diff --git a/llvm/test/CodeGen/AArch64/sve-mul-imm-add-adr.ll b/llvm/test/CodeGen/AArch64/sve-mul-imm-add-adr.ll
index 91423fc1d068d..9b3b855ab66de 100644
--- a/llvm/test/CodeGen/AArch64/sve-mul-imm-add-adr.ll
+++ b/llvm/test/CodeGen/AArch64/sve-mul-imm-add-adr.ll
@@ -288,7 +288,8 @@ define <vscale x 4 x i32> @svmla_u_i32_by_8(<vscale x 4 x i1> %pg, <vscale x 4 x
define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: svmla_u_i32_by_2_commuted:
; CHECK: // %bb.0:
-; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
+; CHECK-NEXT: mov z2.s, #2 // =0x2
+; CHECK-NEXT: mla z0.s, p0/m, z2.s, z1.s
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 2), <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %out
@@ -297,7 +298,8 @@ define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vsc
define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: svmla_u_i32_by_4_commuted:
; CHECK: // %bb.0:
-; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
+; CHECK-NEXT: mov z2.s, #4 // =0x4
+; CHECK-NEXT: mla z0.s, p0/m, z2.s, z1.s
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 4), <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %out
@@ -306,7 +308,8 @@ define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(<vscale x 4 x i1> %pg, <vsc
define <vscale x 4 x i32> @svmla_u_i32_by_8_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: svmla_u_i32_by_8_commuted:
; CHECK: // %bb.0:
-; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
+; CHECK-NEXT: mov z2.s, #8 // =0x8
+; CHECK-NEXT: mla z0.s, p0/m, z2.s, z1.s
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 8), <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %out
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mla-one.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mla-one.ll
index a839d1ddc1d52..f7b7d8ac8444f 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mla-one.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mla-one.ll
@@ -5,7 +5,7 @@ target triple = "aarch64-unknown-linux-gnu"
define <vscale x 4 x i32> @mla_one_rhs_splat_true(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_one_rhs_splat_true(
-; CHECK-NEXT: [[R:%.*]] = add <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 1))
@@ -14,7 +14,7 @@ define <vscale x 4 x i32> @mla_one_rhs_splat_true(<vscale x 4 x i32> %acc, <vsca
define <vscale x 4 x i32> @mla_one_lhs_splat_true(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_one_lhs_splat_true(
-; CHECK-NEXT: [[R:%.*]] = add <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %acc, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> %x)
@@ -23,7 +23,7 @@ define <vscale x 4 x i32> @mla_one_lhs_splat_true(<vscale x 4 x i32> %acc, <vsca
define <vscale x 4 x i32> @mla_allones_rhs_splat_true(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_allones_rhs_splat_true(
-; CHECK-NEXT: [[R:%.*]] = sub <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 -1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 -1))
@@ -32,7 +32,7 @@ define <vscale x 4 x i32> @mla_allones_rhs_splat_true(<vscale x 4 x i32> %acc, <
define <vscale x 4 x i32> @mla_allones_lhs_splat_true(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_allones_lhs_splat_true(
-; CHECK-NEXT: [[R:%.*]] = sub <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 -1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %acc, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> %x)
@@ -41,7 +41,7 @@ define <vscale x 4 x i32> @mla_allones_lhs_splat_true(<vscale x 4 x i32> %acc, <
define <vscale x 4 x i32> @mla_one_rhs_ptrue_all(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_one_rhs_ptrue_all(
-; CHECK-NEXT: [[R:%.*]] = add <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
@@ -80,7 +80,7 @@ define <vscale x 4 x i32> @mla_allones_rhs_unknown_predicate(<vscale x 4 x i1> %
define <vscale x 4 x i32> @mla_u_one_rhs_unknown_predicate(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_u_one_rhs_unknown_predicate(
-; CHECK-NEXT: [[R:%.*]] = add <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 1))
@@ -89,7 +89,7 @@ define <vscale x 4 x i32> @mla_u_one_rhs_unknown_predicate(<vscale x 4 x i1> %pg
define <vscale x 4 x i32> @mla_u_allones_rhs_unknown_predicate(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x) {
; CHECK-LABEL: @mla_u_allones_rhs_unknown_predicate(
-; CHECK-NEXT: [[R:%.*]] = sub <vscale x 4 x i32> [[ACC:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> splat (i32 -1))
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
;
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %acc, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 -1))
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
index cc6641d35eaae..20a47f1c6e917 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-imm-add-adr.ll
@@ -122,7 +122,7 @@ define <vscale x 4 x i32> @svmul_u_i32_by_9_commuted(<vscale x 4 x i1> %pg, <vsc
define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 2))
; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
;
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 2), <vscale x 4 x i32> %x)
@@ -132,7 +132,7 @@ define <vscale x 4 x i32> @svmla_u_i32_by_2_commuted(<vscale x 4 x i1> %pg, <vsc
define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 4))
; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
;
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 4), <vscale x 4 x i32> %x)
@@ -142,7 +142,7 @@ define <vscale x 4 x i32> @svmla_u_i32_by_4_commuted(<vscale x 4 x i1> %pg, <vsc
define <vscale x 4 x i32> @svmla_u_i32_by_8_commuted(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x) {
; CHECK-LABEL: define <vscale x 4 x i32> @svmla_u_i32_by_8_commuted(
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 8), <vscale x 4 x i32> [[X]])
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[X]], <vscale x 4 x i32> splat (i32 8))
; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
;
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 8), <vscale x 4 x i32> %x)
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