[llvm] [X86] madd.ll - add additional tests for matchPMADDWD folds that fail with irregular source types (PR #205514)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 02:35:53 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/205514
Ensure #205391 doesn't crash with non-pow2/illegal types
>From 3cf969aa843b7961f56a31b406b0c7aa3e7aeb89 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 24 Jun 2026 10:34:46 +0100
Subject: [PATCH] [X86] madd.ll - add additional tests for matchPMADDWD folds
that fail with irregular source types
Ensure #205391 doesn't crash with non-pow2/illegal types
---
llvm/test/CodeGen/X86/madd.ll | 235 ++++++++++++++++++++++++++++++++++
1 file changed, 235 insertions(+)
diff --git a/llvm/test/CodeGen/X86/madd.ll b/llvm/test/CodeGen/X86/madd.ll
index 056712cc5a66c..63b390f4b9bdf 100644
--- a/llvm/test/CodeGen/X86/madd.ll
+++ b/llvm/test/CodeGen/X86/madd.ll
@@ -3739,3 +3739,238 @@ define <16 x i32> @extract_concat_pmaddwd(<32 x i16> %a, <32 x i16> %b) {
%ret = add <16 x i32> %odd, %even
ret <16 x i32> %ret
}
+
+define <5 x i32> @oddvector_mul(<16 x i16> %A, <16 x i16> %B) {
+; SSE2-LABEL: oddvector_mul:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq %rdi, %rax
+; SSE2-NEXT: movdqa %xmm1, %xmm4
+; SSE2-NEXT: pmulhw %xmm3, %xmm4
+; SSE2-NEXT: pmullw %xmm3, %xmm1
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
+; SSE2-NEXT: movdqa %xmm0, %xmm3
+; SSE2-NEXT: pmulhw %xmm2, %xmm3
+; SSE2-NEXT: pmullw %xmm2, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm3[4],xmm2[5],xmm3[5],xmm2[6],xmm3[6],xmm2[7],xmm3[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-NEXT: movdqa %xmm0, %xmm3
+; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2],xmm2[0,2]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
+; SSE2-NEXT: paddd %xmm3, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
+; SSE2-NEXT: movd %xmm2, %ecx
+; SSE2-NEXT: movdqa %xmm0, (%rdi)
+; SSE2-NEXT: movd %xmm1, %edx
+; SSE2-NEXT: addl %ecx, %edx
+; SSE2-NEXT: movl %edx, 16(%rdi)
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: oddvector_mul:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: pxor %xmm4, %xmm4
+; SSE42-NEXT: pmovzxwd {{.*#+}} xmm5 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
+; SSE42-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; SSE42-NEXT: pmovzxwd {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; SSE42-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
+; SSE42-NEXT: pmaddwd %xmm2, %xmm0
+; SSE42-NEXT: pmaddwd %xmm5, %xmm4
+; SSE42-NEXT: phaddd %xmm0, %xmm4
+; SSE42-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
+; SSE42-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; SSE42-NEXT: pmaddwd %xmm0, %xmm1
+; SSE42-NEXT: movd %xmm1, %ecx
+; SSE42-NEXT: movdqa %xmm4, (%rdi)
+; SSE42-NEXT: pextrd $1, %xmm1, %edx
+; SSE42-NEXT: addl %ecx, %edx
+; SSE42-NEXT: movl %edx, 16(%rdi)
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: oddvector_mul:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpmovsxwd %xmm2, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; AVX1-NEXT: vpmaddwd %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vphaddd %xmm0, %xmm4, %xmm1
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
+; AVX1-NEXT: vpmaddwd %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vphaddd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[3],ymm1[3]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: oddvector_mul:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmovsxwd %xmm0, %ymm2
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
+; AVX2-NEXT: vpmovsxwd %xmm1, %ymm3
+; AVX2-NEXT: vpmulld %ymm3, %ymm2, %ymm2
+; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
+; AVX2-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: vphaddd %ymm0, %ymm2, %ymm0
+; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: oddvector_mul:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxwd %ymm0, %zmm0
+; AVX512-NEXT: vpmovsxwd %ymm1, %zmm1
+; AVX512-NEXT: vpmulld %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; AVX512-NEXT: vphaddd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
+; AVX512-NEXT: retq
+ %a = sext <16 x i16> %A to <16 x i32>
+ %b = sext <16 x i16> %B to <16 x i32>
+ %m = mul nsw <16 x i32> %a, %b
+ %odd = shufflevector <16 x i32> %m, <16 x i32> undef, <5 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8>
+ %even = shufflevector <16 x i32> %m, <16 x i32> undef, <5 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9>
+ %ret = add <5 x i32> %odd, %even
+ ret <5 x i32> %ret
+}
+
+define <4 x i32> @oddvector_sext(<13 x i16> %A) {
+; SSE2-LABEL: oddvector_sext:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm0, %xmm0
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: pinsrw $1, %r8d, %xmm1
+; SSE2-NEXT: pinsrw $3, %r9d, %xmm1
+; SSE2-NEXT: pinsrw $5, {{[0-9]+}}(%rsp), %xmm1
+; SSE2-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm1
+; SSE2-NEXT: psrad $16, %xmm1
+; SSE2-NEXT: pinsrw $1, %edi, %xmm0
+; SSE2-NEXT: pinsrw $3, %esi, %xmm0
+; SSE2-NEXT: pinsrw $5, %edx, %xmm0
+; SSE2-NEXT: pinsrw $7, %ecx, %xmm0
+; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; SSE2-NEXT: paddd %xmm2, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: oddvector_sext:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movd %edi, %xmm0
+; SSE42-NEXT: pinsrw $1, %esi, %xmm0
+; SSE42-NEXT: pinsrw $2, %edx, %xmm0
+; SSE42-NEXT: pinsrw $3, %ecx, %xmm0
+; SSE42-NEXT: movd %r8d, %xmm1
+; SSE42-NEXT: pinsrw $1, %r9d, %xmm1
+; SSE42-NEXT: pinsrw $2, {{[0-9]+}}(%rsp), %xmm1
+; SSE42-NEXT: pinsrw $3, {{[0-9]+}}(%rsp), %xmm1
+; SSE42-NEXT: pmovsxwd %xmm1, %xmm1
+; SSE42-NEXT: pmovsxwd %xmm0, %xmm0
+; SSE42-NEXT: phaddd %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: oddvector_sext:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,1,1,1,1,1,1,1]
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: oddvector_sext:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,1,1,1,1,1,1,1]
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: oddvector_sext:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxwd %ymm0, %zmm0
+; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512-NEXT: vphaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: retq
+ %a = sext <13 x i16> %A to <13 x i32>
+ %odd = shufflevector <13 x i32> %a, <13 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %even = shufflevector <13 x i32> %a, <13 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %ret = add <4 x i32> %odd, %even
+ ret <4 x i32> %ret
+}
+
+define <3 x i32> @oddvector_shl(<12 x i16> %A) {
+; SSE2-LABEL: oddvector_shl:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: pxor %xmm0, %xmm0
+; SSE2-NEXT: pinsrw $1, %edi, %xmm0
+; SSE2-NEXT: pinsrw $3, %esi, %xmm0
+; SSE2-NEXT: pinsrw $5, %edx, %xmm0
+; SSE2-NEXT: pinsrw $7, %ecx, %xmm0
+; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: pinsrw $1, %r8d, %xmm1
+; SSE2-NEXT: pinsrw $3, %r9d, %xmm1
+; SSE2-NEXT: psrad $16, %xmm1
+; SSE2-NEXT: pslld $7, %xmm1
+; SSE2-NEXT: pslld $7, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,3]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; SSE2-NEXT: paddd %xmm2, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: oddvector_shl:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movd %edi, %xmm0
+; SSE42-NEXT: pinsrw $1, %esi, %xmm0
+; SSE42-NEXT: pinsrw $2, %edx, %xmm0
+; SSE42-NEXT: pinsrw $3, %ecx, %xmm0
+; SSE42-NEXT: pmovsxwd %xmm0, %xmm0
+; SSE42-NEXT: movd %r8d, %xmm1
+; SSE42-NEXT: pinsrw $1, %r9d, %xmm1
+; SSE42-NEXT: pmovsxwd %xmm1, %xmm1
+; SSE42-NEXT: pslld $7, %xmm1
+; SSE42-NEXT: pslld $7, %xmm0
+; SSE42-NEXT: phaddd %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX1-LABEL: oddvector_shl:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX1-NEXT: vpmovsxwd %xmm1, %xmm1
+; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
+; AVX1-NEXT: vpslld $7, %xmm0, %xmm0
+; AVX1-NEXT: vpslld $7, %xmm1, %xmm1
+; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: oddvector_shl:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
+; AVX2-NEXT: vpslld $7, %ymm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vphaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: oddvector_shl:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm1 = [1,3,5,0]
+; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0
+; AVX512-NEXT: vpslld $7, %ymm0, %ymm0
+; AVX512-NEXT: vpermd %ymm0, %ymm1, %ymm1
+; AVX512-NEXT: vpmovqd %zmm0, %ymm0
+; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: retq
+ %a = sext <12 x i16> %A to <12 x i32>
+ %shl = shl <12 x i32> %a, splat (i32 7)
+ %odd = shufflevector <12 x i32> %shl, <12 x i32> undef, <3 x i32> <i32 0, i32 2, i32 4>
+ %even = shufflevector <12 x i32> %shl, <12 x i32> undef, <3 x i32> <i32 1, i32 3, i32 5>
+ %ret = add <3 x i32> %odd, %even
+ ret <3 x i32> %ret
+}
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