[llvm] [ARM] Replace Neon concat patterns with insert_subregs. (PR #205505)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 24 01:57:22 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
This replaces the REG_SEQUENCE we use for concat_vector with INSERT_SUBREG, which whilst not perfect can produce slightly better code overall, and helps us avoid REG_SEQUENCE instructions.
---
Patch is 627.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/205505.diff
27 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMInstrNEON.td (+7-7)
- (modified) llvm/test/CodeGen/ARM/aes-erratum-fix.ll (+196-208)
- (modified) llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll (+4-3)
- (modified) llvm/test/CodeGen/ARM/bf16-shuffle.ll (+31-31)
- (modified) llvm/test/CodeGen/ARM/big-endian-vector-callee.ll (+24-24)
- (modified) llvm/test/CodeGen/ARM/div-by-constant-to-mul-crash.ll (+12-12)
- (modified) llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll (+16-16)
- (modified) llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll (+68-68)
- (modified) llvm/test/CodeGen/ARM/fpclamptosat_vec.ll (+1130-1131)
- (modified) llvm/test/CodeGen/ARM/legalize-bitcast.ll (+6-5)
- (modified) llvm/test/CodeGen/ARM/llvm.frexp.ll (+10-10)
- (modified) llvm/test/CodeGen/ARM/neon-vmovn.ll (+116-112)
- (modified) llvm/test/CodeGen/ARM/neon_vabd.ll (+12-12)
- (modified) llvm/test/CodeGen/ARM/pr196779.ll (+13-13)
- (modified) llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll (+32-36)
- (modified) llvm/test/CodeGen/ARM/vcombine.ll (+81-42)
- (modified) llvm/test/CodeGen/ARM/vector-llrint.ll (+849-868)
- (modified) llvm/test/CodeGen/ARM/vector-lrint.ll (+1649-1657)
- (modified) llvm/test/CodeGen/ARM/vext.ll (+4-4)
- (modified) llvm/test/CodeGen/ARM/vldlane.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/vrint.ll (+499-499)
- (modified) llvm/test/CodeGen/ARM/vselect_imax.ll (+205-202)
- (modified) llvm/test/CodeGen/ARM/vtrn.ll (+15-15)
- (modified) llvm/test/CodeGen/ARM/vuzp.ll (+73-73)
- (modified) llvm/test/CodeGen/ARM/vzip.ll (+9-9)
- (modified) llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll (+8-9)
- (modified) llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll (+4-4)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index a4e90204705b9..ea322e38420ff 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -8130,19 +8130,19 @@ let Predicates = [HasNEON,IsBE] in {
let Predicates = [HasNEON] in {
def : Pat<(v2i64 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v4i32 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v8i16 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v16i8 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v4f32 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v8f16 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
def : Pat<(v8bf16 (concat_vectors DPR:$Dn, DPR:$Dm)),
- (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
+ (INSERT_SUBREG (INSERT_SUBREG (IMPLICIT_DEF), DPR:$Dn, dsub_0), DPR:$Dm, dsub_1)>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
index 82f5bfd02a56e..60658444ea6d0 100644
--- a/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
+++ b/llvm/test/CodeGen/ARM/aes-erratum-fix.ll
@@ -1387,20 +1387,20 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-FIX-NOSCHED-NEXT: .LBB36_3:
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #8
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[0]}, [r2:32]
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[0]}, [r3:32]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[0]}, [r3:32]
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #4
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[1]}, [r3:32]
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #12
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[1]}, [r3:32]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[1]}, [r3:32]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d18[0]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d16[0]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[2]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[1]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[1]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d16[1]
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
@@ -1444,91 +1444,85 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX: @ %bb.0:
; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-CORTEX-FIX-NEXT: .pad #24
-; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #24
+; CHECK-CORTEX-FIX-NEXT: .pad #16
+; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #16
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB36_3
; CHECK-CORTEX-FIX-NEXT: @ %bb.1:
; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2]
+; CHECK-CORTEX-FIX-NEXT: ldrh r11, [r1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d17[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d17[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #20] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d17[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #4] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[1]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: ldrh r3, [r1]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #16] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: mov r3, r6
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: bne .LBB36_4
; CHECK-CORTEX-FIX-NEXT: .LBB36_2:
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r0, d0[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d0[0]
; CHECK-CORTEX-FIX-NEXT: b .LBB36_5
; CHECK-CORTEX-FIX-NEXT: .LBB36_3:
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[0]}, [r2:32]
; CHECK-CORTEX-FIX-NEXT: add r3, r2, #8
; CHECK-CORTEX-FIX-NEXT: add r7, r2, #4
-; CHECK-CORTEX-FIX-NEXT: vld1.32 {d17[0]}, [r3:32]
+; CHECK-CORTEX-FIX-NEXT: vld1.32 {d18[0]}, [r3:32]
; CHECK-CORTEX-FIX-NEXT: add r3, r2, #12
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[1]}, [r7:32]
-; CHECK-CORTEX-FIX-NEXT: vld1.32 {d17[1]}, [r3:32]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[1]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d17[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #16] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vld1.32 {d18[1]}, [r3:32]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
-; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #12] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d17[2]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #20] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d16[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d18[2]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d18[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d18[3]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[2]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r7, [sp, #4] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #12] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[0]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d18[1]
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB36_2
; CHECK-CORTEX-FIX-NEXT: .LBB36_4:
-; CHECK-CORTEX-FIX-NEXT: ldrh r0, [r1]
+; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r1]
; CHECK-CORTEX-FIX-NEXT: .LBB36_5:
-; CHECK-CORTEX-FIX-NEXT: str r0, [sp] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r9, r7, r4, lsl #16
-; CHECK-CORTEX-FIX-NEXT: ldr r4, [sp, #20] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d0[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d0[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d0[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r12, d0[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d1[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d1[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d1[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r1, d1[1]
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d1[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d1[3]
-; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r0, r1, lsl #16
-; CHECK-CORTEX-FIX-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r0, lr, r8, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d1[3]
+; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r8, r3, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r11, r0, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r4, r5, lsl #16
; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r12, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r11, r5, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r3, r1, lsl #16
-; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r4, r3, r4, lsl #16
-; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r4
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r1
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r7
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r9
-; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r10, lsl #16
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r3
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r5
+; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r9, r1, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r0
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r3
+; CHECK-CORTEX-FIX-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r7, lr, r7, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r5
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r10, lsl #16
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r6
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r0
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r1
+; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r6, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r3
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r0
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r7
; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8
; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9
; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2]
-; CHECK-CORTEX-FIX-NEXT: add sp, sp, #24
+; CHECK-CORTEX-FIX-NEXT: add sp, sp, #16
; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
br i1 %0, label %5, label %12
@@ -1598,18 +1592,18 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-FIX-NOSCHED-NEXT: .LBB37_2:
; CHECK-FIX-NOSCHED-NEXT: add r2, r1, #8
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[0]}, [r1:32]
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[0]}, [r2:32]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[0]}, [r2:32]
; CHECK-FIX-NOSCHED-NEXT: add r2, r1, #4
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[1]}, [r2:32]
; CHECK-FIX-NOSCHED-NEXT: add r2, r1, #12
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[1]}, [r2:32]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[1]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[1]}, [r2:32]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d18[1]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d18[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 lr, d18[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r8, d16[1]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d18[0]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp, #4] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r2, d16[3]
; CHECK-FIX-NOSCHED-NEXT: str r2, [sp] @ 4-byte Spill
@@ -1665,8 +1659,8 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-CORTEX-FIX: @ %bb.0:
; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-CORTEX-FIX-NEXT: .pad #12
-; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #12
+; CHECK-CORTEX-FIX-NEXT: .pad #8
+; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #8
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB37_3
; CHECK-CORTEX-FIX-NEXT: @ %bb.1:
@@ -1674,82 +1668,82 @@ define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <1
; CHECK-CORTEX-FIX-NEXT: vmov.f32 s2, s0
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d16[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d16[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d17[3]
-; CHECK-CORTEX-FIX-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d17[0]
-; CHECK-CORTEX-FIX-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d17[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d16[3]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d17[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d17[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d17[3]
; CHECK-CORTEX-FIX-NEXT: str r2, [sp] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d17[2]
+; CHECK-CORTEX-FIX-NEXT: str r2, [sp, #4] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: bne .LBB37_4
; CHECK-CORTEX-FIX-NEXT: .LBB37_2:
+; CHECK-CORTEX-FIX-NEXT: mov r0, lr
; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d2[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d2[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d2[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d2[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d2[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d3[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d3[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d3[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d3[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d3[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r12, d3[3]
; CHECK-CORTEX-FIX-NEXT: vmov s0, lr
+; CHECK-CORTEX-FIX-NEXT: mov lr, r0
; CHECK-CORTEX-FIX-NEXT: b .LBB37_5
; CHECK-CORTEX-FIX-NEXT: .LBB37_3:
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[0]}, [r1:32]
; CHECK-CORTEX-FIX-NEXT: add r2, r1, #8
; CHECK-CORTEX-FIX-NEXT: add r3, r1, #4
-; CHECK-CORTEX-FIX-NEXT: vld1.32 {d17[0]}, [r2:32]
+; CHECK-CORTEX-FIX-NEXT: vld1.32 {d18[0]}, [r2:32]
; CHECK-CORTEX-FIX-NEXT: add r2, r1, #12
; CHECK-CORTEX-FIX-NEXT: vld1.32 {d16[1]}, [r3:32]
-; CHECK-CORTEX-FIX-NEXT: vld1.32 {d17[1]}, [r2:32]
+; CHECK-CORTEX-FIX-NEXT: vld1.32 {d18[1]}, [r2:32]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d16[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d16[0]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r7, d16[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d16[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d17[2]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d17[3]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 lr, d16[3]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r11, d18[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r6, d18[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r10, d18[3]
+; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d18[2]
; CHECK-CORTEX-FIX-NEXT: vmov s2, r2
; CHECK-CORTEX-FIX-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d17[1]
-; CHECK-CORTEX-FIX-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-CORTEX-FIX-NEXT: cmp r0, #0
; CHECK-CORTEX-FIX-NEXT: beq .LBB37_2
; CHECK-CORTEX-FIX-NEXT: .LBB37_4:
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d2[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d2[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r3, d2[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r4, d2[3]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d3[0]
-; CHECK-CORTEX-FIX-NEXT: vmov.u16 r2, d3[1]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r8, d3[0]
+; CHECK-CORTEX-FIX-NEXT: vmov.u16 r9, d3[1]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r5, d3[2]
; CHECK-CORTEX-FIX-NEXT: vmov.u16 r12, d3[3]
; CHECK-CORTEX-FIX-NEXT: .LBB37_5:
-; CHECK-CORTEX-FIX-NEXT: pkhbt lr, r11, r6, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r7, r10, lsl #16
-; CHECK-CORTEX-FIX-NEXT: ldm sp, {r6, r7} @ 8-byte Folded Reload
; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r4, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov r4, s2
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r5, r12, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r2, r9, r2, lsl #16
-; CHECK-CORTEX-FIX-NEXT: pkhbt r4, r7, r6, lsl #16
-; CHECK-CORTEX-FIX-NEXT: vmov r7, s2
-; CHECK-CORTEX-FIX-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
-; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r7, r6, lsl #16
-; CHECK-CORTEX-FIX-NEXT: vmov r6, s0
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r7
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r4
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r0
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], lr
-; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r8, lsl #16
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r6
-; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r2
+; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r11, r6, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r4, r4, r0, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov r0, s0
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r4
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r6
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r2, lsl #16
+; CHECK-CORTEX-FIX-NEXT: pkhbt r2, r7, lr, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r0
+; CHECK-CORTEX-FIX-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], r2
+; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r0, r10, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r0
; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r3
+; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r8, r9, lsl #16
+; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r3
; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r5
; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8
; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9
; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1]
-; CHECK-CORTEX-FIX-NEXT: add sp, sp, #12
+; CHECK-CORTEX-FIX-NEXT: add sp, sp, #8
; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
br i1 %0, label %5, label %11
@@ -3541,20 +3535,20 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-FIX-NOSCHED-NEXT: .LBB82_3:
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #8
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[0]}, [r2:32]
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[0]}, [r3:32]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[0]}, [r3:32]
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #4
; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d16[1]}, [r3:32]
; CHECK-FIX-NOSCHED-NEXT: add r3, r2, #12
-; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d17[1]}, [r3:32]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[3]
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d17[0]
+; CHECK-FIX-NOSCHED-NEXT: vld1.32 {d18[1]}, [r3:32]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[3]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r9, d18[0]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r10, d16[3]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r11, d16[2]
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r7, d16[0]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[2]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[2]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d17[1]
+; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d18[1]
; CHECK-FIX-NOSCHED-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-FIX-NOSCHED-NEXT: vmov.u16 r3, d16[1]
; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0
@@ -3598,91 +3592,85 @@ define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, ptr %1, <16
; CHECK-CORTEX-FIX: @ %bb.0:
; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-CORTEX-FIX-NEXT: .pad #24
-; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #24
+; CHECK-CORTEX-FIX-NEXT: .pad #16
+; CHECK-CORTEX-FIX-NEXT: sub sp, sp, #16
; CHECK-CORTEX-FIX-NEXT: cmp r0,...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205505
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