[llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)

Jessica Clarke via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 23 19:51:35 PDT 2026


================
@@ -1981,10 +1983,37 @@ def PseudoTLSDESCCall : Pseudo<(outs GPR:$rd),
                          (ins GPR:$rs1, simm12_lo:$imm12, tlsdesc_call_symbol:$src), [],
                          "jalr", "$rd, ${imm12}(${rs1}), $src">,
                          Sched<[WriteJalr, ReadJalr]> {
-  let Defs = [X10];
+  let Defs = [X5, X10];
   let Uses = [X10];
 }
 
+//===----------------------------------------------------------------------===//
+// TLSDESC V-extension clobber variants
+//===----------------------------------------------------------------------===//
+// When the V extension is enabled, the TLSDESC resolver additionally clobbers
+// all vector registers and vector CSRs (vl, vtype, vxrm, vxsat) per the psABI.
+
+defvar TLSDESCVClobbers = !listconcat(
+    !foreach(i, !range(32), !cast<Register>("V"#i)),
+    [VTYPE, VL, VXSAT, VXRM]);
+
+let Predicates = [HasVInstructions] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 32, isCodeGenOnly = 0 in
+def PseudoLA_TLSDESC_V : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+                               "la.tlsdesc", "$dst, $src"> {
+  let Defs = !listconcat([X5, X10], TLSDESCVClobbers);
+}
+
+let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0,
+    mayStore = 0, mayLoad = 0 in
+def PseudoTLSDESCCall_V : Pseudo<(outs GPR:$rd),
----------------
jrtc27 wrote:

That was PseudoLA_TLSDESC not PseudoTLSDESCCall? The latter is for `jalr t0, 0(tmpreg), %tlsdesc_call(label)` and definitely is real assembly that needs to be parsed.

https://github.com/llvm/llvm-project/pull/205027


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