[llvm] [AMDGPU] Reject src1 immediates with dpp when unsupported (PR #201494)
Frederick Vu via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 23 18:11:48 PDT 2026
https://github.com/FrederickVu updated https://github.com/llvm/llvm-project/pull/201494
>From b6896c4bce1139c0b113d9c0163753c0434886d9 Mon Sep 17 00:00:00 2001
From: Frederick Vu <100011202+FrederickVu at users.noreply.github.com>
Date: Thu, 4 Jun 2026 02:14:26 +0000
Subject: [PATCH 1/4] Reject immediates with dpp when illegal
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 ++++++++++
llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir | 6 ++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a544f1380e53d..970da3934ebc5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4931,6 +4931,12 @@ bool SIInstrInfo::isLiteralOperandLegal(const MCInstrDesc &InstDesc,
bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
int64_t ImmVal) const {
+ const unsigned Opc = InstDesc.getOpcode();
+ int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
+ if (Src1Idx != -1 && !ST.hasDPPSrc1SGPR() && isDPP(Opc) &&
+ OpNo == static_cast<unsigned>(Src1Idx))
+ return false;
+
const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
if (isInlineConstant(ImmVal, OpInfo.OperandType)) {
if (isMAI(InstDesc) && ST.hasMFMAInlineLiteralBug() &&
@@ -5543,6 +5549,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
ErrInfo = "DPP src1 cannot be SGPR on this subtarget";
return false;
}
+ if (Src1MO.isImm()) {
+ ErrInfo = "DPP src1 cannot be an immediate on this subtarget";
+ return false;
+ }
}
// Verify MIMG / VIMAGE / VSAMPLE
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
index ab44ea970025d..fd5a662815e21 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
@@ -8,7 +8,8 @@
# GCN: %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64_dpp %3, %0, %1, %5, 1, 1, 15, 15, 1, implicit $exec
# GCN: %8:vgpr_32 = V_CVT_PK_U8_F32_e64_dpp %3, 4, %0, 2, %2, 2, %1, 1, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec
-# GCN: %12:vgpr_32 = V_MED3_F32_e64_dpp %3, 0, %1, 0, 2, 0, %7, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
+# GFX_NO_SRC1_SGPR: %12:vgpr_32 = V_MED3_F32_e64 0, %11, 0, 2, 0, %7, 0, 0, implicit $mode, implicit $exec
+# GFX_SRC1_SGPR: %12:vgpr_32 = V_MED3_F32_e64_dpp %3, 0, %1, 0, 2, 0, %7, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
name: vop3
tracksRegLiveness: true
body: |
@@ -42,7 +43,8 @@ body: |
# GFX_SRC1_SGPR: %8:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %1, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
# GFX_NO_SRC1_SGPR: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec
# GFX_SRC1_SGPR: %10:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %3, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
-# GCN: %12:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, 42, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
+# GFX_NO_SRC1_SGPR: %12:vgpr_32 = V_MED3_F32_e64 0, %11, 0, 42, 0, %2, 0, 0, implicit $mode, implicit $exec
+# GFX_SRC1_SGPR: %12:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, 42, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %14:vgpr_32 = V_MED3_F32_e64 0, %13, 0, 4242, 0, %2, 0, 0, implicit $mode, implicit $exec
name: vop3_sgpr_src1
tracksRegLiveness: true
>From 10d9ffa10e3e6bc824ac8d77b63b350fa0dc9ac8 Mon Sep 17 00:00:00 2001
From: Frederick Vu <100011202+FrederickVu at users.noreply.github.com>
Date: Tue, 9 Jun 2026 17:43:17 +0000
Subject: [PATCH 2/4] Add test
---
.../MachineVerifier/AMDGPU/dpp-sgpr-src1.mir | 28 +++++++++++++++++--
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir b/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
index 5a9f3db3f0a04..3c1a7dbf9e83d 100644
--- a/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
@@ -1,9 +1,16 @@
-# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_NO_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: split-file %s %t
+
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %t/sgpr.mir --check-prefix=GFX_NO_SRC1_SGPR
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %t/imm.mir --check-prefix=GFX_NO_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
# GFX_SRC1_SGPR-NOT: *** Bad machine code: DPP src1 cannot be SGPR on this subtarget ***
+# GFX_SRC1_SGPR-NOT: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
+#--- sgpr.mir
---
name: dpp_sgpr_src1
tracksRegLiveness: true
@@ -18,3 +25,18 @@ body: |
; GFX_NO_SRC1_SGPR: V_ADD_CO_U32_e64_dpp
%2:vgpr_32, %3:sreg_32_xexec = V_ADD_CO_U32_e64_dpp %0:vgpr_32, %0:vgpr_32, %1:sreg_32, 0, 228, 12, 15, 0, implicit $exec
...
+
+#--- imm.mir
+---
+name: dpp_imm_src1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ %0:vgpr_32 = COPY $vgpr0
+
+ ; GFX_NO_SRC1_SGPR: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
+ ; GFX_NO_SRC1_SGPR: V_ADD_CO_U32_e64_dpp
+ %1:vgpr_32, %2:sreg_32_xexec = V_ADD_CO_U32_e64_dpp %0:vgpr_32, %0:vgpr_32, 42, 0, 228, 12, 15, 0, implicit $exec
+...
>From 4bb0580f625f91691af5a7b2778bbdc5a9e6fa26 Mon Sep 17 00:00:00 2001
From: Frederick Vu <100011202+FrederickVu at users.noreply.github.com>
Date: Wed, 10 Jun 2026 16:49:41 +0000
Subject: [PATCH 3/4] Make src1 imm test file
---
.../MachineVerifier/AMDGPU/dpp-imm-src1.mir | 19 +++++++++++++
.../MachineVerifier/AMDGPU/dpp-sgpr-src1.mir | 28 ++-----------------
2 files changed, 22 insertions(+), 25 deletions(-)
create mode 100644 llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir
diff --git a/llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir b/llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir
new file mode 100644
index 0000000000000..a15ca1c394044
--- /dev/null
+++ b/llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_NO_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+
+# GFX_SRC1_SGPR-NOT: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
+
+---
+name: dpp_imm_src1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ %0:vgpr_32 = COPY $vgpr0
+
+ ; GFX_NO_SRC1_SGPR: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
+ ; GFX_NO_SRC1_SGPR: V_ADD_CO_U32_e64_dpp
+ %1:vgpr_32, %2:sreg_32_xexec = V_ADD_CO_U32_e64_dpp %0:vgpr_32, %0:vgpr_32, 42, 0, 228, 12, 15, 0, implicit $exec
+...
diff --git a/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir b/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
index 3c1a7dbf9e83d..5a9f3db3f0a04 100644
--- a/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
@@ -1,16 +1,9 @@
-# RUN: split-file %s %t
-
-# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %t/sgpr.mir --check-prefix=GFX_NO_SRC1_SGPR
-# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %t/imm.mir --check-prefix=GFX_NO_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %t/sgpr.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %t/imm.mir 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_NO_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=GFX_SRC1_SGPR
# GFX_SRC1_SGPR-NOT: *** Bad machine code: DPP src1 cannot be SGPR on this subtarget ***
-# GFX_SRC1_SGPR-NOT: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
-#--- sgpr.mir
---
name: dpp_sgpr_src1
tracksRegLiveness: true
@@ -25,18 +18,3 @@ body: |
; GFX_NO_SRC1_SGPR: V_ADD_CO_U32_e64_dpp
%2:vgpr_32, %3:sreg_32_xexec = V_ADD_CO_U32_e64_dpp %0:vgpr_32, %0:vgpr_32, %1:sreg_32, 0, 228, 12, 15, 0, implicit $exec
...
-
-#--- imm.mir
----
-name: dpp_imm_src1
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr0
-
- %0:vgpr_32 = COPY $vgpr0
-
- ; GFX_NO_SRC1_SGPR: *** Bad machine code: DPP src1 cannot be an immediate on this subtarget ***
- ; GFX_NO_SRC1_SGPR: V_ADD_CO_U32_e64_dpp
- %1:vgpr_32, %2:sreg_32_xexec = V_ADD_CO_U32_e64_dpp %0:vgpr_32, %0:vgpr_32, 42, 0, 228, 12, 15, 0, implicit $exec
-...
>From c19e7a388f5e668c0f76691af1d53121903d6e84 Mon Sep 17 00:00:00 2001
From: Frederick Vu <100011202+FrederickVu at users.noreply.github.com>
Date: Wed, 24 Jun 2026 01:05:10 +0000
Subject: [PATCH 4/4] Swap conditions in if-statement
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 970da3934ebc5..53bfd287501cf 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4933,7 +4933,7 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
int64_t ImmVal) const {
const unsigned Opc = InstDesc.getOpcode();
int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
- if (Src1Idx != -1 && !ST.hasDPPSrc1SGPR() && isDPP(Opc) &&
+ if (Src1Idx != -1 && isDPP(Opc) && !ST.hasDPPSrc1SGPR() &&
OpNo == static_cast<unsigned>(Src1Idx))
return false;
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