[llvm] [ScheduleDAGFast] Fix crash due to incorrect live reg delay in fast scheduler (PR #200567)

[Ye Tian via llvm-commits]

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@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs -pre-RA-sched=fast -O3 %s -o - | FileCheck %s
+
+; Test that the fast scheduler correctly handles the case where a node being
+; scheduled is itself the live physical register definition (EFLAGS). Previously,
+; DelayForLiveRegsBottomUp would incorrectly delay such a node, leading to an
+; infinite loop of register copy insertion and a scheduling failure assertion.
+
+define i1 @Perl_pp_match(i32 %0) {
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TianYe717 wrote:

Fixed, thanks!

https://github.com/llvm/llvm-project/pull/200567