[llvm] [AArch64][TableGen] Define ZA, ZT0 and FPMR memory defvars (PR #154144)

[Paul Walker via llvm-commits]

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@@ -2997,18 +3005,21 @@ let TargetPrefix = "aarch64" in {
 
   // Spill + fill
   class SME_LDR_STR_ZA_Intrinsic
-    : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_anyptr_ty, llvm_i32_ty], [IntrInaccessibleMemOrArgMemOnly]>;
+    : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_anyptr_ty, llvm_i32_ty], [IntrRead<[ArgMem, ZA]>, IntrWrite<[ArgMem, ZA]>]>;
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paulwalker-arm wrote:

As above.

https://github.com/llvm/llvm-project/pull/154144