[llvm] a06ac5d - [AArch64] Add flag to conditionally write FPMR (#203911)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 23 06:13:08 PDT 2026
Author: CarolineConcatto
Date: 2026-06-23T14:13:03+01:00
New Revision: a06ac5d5d555bf01b9ef4ad233a9d3d962b25c43
URL: https://github.com/llvm/llvm-project/commit/a06ac5d5d555bf01b9ef4ad233a9d3d962b25c43
DIFF: https://github.com/llvm/llvm-project/commit/a06ac5d5d555bf01b9ef4ad233a9d3d962b25c43.diff
LOG: [AArch64] Add flag to conditionally write FPMR (#203911)
Add a AArch64 codegen flag to make llvm.aarch64.set.fpmr avoid writing
FPMR when it already contains the requested value.
By default, llvm.aarch64.set.fpmr continues to lower directly to an MSR
FPMR instruction. With -aarch64-conditional-fpmr-write, the backend
lowers the intrinsic to an MRS/MSR conditional branch sequence.
This is based on the initial implementation from:
https://github.com/llvm/llvm-project/pull/114248
However this PR keeps the conditional FPMR write sequence behind a
codegen flag. One reason to change the codegen lowering is because GCC
emits the conditional branch sequence unconditionally. LLVM preserves
the existing direct MSR lowering by default.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-fpenv.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 12a8c829dc380..e56a9be69dd7c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -163,6 +163,15 @@ static cl::opt<bool> UseFEATCPACodegen(
"SelectionDAG for FEAT_CPA"),
cl::init(false));
+// FPMR writes might be a synchronization barrier and thus carry a significant
+// cost. Give users the option to skip writes when the requested value is
+// already set.
+static cl::opt<bool> UseConditionalFPMRWrite(
+ "aarch64-use-conditional-fpmr-write", cl::Hidden,
+ cl::desc("Only write FPMR when the requested value
diff ers from the "
+ "current value"),
+ cl::init(false));
+
/// Value type used for condition codes.
constexpr MVT CondCodeVT = MVT::i32;
@@ -3196,6 +3205,52 @@ MachineBasicBlock *AArch64TargetLowering::EmitLoweredCatchRet(
return BB;
}
+MachineBasicBlock *
+AArch64TargetLowering::EmitLoweredSetFpmr(MachineInstr &MI,
+ MachineBasicBlock *MBB) const {
+ MachineFunction *MF = MBB->getParent();
+ const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+ DebugLoc DL = MI.getDebugLoc();
+
+ if (!UseConditionalFPMRWrite) {
+ BuildMI(*MBB, MI, DL, TII->get(AArch64::MSR))
+ .addImm(0xda22)
+ .add(MI.getOperand(0))
+ .addDef(AArch64::FPMR, RegState::Implicit);
+ MI.eraseFromParent();
+ return MBB;
+ }
+
+ Register NewFpmrVal = MI.getOperand(0).getReg();
+ const BasicBlock *LLVM_BB = MBB->getBasicBlock();
+ MachineBasicBlock *MsrBB = MF->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *EndBB = MBB->splitAt(MI);
+ MF->insert(++MBB->getIterator(), MsrBB);
+
+ Register CurrentFpmrVal =
+ MF->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
+ BuildMI(*MBB, MI, DL, TII->get(AArch64::MRS), CurrentFpmrVal)
+ .addImm(0xda22)
+ .addUse(AArch64::FPMR, RegState::Implicit);
+ BuildMI(*MBB, MI, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
+ .addReg(CurrentFpmrVal, RegState::Kill)
+ .addReg(NewFpmrVal)
+ .addImm(0);
+ BuildMI(*MBB, MI, DL, TII->get(AArch64::Bcc))
+ .addImm(AArch64CC::EQ)
+ .addMBB(EndBB);
+ BuildMI(*MsrBB, MsrBB->begin(), DL, TII->get(AArch64::MSR))
+ .addImm(0xda22)
+ .addReg(NewFpmrVal, getKillRegState(MI.getOperand(0).isDead()))
+ .addDef(AArch64::FPMR, RegState::Implicit);
+
+ MBB->addSuccessor(MsrBB);
+ MsrBB->addSuccessor(EndBB);
+
+ MI.eraseFromParent();
+ return EndBB;
+}
+
MachineBasicBlock *
AArch64TargetLowering::EmitDynamicProbedAlloc(MachineInstr &MI,
MachineBasicBlock *MBB) const {
@@ -3568,6 +3623,8 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
return EmitZTInstr(MI, BB, AArch64::ZERO_T, /*Op0IsDef=*/true);
case AArch64::MOVT_TIZ_PSEUDO:
return EmitZTInstr(MI, BB, AArch64::MOVT_TIZ, /*Op0IsDef=*/true);
+ case AArch64::MSR_FPMR:
+ return EmitLoweredSetFpmr(MI, BB);
case AArch64::PAC:
fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4),
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 704eed7877bdc..4c3994e4e3d1d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -175,6 +175,9 @@ class AArch64TargetLowering : public TargetLowering {
MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
MachineBasicBlock *BB) const;
+ MachineBasicBlock *EmitLoweredSetFpmr(MachineInstr &MI,
+ MachineBasicBlock *MBB) const;
+
MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI,
MachineBasicBlock *MBB) const;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 96c77c2f75196..fc7aea5a4d5f5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2529,10 +2529,9 @@ def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
Sched<[WriteSys]>;
-let Defs = [FPMR] in
+let Uses = [FPMR], Defs = [FPMR, NZCV], usesCustomInserter = 1 in
def MSR_FPMR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpmr i64:$val)]>,
- PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,
Sched<[WriteSys]>;
// Generic system instructions
diff --git a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll b/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
index 412f89ae67439..c67cbd8cdb406 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+neon,+fp8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DIRECT
+; RUN: llc -mtriple=aarch64 -mattr=+neon,+fp8 -verify-machineinstrs -aarch64-use-conditional-fpmr-write < %s | FileCheck %s --check-prefixes=CHECK,COND
define i64 @get_fpcr() #0 {
; CHECK-LABEL: get_fpcr:
@@ -38,12 +39,51 @@ define void @set_fpsr(i64 %sr) {
}
define void @set_fpmr(i64 %sr) {
-; CHECK-LABEL: set_fpmr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: msr FPMR, x0
-; CHECK-NEXT: ret
- call void @llvm.aarch64.set.fpmr(i64 %sr)
- ret void
+; DIRECT-LABEL: set_fpmr:
+; DIRECT: // %bb.0:
+; DIRECT-NEXT: msr FPMR, x0
+; DIRECT-NEXT: ret
+; COND-LABEL: set_fpmr:
+; COND: // %bb.0:
+; COND-NEXT: mrs x8, FPMR
+; COND-NEXT: cmp x8, x0
+; COND-NEXT: b.eq .LBB4_2
+; COND-NEXT: // %bb.1:
+; COND-NEXT: msr FPMR, x0
+; COND-NEXT: .LBB4_2:
+; COND-NEXT: ret
+ call void @llvm.aarch64.set.fpmr(i64 %sr)
+ ret void
+}
+
+define void @set_fpmr_then_fp8_cvt_and_store(i64 %fpmr, ptr %a, ptr %b, ptr %out) {
+; DIRECT-LABEL: set_fpmr_then_fp8_cvt_and_store:
+; DIRECT: // %bb.0:
+; DIRECT-NEXT: msr FPMR, x0
+; DIRECT-NEXT: ldr d0, [x1]
+; DIRECT-NEXT: ldr d1, [x2]
+; DIRECT-NEXT: fcvtn v0.8b, v0.4h, v1.4h
+; DIRECT-NEXT: str d0, [x3]
+; DIRECT-NEXT: ret
+; COND-LABEL: set_fpmr_then_fp8_cvt_and_store:
+; COND: // %bb.0:
+; COND-NEXT: mrs x8, FPMR
+; COND-NEXT: cmp x8, x0
+; COND-NEXT: b.eq .LBB5_2
+; COND-NEXT: // %bb.1:
+; COND-NEXT: msr FPMR, x0
+; COND-NEXT: .LBB5_2:
+; COND-NEXT: ldr d0, [x1]
+; COND-NEXT: ldr d1, [x2]
+; COND-NEXT: fcvtn v0.8b, v0.4h, v1.4h
+; COND-NEXT: str d0, [x3]
+; COND-NEXT: ret
+ call void @llvm.aarch64.set.fpmr(i64 %fpmr)
+ %va = load <4 x half>, ptr %a, align 8
+ %vb = load <4 x half>, ptr %b, align 8
+ %res = call <8 x i8> @llvm.aarch64.neon.fp8.fcvtn.v8i8.v4f16(<4 x half> %va, <4 x half> %vb)
+ store <8 x i8> %res, ptr %out, align 8
+ ret void
}
declare i64 @llvm.aarch64.get.fpcr()
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