[llvm] [AMDGPU] Add MC omod support for bf16 trans instructions (PR #205144)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 22 10:09:14 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Changpeng Fang (changpeng)
<details>
<summary>Changes</summary>
Based on recent gfx1250 sp3 update. Refer to DEGFXSP3-664
---
Full diff: https://github.com/llvm/llvm-project/pull/205144.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/VOP1Instructions.td (-3)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s (-40)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s (+24)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s (+24)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt (+32)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index d504b440b4fe4..bb112ddb329df 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -533,12 +533,9 @@ defm V_CVT_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_u16_f16",
defm V_CVT_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_i16_f16",
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_sint>;
-
-let HasOMod = 0 in {
def V_TRANS_BF16_Profile : VOPProfile <[bf16, bf16, untyped, untyped]>;
def V_TRANS_BF16_t16_Profile : VOPProfile_True16 <VOP_BF16_BF16>;
def V_TRANS_BF16_fake16_Profile : VOPProfile_Fake16 <VOP_BF16_BF16>;
-}
let TRANS = 1, SchedRW = [WriteTrans32] in {
defm V_RCP_F16 : VOP1Inst_t16 <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
index 43733c28be642..35375d4e62597 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
@@ -34,43 +34,3 @@ v_cvt_f32_bf16 v5, v1 div:2
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
// GFX1250-ERR-NEXT:{{^}}v_cvt_f32_bf16 v5, v1 div:2
// GFX1250-ERR-NEXT:{{^}} ^
-
-v_cos_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_cos_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_exp_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_exp_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_log_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_log_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_rcp_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_rcp_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_rsq_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_rsq_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_sin_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_sin_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_sqrt_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_sqrt_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
-
-v_tanh_bf16 v1, v2 mul:2
-// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
-// GFX1250-ERR-NEXT:{{^}}v_tanh_bf16 v1, v2 mul:2
-// GFX1250-ERR-NEXT:{{^}} ^
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
index 61497adad6206..da3974cc30115 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
@@ -3751,6 +3751,9 @@ v_tanh_bf16_e64 v5, v1
v_tanh_bf16_e64 v5, v1 clamp
// GFX1250: v_tanh_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+v_tanh_bf16_e64 v5, v1 mul:4
+// GFX1250: v_tanh_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x12]
+
v_tanh_bf16_e64 v5, v255
// GFX1250: v_tanh_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xca,0xd5,0xff,0x01,0x01,0x02]
@@ -3826,6 +3829,9 @@ v_rcp_bf16_e64 v5, v1
v_rcp_bf16_e64 v5, v1 clamp
// GFX1250: v_rcp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+v_rcp_bf16_e64 v5, v1 mul:2
+// GFX1250: v_rcp_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x0a]
+
v_rcp_bf16_e64 v5, v255
// GFX1250: v_rcp_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xf9,0xd5,0xff,0x01,0x01,0x02]
@@ -3865,6 +3871,9 @@ v_sqrt_bf16_e64 v5, v1
v_sqrt_bf16_e64 v5, v1 clamp
// GFX1250: v_sqrt_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+v_sqrt_bf16_e64 v5, v1 mul:4
+// GFX1250: v_sqrt_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x12]
+
v_sqrt_bf16_e64 v5, v255
// GFX1250: v_sqrt_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfa,0xd5,0xff,0x01,0x01,0x02]
@@ -3904,6 +3913,9 @@ v_rsq_bf16_e64 v5, v1
v_rsq_bf16_e64 v5, v1 clamp
// GFX1250: v_rsq_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+v_rsq_bf16_e64 v5, v1 div:2
+// GFX1250: v_rsq_bf16_e64 v5, v1 div:2 ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x1a]
+
v_rsq_bf16_e64 v5, v255
// GFX1250: v_rsq_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfb,0xd5,0xff,0x01,0x01,0x02]
@@ -3943,6 +3955,9 @@ v_log_bf16_e64 v5, v1
v_log_bf16_e64 v5, v1 clamp
// GFX1250: v_log_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+v_log_bf16_e64 v5, v1 mul:2
+// GFX1250: v_log_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x0a]
+
v_log_bf16_e64 v5, v255
// GFX1250: v_log_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfc,0xd5,0xff,0x01,0x01,0x02]
@@ -3982,6 +3997,9 @@ v_exp_bf16_e64 v5, v1
v_exp_bf16_e64 v5, v1 clamp
// GFX1250: v_exp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+v_exp_bf16_e64 v5, v1 mul:4
+// GFX1250: v_exp_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x12]
+
v_exp_bf16_e64 v5, v255
// GFX1250: v_exp_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfd,0xd5,0xff,0x01,0x01,0x02]
@@ -4021,6 +4039,9 @@ v_sin_bf16_e64 v5, v1
v_sin_bf16_e64 v5, v1 clamp
// GFX1250: v_sin_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+v_sin_bf16_e64 v5, v1 div:2
+// GFX1250: v_sin_bf16_e64 v5, v1 div:2 ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x1a]
+
v_sin_bf16_e64 v5, v255
// GFX1250: v_sin_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xfe,0xd5,0xff,0x01,0x01,0x02]
@@ -4060,6 +4081,9 @@ v_cos_bf16_e64 v5, v1
v_cos_bf16_e64 v5, v1 clamp
// GFX1250: v_cos_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+v_cos_bf16_e64 v5, v1 mul:2
+// GFX1250: v_cos_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x0a]
+
v_cos_bf16_e64 v5, v255
// GFX1250: v_cos_bf16_e64 v5, v255 ; encoding: [0x05,0x00,0xff,0xd5,0xff,0x01,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
index e31a644345d70..5828742ae751f 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
@@ -3922,6 +3922,9 @@ v_tanh_bf16_e64 v5.l, v1.l
v_tanh_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_tanh_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+v_tanh_bf16_e64 v5.l, v1.l mul:4
+// GFX1250: v_tanh_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x12]
+
v_tanh_bf16_e64 v5.l, v255.l
// GFX1250: v_tanh_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xca,0xd5,0xff,0x01,0x01,0x02]
@@ -4000,6 +4003,9 @@ v_rcp_bf16_e64 v5.l, v1.l
v_rcp_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_rcp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+v_rcp_bf16_e64 v5.l, v1.l mul:2
+// GFX1250: v_rcp_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x0a]
+
v_rcp_bf16_e64 v5.l, v255.l
// GFX1250: v_rcp_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xf9,0xd5,0xff,0x01,0x01,0x02]
@@ -4042,6 +4048,9 @@ v_sqrt_bf16_e64 v5.l, v1.l
v_sqrt_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_sqrt_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+v_sqrt_bf16_e64 v5.l, v1.l mul:4
+// GFX1250: v_sqrt_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x12]
+
v_sqrt_bf16_e64 v5.l, v255.l
// GFX1250: v_sqrt_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfa,0xd5,0xff,0x01,0x01,0x02]
@@ -4084,6 +4093,9 @@ v_rsq_bf16_e64 v5.l, v1.l
v_rsq_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_rsq_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+v_rsq_bf16_e64 v5.l, v1.l div:2
+// GFX1250: v_rsq_bf16_e64 v5.l, v1.l div:2 ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x1a]
+
v_rsq_bf16_e64 v5.l, v255.l
// GFX1250: v_rsq_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfb,0xd5,0xff,0x01,0x01,0x02]
@@ -4126,6 +4138,9 @@ v_log_bf16_e64 v5.l, v1.l
v_log_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_log_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+v_log_bf16_e64 v5.l, v1.l mul:2
+// GFX1250: v_log_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x0a]
+
v_log_bf16_e64 v5.l, v255.l
// GFX1250: v_log_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfc,0xd5,0xff,0x01,0x01,0x02]
@@ -4168,6 +4183,9 @@ v_exp_bf16_e64 v5.l, v1.l
v_exp_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_exp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+v_exp_bf16_e64 v5.l, v1.l mul:4
+// GFX1250: v_exp_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x12]
+
v_exp_bf16_e64 v5.l, v255.l
// GFX1250: v_exp_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfd,0xd5,0xff,0x01,0x01,0x02]
@@ -4210,6 +4228,9 @@ v_sin_bf16_e64 v5.l, v1.l
v_sin_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_sin_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+v_sin_bf16_e64 v5.l, v1.l div:2
+// GFX1250: v_sin_bf16_e64 v5.l, v1.l div:2 ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x1a]
+
v_sin_bf16_e64 v5.l, v255.l
// GFX1250: v_sin_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xfe,0xd5,0xff,0x01,0x01,0x02]
@@ -4252,6 +4273,9 @@ v_cos_bf16_e64 v5.l, v1.l
v_cos_bf16_e64 v5.l, v1.l clamp
// GFX1250: v_cos_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+v_cos_bf16_e64 v5.l, v1.l mul:2
+// GFX1250: v_cos_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x0a]
+
v_cos_bf16_e64 v5.l, v255.l
// GFX1250: v_cos_bf16_e64 v5.l, v255.l ; encoding: [0x05,0x00,0xff,0xd5,0xff,0x01,0x01,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
index 73a38bfcce68d..56857abc530d9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
@@ -4134,6 +4134,10 @@
# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xca,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x12
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x12]
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xca,0xd5,0x01,0x01,0x01,0x12]
+
0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_tanh_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xca,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xca,0xd5,0x7f,0x00,0x01,0x02]
@@ -4226,6 +4230,10 @@
# GFX1250-FAKE16: v_rcp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xf9,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x0a
+# GFX1250-FAKE16: v_rcp_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x0a]
+# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xf9,0xd5,0x01,0x01,0x01,0x0a]
+
0x05,0x00,0xf9,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_rcp_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xf9,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_rcp_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xf9,0xd5,0x7f,0x00,0x01,0x02]
@@ -4282,6 +4290,10 @@
# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfa,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x12
+# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x12]
+# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xfa,0xd5,0x01,0x01,0x01,0x12]
+
0x05,0x00,0xfa,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_sqrt_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfa,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_sqrt_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfa,0xd5,0x7f,0x00,0x01,0x02]
@@ -4338,6 +4350,10 @@
# GFX1250-FAKE16: v_rsq_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfb,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x1a
+# GFX1250-FAKE16: v_rsq_bf16_e64 v5, v1 div:2 ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x1a]
+# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, v1.l div:2 ; encoding: [0x05,0x00,0xfb,0xd5,0x01,0x01,0x01,0x1a]
+
0x05,0x00,0xfb,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_rsq_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfb,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_rsq_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfb,0xd5,0x7f,0x00,0x01,0x02]
@@ -4394,6 +4410,10 @@
# GFX1250-FAKE16: v_log_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_log_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfc,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x0a
+# GFX1250-FAKE16: v_log_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x0a]
+# GFX1250-REAL16: v_log_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xfc,0xd5,0x01,0x01,0x01,0x0a]
+
0x05,0x00,0xfc,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_log_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfc,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_log_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfc,0xd5,0x7f,0x00,0x01,0x02]
@@ -4450,6 +4470,10 @@
# GFX1250-FAKE16: v_exp_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_exp_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfd,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x12
+# GFX1250-FAKE16: v_exp_bf16_e64 v5, v1 mul:4 ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x12]
+# GFX1250-REAL16: v_exp_bf16_e64 v5.l, v1.l mul:4 ; encoding: [0x05,0x00,0xfd,0xd5,0x01,0x01,0x01,0x12]
+
0x05,0x00,0xfd,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_exp_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfd,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_exp_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfd,0xd5,0x7f,0x00,0x01,0x02]
@@ -4506,6 +4530,10 @@
# GFX1250-FAKE16: v_sin_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_sin_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xfe,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x1a
+# GFX1250-FAKE16: v_sin_bf16_e64 v5, v1 div:2 ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x1a]
+# GFX1250-REAL16: v_sin_bf16_e64 v5.l, v1.l div:2 ; encoding: [0x05,0x00,0xfe,0xd5,0x01,0x01,0x01,0x1a]
+
0x05,0x00,0xfe,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_sin_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xfe,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_sin_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xfe,0xd5,0x7f,0x00,0x01,0x02]
@@ -4562,6 +4590,10 @@
# GFX1250-FAKE16: v_cos_bf16_e64 v5, v1 clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
# GFX1250-REAL16: v_cos_bf16_e64 v5.l, v1.l clamp ; encoding: [0x05,0x80,0xff,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x0a
+# GFX1250-FAKE16: v_cos_bf16_e64 v5, v1 mul:2 ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x0a]
+# GFX1250-REAL16: v_cos_bf16_e64 v5.l, v1.l mul:2 ; encoding: [0x05,0x00,0xff,0xd5,0x01,0x01,0x01,0x0a]
+
0x05,0x00,0xff,0xd5,0x7f,0x00,0x00,0x00
# GFX1250-FAKE16: v_cos_bf16_e64 v5, exec_hi ; encoding: [0x05,0x00,0xff,0xd5,0x7f,0x00,0x01,0x02]
# GFX1250-REAL16: v_cos_bf16_e64 v5.l, exec_hi ; encoding: [0x05,0x00,0xff,0xd5,0x7f,0x00,0x01,0x02]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205144
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