[llvm] 97fe69e - [AMDGPU] Add a test for sext i1 feeding into icmp (#205121)

[via llvm-commits]

Author: Jay Foad
Date: 2026-06-22T16:04:39Z
New Revision: 97fe69eaec8920e84308f80ade9e641aa424267b

URL: https://github.com/llvm/llvm-project/commit/97fe69eaec8920e84308f80ade9e641aa424267b
DIFF: https://github.com/llvm/llvm-project/commit/97fe69eaec8920e84308f80ade9e641aa424267b.diff

LOG: [AMDGPU] Add a test for sext i1 feeding into icmp (#205121)

This is a precommit of a test case that causes problems for #204238.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/sign_extend.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/sign_extend.ll b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
index ece46b59ba49e..373618f3da1b8 100644
--- a/llvm/test/CodeGen/AMDGPU/sign_extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
@@ -604,6 +604,34 @@ define amdgpu_kernel void @v_sext_v4i16_to_v4i32(ptr addrspace(1) %out, ptr addr
   ret void
 }
 
+define i32 @s_ext_cmp_ext(i32 %arg, float inreg %x) {
+; SI-LABEL: s_ext_cmp_ext:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_cvt_u32_f32_e32 v1, s16
+; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; SI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
+; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
+; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: s_ext_cmp_ext:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_cvt_u32_f32_e32 v1, s16
+; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; VI-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
+; VI-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
+; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; VI-NEXT:    s_setpc_b64 s[30:31]
+  %cvt = fptoui float %x to i32
+  %ne = icmp ne i32 %cvt, 0
+  %sext = sext i1 %ne to i32
+  %eq = icmp eq i32 %arg, %sext
+  %zext = zext i1 %eq to i32
+  ret i32 %zext
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #1 = { nounwind readnone }