[llvm] [SPIR-V] Access-chain aggregate pointers to element 0 for cooperative matrix load/store (PR #202050)

[Juan Manuel Martinez Caamaño via llvm-commits]

================
@@ -1609,6 +1611,50 @@ bool SPIRVInstructionSelector::selectSincos(Register ResVReg,
   return false;
 }
 
+Register SPIRVInstructionSelector::coopMatrixElementPtr(Register PtrReg,
+                                                        MachineInstr &I) const {
+  SPIRVTypeInst PtrType = GR.getSPIRVTypeForVReg(PtrReg);
+  if (!PtrType)
+    return PtrReg;
+  SPIRVTypeInst PointeeType = GR.getPointeeType(PtrType);
+  if (!PointeeType || PointeeType->getOpcode() != SPIRV::OpTypeArray)
+    return PtrReg;
+  SPIRVTypeInst ElemType =
+      GR.getSPIRVTypeForVReg(PointeeType->getOperand(1).getReg());
+  if (!ElemType)
+    return PtrReg;
+  SPIRV::StorageClass::StorageClass SC = GR.getPointerStorageClass(PtrReg);
+  MachineIRBuilder MIRBuilder(I);
+  SPIRVTypeInst ElemPtrType =
+      GR.getOrCreateSPIRVPointerType(ElemType, MIRBuilder, SC);
+  SPIRVTypeInst I32Type = GR.getOrCreateSPIRVIntegerType(32, I, TII);
+  Register Zero = buildZerosVal(I32Type, I);
+  Register NewPtr = MRI->createVirtualRegister(GR.getRegClass(ElemPtrType));
+  GR.assignSPIRVTypeToVReg(ElemPtrType, NewPtr, *I.getParent()->getParent());
+  bool IsLogical = STI.isLogicalSPIRV();
+  unsigned Opcode = IsLogical ? SPIRV::OpAccessChain : SPIRV::OpPtrAccessChain;
+  auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
+                 .addDef(NewPtr)
+                 .addUse(GR.getSPIRVTypeID(ElemPtrType))
+                 .addUse(PtrReg);
----------------
jmmartinez wrote:

Can you use the `MIRBuilder` that you built before for this?

Something like:

```cpp
auto MIB = MIRBuilder.buildInstr(Opcode).addDef(NewPtr);
```

https://github.com/llvm/llvm-project/pull/202050