[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for pk_u64 add and sub (PR #205079)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 22 04:06:36 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/205079
None
>From 63f99556df04ceb2d6f2833e3e16cdd137d6ee9b Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Mon, 15 Jun 2026 14:06:44 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for pk_u64 add and
sub
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 4 ++-
llvm/test/CodeGen/AMDGPU/packed-u64.ll | 30 ++++++++++++++-----
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 0f0c9557e4e60..b0a8c1dd11e6e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -593,7 +593,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, UnpackAExt})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}})
- .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}});
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
+ .Any({{UniV2S64}, {{UniInVgprV2S64}, {VgprV2S64, VgprV2S64}}})
+ .Any({{DivV2S64}, {{VgprV2S64}, {VgprV2S64, VgprV2S64}}});
addRulesForGOpcs({G_UADDO, G_USUBO}, Standard)
.Uni(S32, {{Sgpr32, Sgpr32Trunc}, {Sgpr32, Sgpr32}})
diff --git a/llvm/test/CodeGen/AMDGPU/packed-u64.ll b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
index ea3c4ce56ae52..c1140977339dc 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-SDAG %s
-; xUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1251,GFX1251-GISEL %s
define amdgpu_kernel void @add_v2_vv(ptr addrspace(1) %a) {
; GFX1251-LABEL: add_v2_vv:
@@ -70,16 +70,24 @@ define amdgpu_kernel void @add_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64
; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1251-GISEL-NEXT: s_clause 0x1
; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
-; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX1251-GISEL-NEXT: s_endpgm
%add = add <2 x i64> %x, %y
store <2 x i64> %add, ptr addrspace(1) %a, align 8
@@ -705,16 +713,24 @@ define amdgpu_kernel void @sub_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64
; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1251-GISEL-NEXT: s_clause 0x1
; GFX1251-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
-; GFX1251-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1251-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX1251-GISEL-NEXT: s_endpgm
%sub = sub <2 x i64> %x, %y
store <2 x i64> %sub, ptr addrspace(1) %a, align 8
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