[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

Kito Cheng via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 22 02:57:50 PDT 2026

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https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/97010

Previous message: [llvm] [RISCV] Lower non-power-of-2 vector to nearest power-of-2 vector leng… (PR #106092)
Next message: [llvm] 192ef55 - AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default (#203928)
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