[llvm] [RISCV] Support floating point registers with -fzero-call-used-regs (PR #204929)

[Craig Topper via llvm-commits]

================
@@ -1432,6 +1432,34 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   emitSiFiveCLICStackSwap(MF, MBB, MBBI, DL);
 }
 
+static MCRegister getLargestFPRegisterOrZero(const RISCVSubtarget &STI,
+                                             const TargetRegisterInfo &TRI,
+                                             MCRegister Reg) {
+  if (!STI.hasStdExtF())
+    return 0;
+
+  TargetRegisterClass LargestFPRegClass = STI.getLargestFPRegClass().value();
+
+  if (LargestFPRegClass.contains(Reg))
+    return Reg;
+
+  std::array<TargetRegisterClass, 3> RegisterClasses = {
+      RISCV::FPR16RegClass, RISCV::FPR32RegClass, RISCV::FPR64RegClass};
+  std::array<int, 3> SubIdx = {RISCV::sub_16, RISCV::sub_32, RISCV::sub_64};
+
+  for (unsigned i = 0; i < RegisterClasses.size(); ++i) {
----------------
topperc wrote:

You can use `zip` to make this a range loop. Something like

```
for (auto [RegClass, SubReg] : zip(RegisterClasses, SubIdx))
```

https://github.com/llvm/llvm-project/pull/204929