[llvm] [RISCV] Update Xqcilo Pseudos (PR #196422)

[Sam Elliott via llvm-commits]

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@@ -108,7 +108,14 @@ class RISCVUImmLsbZeroOp<int width, int zeros>
 }
 
 // A 7-bit unsigned immediate where the least significant two bits are zero.
-def uimm7_lsb00 : RISCVUImmLsbZeroOp<7, 2>;
+def uimm7_lsb00 : RISCVUImmLsbZeroOp<7, 2> {
+  let MCOperandPredicate = [{
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lenary wrote:

You already did this in January, so I can remove this code: c563a88413f1139a0c81153101cadcd3227c6d6e

https://github.com/llvm/llvm-project/pull/196422