[llvm] 6b7dbd8 - AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 mfmas (#204696)

[via llvm-commits]

Author: vangthao95
Date: 2026-06-19T10:51:44-07:00
New Revision: 6b7dbd8f485dc710f41fe5383ac99c2c42f9f6b9

URL: https://github.com/llvm/llvm-project/commit/6b7dbd8f485dc710f41fe5383ac99c2c42f9f6b9
DIFF: https://github.com/llvm/llvm-project/commit/6b7dbd8f485dc710f41fe5383ac99c2c42f9f6b9.diff

LOG: AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 mfmas (#204696)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 00ac786855c89..da2fed40539f3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2632,16 +2632,34 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
 
   // gfx90a+ only MFMAs
   addRulesForIOpcs(
-      {amdgcn_mfma_f32_32x32x4bf16_1k, amdgcn_mfma_f32_16x16x4bf16_1k,
-       amdgcn_mfma_f32_4x4x4bf16_1k, amdgcn_mfma_f32_32x32x8bf16_1k,
-       amdgcn_mfma_f32_16x16x16bf16_1k, amdgcn_mfma_f64_16x16x4f64,
-       amdgcn_mfma_f64_4x4x4f64, amdgcn_mfma_i32_16x16x32_i8,
-       amdgcn_mfma_i32_32x32x16_i8, amdgcn_mfma_f32_16x16x8_xf32,
-       amdgcn_mfma_f32_32x32x4_xf32, amdgcn_mfma_f32_16x16x32_bf8_bf8,
-       amdgcn_mfma_f32_16x16x32_bf8_fp8, amdgcn_mfma_f32_16x16x32_fp8_bf8,
-       amdgcn_mfma_f32_16x16x32_fp8_fp8, amdgcn_mfma_f32_32x32x16_bf8_bf8,
-       amdgcn_mfma_f32_32x32x16_bf8_fp8, amdgcn_mfma_f32_32x32x16_fp8_bf8,
-       amdgcn_mfma_f32_32x32x16_fp8_fp8})
+      {
+          amdgcn_mfma_f32_32x32x4bf16_1k,
+          amdgcn_mfma_f32_16x16x4bf16_1k,
+          amdgcn_mfma_f32_4x4x4bf16_1k,
+          amdgcn_mfma_f32_32x32x8bf16_1k,
+          amdgcn_mfma_f32_16x16x16bf16_1k,
+          amdgcn_mfma_f64_16x16x4f64,
+          amdgcn_mfma_f64_4x4x4f64,
+          amdgcn_mfma_i32_16x16x32_i8,
+          amdgcn_mfma_i32_32x32x16_i8,
+          amdgcn_mfma_f32_16x16x8_xf32,
+          amdgcn_mfma_f32_32x32x4_xf32,
+          amdgcn_mfma_f32_16x16x32_bf8_bf8,
+          amdgcn_mfma_f32_16x16x32_bf8_fp8,
+          amdgcn_mfma_f32_16x16x32_fp8_bf8,
+          amdgcn_mfma_f32_16x16x32_fp8_fp8,
+          amdgcn_mfma_f32_32x32x16_bf8_bf8,
+          amdgcn_mfma_f32_32x32x16_bf8_fp8,
+          amdgcn_mfma_f32_32x32x16_fp8_bf8,
+          amdgcn_mfma_f32_32x32x16_fp8_fp8,
+          // gfx950
+          amdgcn_mfma_f32_16x16x32_f16,
+          amdgcn_mfma_f32_32x32x16_f16,
+          amdgcn_mfma_i32_16x16x64_i8,
+          amdgcn_mfma_i32_32x32x32_i8,
+          // TODO: bf16 variants fail in IRTranslator.
+          // amdgcn_mfma_f32_16x16x32_bf16, amdgcn_mfma_f32_32x32x16_bf16,
+      })
       .Any({{DivAnyTy},
             {{VgprOrAgprAnyTy},
              {IntrId, VgprAnyTy, VgprAnyTy, VgprOrAgprAnyTy}}});

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
index a1fe463de1c54..78e9c9294cd09 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -new-reg-bank-select -global-isel-abort=2 < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GISEL %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 --amdgpu-mfma-vgpr-form=0 < %s | FileCheck -enable-var-scope --check-prefixes=HEURRC %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 --amdgpu-mfma-vgpr-form=1 < %s | FileCheck -enable-var-scope --check-prefixes=VGPRRC %s