[llvm] [MachineSink] Allow readReg instead of isUse (PR #204610)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 19 09:02:18 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/204610
>From 90a1ccbe252376e750bea83f493cfb799b1ac1df Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Fri, 19 Jun 2026 11:27:46 -0400
Subject: [PATCH 1/2] Pre-commit tests (NFC)
---
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../postra-machine-sink-undef-internal.mir | 57 +++++++++++++++++++
.../X86/postra-machine-sink-undef-use.mir | 57 +++++++++++++++++++
8 files changed, 456 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
create mode 100644 llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
diff --git a/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..a54ba5011c0c2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x1 = COPY killed renamable $x0, implicit undef $x2
+ ; CHECK-NEXT: $x2 = COPY $xzr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: RET_ReallyLR implicit $x1
+ bb.0:
+ liveins: $x0, $x2
+ successors: %bb.1
+
+ renamable $x1 = COPY killed renamable $x0, implicit undef $x2
+ $x2 = COPY $xzr
+
+ bb.1:
+ liveins: $x1
+ RET_ReallyLR implicit $x1
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x1 = COPY killed renamable $x0, implicit-def $x2, implicit internal $x2
+ ; CHECK-NEXT: $x3 = COPY $xzr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: RET_ReallyLR implicit $x1
+ bb.0:
+ liveins: $x0
+ successors: %bb.1
+
+ renamable $x1 = COPY killed renamable $x0, implicit-def $x2, implicit internal $x2
+ $x3 = COPY $xzr
+
+ bb.1:
+ liveins: $x1
+ RET_ReallyLR implicit $x1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..34453b9dae6ea
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr0 = S_MOV_B32 1
+ ; CHECK-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr0, implicit undef $vgpr0
+ ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr1
+ bb.0:
+ successors: %bb.1
+
+ renamable $sgpr0 = S_MOV_B32 1
+ renamable $sgpr1 = COPY killed renamable $sgpr0, implicit undef $vgpr0
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+
+ bb.1:
+ liveins: $sgpr1
+ S_ENDPGM 0, implicit $sgpr1
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr0 = S_MOV_B32 1
+ ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $sgpr0, $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr0, implicit-def $vgpr0, implicit internal $vgpr0
+ ; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr1
+ bb.0:
+ successors: %bb.1
+
+ renamable $sgpr0 = S_MOV_B32 1
+ renamable $sgpr1 = COPY killed renamable $sgpr0, implicit-def $vgpr0, implicit internal $vgpr0
+ $vgpr1 = V_MOV_B32_e32 0, implicit $exec
+
+ bb.1:
+ liveins: $sgpr1, $vgpr0
+ S_ENDPGM 0, implicit $sgpr1
+...
diff --git a/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..c95e1d2bfd4d7
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=armv7-apple-ios -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
+ ; CHECK-NEXT: $r2 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r1
+ bb.0:
+ successors: %bb.1
+
+ renamable $r0 = MOVi 1, 14, $noreg, $noreg
+ renamable $r1 = COPY killed renamable $r0, implicit undef $r2
+ $r2 = MOVi 0, 14, $noreg, $noreg
+
+ bb.1:
+ liveins: $r1
+ BX_RET 14, $noreg, implicit $r1
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit-def $r2, implicit internal $r2
+ ; CHECK-NEXT: $r3 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r1
+ bb.0:
+ successors: %bb.1
+
+ renamable $r0 = MOVi 1, 14, $noreg, $noreg
+ renamable $r1 = COPY killed renamable $r0, implicit-def $r2, implicit internal $r2
+ $r3 = MOVi 0, 14, $noreg, $noreg
+
+ bb.1:
+ liveins: $r1
+ BX_RET 14, $noreg, implicit $r1
+...
diff --git a/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..b7ffa261841b5
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=hexagon -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = A2_tfrsi 1
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
+ ; CHECK-NEXT: $r2 = A2_tfrsi 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_jumpr $r31, implicit-def $pc, implicit $r1
+ bb.0:
+ successors: %bb.1
+
+ renamable $r0 = A2_tfrsi 1
+ renamable $r1 = COPY killed renamable $r0, implicit undef $r2
+ $r2 = A2_tfrsi 0
+
+ bb.1:
+ liveins: $r1
+ J2_jumpr $r31, implicit-def $pc, implicit $r1
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = A2_tfrsi 1
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit-def $r2, implicit internal $r2
+ ; CHECK-NEXT: $r3 = A2_tfrsi 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_jumpr $r31, implicit-def $pc, implicit $r1
+ bb.0:
+ successors: %bb.1
+
+ renamable $r0 = A2_tfrsi 1
+ renamable $r1 = COPY killed renamable $r0, implicit-def $r2, implicit internal $r2
+ $r3 = A2_tfrsi 0
+
+ bb.1:
+ liveins: $r1
+ J2_jumpr $r31, implicit-def $pc, implicit $r1
+...
diff --git a/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..1aa290186e0d1
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mips -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $a0 = LUi 1
+ ; CHECK-NEXT: renamable $a1 = COPY killed renamable $a0, implicit undef $a2
+ ; CHECK-NEXT: $a2 = LUi 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $a1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: RetRA implicit $a1
+ bb.0:
+ successors: %bb.1
+
+ renamable $a0 = LUi 1
+ renamable $a1 = COPY killed renamable $a0, implicit undef $a2
+ $a2 = LUi 0
+
+ bb.1:
+ liveins: $a1
+ RetRA implicit $a1
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $a0 = LUi 1
+ ; CHECK-NEXT: renamable $a1 = COPY killed renamable $a0, implicit-def $a2, implicit internal $a2
+ ; CHECK-NEXT: $a3 = LUi 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $a1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: RetRA implicit $a1
+ bb.0:
+ successors: %bb.1
+
+ renamable $a0 = LUi 1
+ renamable $a1 = COPY killed renamable $a0, implicit-def $a2, implicit internal $a2
+ $a3 = LUi 0
+
+ bb.1:
+ liveins: $a1
+ RetRA implicit $a1
+...
diff --git a/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..e9874c5df566b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=powerpc64le -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x3 = LI8 1
+ ; CHECK-NEXT: renamable $x4 = COPY killed renamable $x3, implicit undef $x5
+ ; CHECK-NEXT: $x5 = LI8 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x4
+ bb.0:
+ successors: %bb.1
+
+ renamable $x3 = LI8 1
+ renamable $x4 = COPY killed renamable $x3, implicit undef $x5
+ $x5 = LI8 0
+
+ bb.1:
+ liveins: $x4
+ BLR8 implicit $lr8, implicit $rm, implicit $x4
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x3 = LI8 1
+ ; CHECK-NEXT: renamable $x4 = COPY killed renamable $x3, implicit-def $x5, implicit internal $x5
+ ; CHECK-NEXT: $x6 = LI8 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x4
+ bb.0:
+ successors: %bb.1
+
+ renamable $x3 = LI8 1
+ renamable $x4 = COPY killed renamable $x3, implicit-def $x5, implicit internal $x5
+ $x6 = LI8 0
+
+ bb.1:
+ liveins: $x4
+ BLR8 implicit $lr8, implicit $rm, implicit $x4
+...
diff --git a/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
new file mode 100644
index 0000000000000..d98e02f18e57f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1
+ ; CHECK-NEXT: renamable $x11 = COPY killed renamable $x10, implicit undef $x12
+ ; CHECK-NEXT: $x12 = ADDI $x0, 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x11
+ bb.0:
+ successors: %bb.1
+
+ renamable $x10 = ADDI $x0, 1
+ renamable $x11 = COPY killed renamable $x10, implicit undef $x12
+ $x12 = ADDI $x0, 0
+
+ bb.1:
+ liveins: $x11
+ PseudoRET implicit $x11
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1
+ ; CHECK-NEXT: renamable $x11 = COPY killed renamable $x10, implicit-def $x12, implicit internal $x12
+ ; CHECK-NEXT: $x13 = ADDI $x0, 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: PseudoRET implicit $x11
+ bb.0:
+ successors: %bb.1
+
+ renamable $x10 = ADDI $x0, 1
+ renamable $x11 = COPY killed renamable $x10, implicit-def $x12, implicit internal $x12
+ $x13 = ADDI $x0, 0
+
+ bb.1:
+ liveins: $x11
+ PseudoRET implicit $x11
+...
diff --git a/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir b/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
new file mode 100644
index 0000000000000..0b09f16a2b25c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=postra-machine-sink -o - %s | FileCheck %s
+
+---
+name: test_undef_use_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_undef_use_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $ebx = MOV32ri 1
+ ; CHECK-NEXT: renamable $eax = COPY killed renamable $ebx, implicit undef $ecx
+ ; CHECK-NEXT: $ecx = MOV32ri 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: RET 0, $eax
+ bb.0:
+ successors: %bb.1
+
+ renamable $ebx = MOV32ri 1
+ renamable $eax = COPY killed renamable $ebx, implicit undef $ecx
+ $ecx = MOV32ri 0
+
+ bb.1:
+ liveins: $eax
+ RET 0, $eax
+...
+---
+name: test_internal_read_sinking
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_internal_read_sinking
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $ebx = MOV32ri 1
+ ; CHECK-NEXT: $edx = MOV32ri 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $ebx, $ecx
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $eax = COPY killed renamable $ebx, implicit-def $ecx, implicit internal $ecx
+ ; CHECK-NEXT: RET 0, $eax
+ bb.0:
+ successors: %bb.1
+
+ renamable $ebx = MOV32ri 1
+ renamable $eax = COPY killed renamable $ebx, implicit-def $ecx, implicit internal $ecx
+ $edx = MOV32ri 0
+
+ bb.1:
+ liveins: $eax, $ecx
+ RET 0, $eax
+...
>From f95bc5a11bf48a55ce9c2897bb4b91841781dee0 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Fri, 19 Jun 2026 11:27:58 -0400
Subject: [PATCH 2/2] [MachineSink] Allow readReg instead of isUse
When an instruction (or bundle) is sunk, the entire instruction moves together. An internal read (isInternalRead()) indicates that the operand reads a value defined inside the same instruction or bundle. Because both the definition and the read move together, the internal read doesn't introduce any data dependency on the register's state from outside the instruction.
Therefore, ignoring internal reads when evaluating register dependencies for sinking is fundamentally safe across all targets.
Similarly, ignoring undef uses (which readsReg() also does) is safe because an undef operand explicitly doesn't care about the previous register value, meaning it doesn't create any cross-instruction data dependencies that would prevent sinking.
---
llvm/lib/CodeGen/MachineSink.cpp | 7 +------
.../CodeGen/AArch64/postra-machine-sink-undef-internal.mir | 4 ++--
.../CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir | 6 +++---
.../CodeGen/ARM/postra-machine-sink-undef-internal.mir | 4 ++--
.../CodeGen/Hexagon/postra-machine-sink-undef-internal.mir | 4 ++--
.../CodeGen/Mips/postra-machine-sink-undef-internal.mir | 4 ++--
.../CodeGen/PowerPC/postra-machine-sink-undef-internal.mir | 4 ++--
.../CodeGen/RISCV/postra-machine-sink-undef-internal.mir | 4 ++--
llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir | 6 +++---
9 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index da9eaa68d22e0..b711d5c90281f 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2223,12 +2223,7 @@ static bool hasRegisterDependency(MachineInstr *MI,
break;
}
DefedRegsInCopy.push_back(Reg);
-
- // FIXME: instead of isUse(), readsReg() would be a better fix here,
- // For example, we can ignore modifications in reg with undef. However,
- // it's not perfectly clear if skipping the internal read is safe in all
- // other targets.
- } else if (MO.isUse()) {
+ } else if (MO.readsReg()) {
if (!ModifiedRegUnits.available(Reg)) {
HasRegDependency = true;
break;
diff --git a/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
index a54ba5011c0c2..2edcda68e3a2e 100644
--- a/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/AArch64/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x0, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x1 = COPY killed renamable $x0, implicit undef $x2
; CHECK-NEXT: $x2 = COPY $xzr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $x1
+ ; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x1 = COPY killed renamable $x0, implicit undef $x2
; CHECK-NEXT: RET_ReallyLR implicit $x1
bb.0:
liveins: $x0, $x2
diff --git a/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
index 34453b9dae6ea..9f4e396c159ec 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/AMDGPU/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr0 = S_MOV_B32 1
- ; CHECK-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr0, implicit undef $vgpr0
; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $sgpr1
+ ; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr0, implicit undef $vgpr0
; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr1
bb.0:
successors: %bb.1
@@ -40,7 +40,7 @@ body: |
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $sgpr0, $vgpr0
+ ; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr1 = COPY killed renamable $sgpr0, implicit-def $vgpr0, implicit internal $vgpr0
; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr1
diff --git a/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
index c95e1d2bfd4d7..dff912a03fcc6 100644
--- a/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/ARM/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
; CHECK-NEXT: $r2 = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: liveins: $r0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r1
bb.0:
successors: %bb.1
diff --git a/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
index b7ffa261841b5..27ec45a67b8ec 100644
--- a/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/Hexagon/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0 = A2_tfrsi 1
- ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
; CHECK-NEXT: $r2 = A2_tfrsi 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $r1
+ ; CHECK-NEXT: liveins: $r0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1 = COPY killed renamable $r0, implicit undef $r2
; CHECK-NEXT: J2_jumpr $r31, implicit-def $pc, implicit $r1
bb.0:
successors: %bb.1
diff --git a/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
index 1aa290186e0d1..6121f365df125 100644
--- a/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/Mips/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $a0 = LUi 1
- ; CHECK-NEXT: renamable $a1 = COPY killed renamable $a0, implicit undef $a2
; CHECK-NEXT: $a2 = LUi 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $a1
+ ; CHECK-NEXT: liveins: $a0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $a1 = COPY killed renamable $a0, implicit undef $a2
; CHECK-NEXT: RetRA implicit $a1
bb.0:
successors: %bb.1
diff --git a/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
index e9874c5df566b..75280ea3a9523 100644
--- a/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/PowerPC/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x3 = LI8 1
- ; CHECK-NEXT: renamable $x4 = COPY killed renamable $x3, implicit undef $x5
; CHECK-NEXT: $x5 = LI8 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $x4
+ ; CHECK-NEXT: liveins: $x3
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x4 = COPY killed renamable $x3, implicit undef $x5
; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x4
bb.0:
successors: %bb.1
diff --git a/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir b/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
index d98e02f18e57f..18dc78c54c92c 100644
--- a/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
+++ b/llvm/test/CodeGen/RISCV/postra-machine-sink-undef-internal.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x10 = ADDI $x0, 1
- ; CHECK-NEXT: renamable $x11 = COPY killed renamable $x10, implicit undef $x12
; CHECK-NEXT: $x12 = ADDI $x0, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $x11
+ ; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = COPY killed renamable $x10, implicit undef $x12
; CHECK-NEXT: PseudoRET implicit $x11
bb.0:
successors: %bb.1
diff --git a/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir b/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
index 0b09f16a2b25c..7a59548076561 100644
--- a/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
+++ b/llvm/test/CodeGen/X86/postra-machine-sink-undef-use.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $ebx = MOV32ri 1
- ; CHECK-NEXT: renamable $eax = COPY killed renamable $ebx, implicit undef $ecx
; CHECK-NEXT: $ecx = MOV32ri 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $eax
+ ; CHECK-NEXT: liveins: $ebx
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $eax = COPY killed renamable $ebx, implicit undef $ecx
; CHECK-NEXT: RET 0, $eax
bb.0:
successors: %bb.1
@@ -40,7 +40,7 @@ body: |
; CHECK-NEXT: $edx = MOV32ri 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: liveins: $ebx, $ecx
+ ; CHECK-NEXT: liveins: $ebx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $eax = COPY killed renamable $ebx, implicit-def $ecx, implicit internal $ecx
; CHECK-NEXT: RET 0, $eax
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