[llvm] [RISC-V] Rename GPRMem operand to BasePtr. NFC (PR #204215)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 16 10:56:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Alexander Richardson (arichardson)
<details>
<summary>Changes</summary>
This is in preparation for https://github.com/llvm/llvm-project/pull/177073
where these operands can refer to either a GPR or YGPR depending on the
current HwMode. Since this is the base pointer operand of the load/store
instruction, BasePtr was chosen as the name.
---
Full diff: https://github.com/llvm/llvm-project/pull/204215.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+7-7)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td (+3-3)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+34-34)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td (+1-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index f25654de03183..3652f33b84d3a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -234,7 +234,7 @@ def GPRMemZeroOffset : MemOperand<GPR> {
let PrintMethod = "printZeroOffsetMemOp";
}
-def GPRMem : MemOperand<GPR>;
+def BasePtr : MemOperand<GPR>;
def SPMem : MemOperand<SP>;
@@ -653,7 +653,7 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
class Load_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
- : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins GPRMem:$rs1, simm12_lo:$imm12),
+ : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins BasePtr:$rs1, simm12_lo:$imm12),
opcodestr, "$rd, ${imm12}(${rs1})">;
class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
@@ -669,7 +669,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
class Store_rri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
: RVInstS<funct3, OPC_STORE, (outs),
- (ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
+ (ins rty:$rs2, BasePtr:$rs1, simm12_lo:$imm12),
opcodestr, "$rs2, ${imm12}(${rs1})">;
class HStore_rr<bits<7> funct7, string opcodestr>
@@ -2008,8 +2008,8 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT,
ValueType PtrVT = XLenVT>
- : Pat<(vt (LoadOp (AddrRegImm (PtrVT GPRMem:$rs1), simm12_lo:$imm12))),
- (Inst GPRMem:$rs1, simm12_lo:$imm12)>;
+ : Pat<(vt (LoadOp (AddrRegImm (PtrVT BasePtr:$rs1), simm12_lo:$imm12))),
+ (Inst BasePtr:$rs1, simm12_lo:$imm12)>;
def : LdPat<sextloadi8, LB>;
def : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
@@ -2023,9 +2023,9 @@ def : LdPat<zextloadi16, LHU>;
class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
ValueType vt, ValueType PtrVT = XLenVT>
- : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (PtrVT GPRMem:$rs1),
+ : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (PtrVT BasePtr:$rs1),
simm12_lo:$imm12)),
- (Inst StTy:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
+ (Inst StTy:$rs2, BasePtr:$rs1, simm12_lo:$imm12)>;
def : StPat<truncstorei8, SB, GPR, XLenVT>;
def : StPat<truncstorei16, SH, GPR, XLenVT>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 90b954b6c7072..20d062ba7c7f2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -199,7 +199,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class FPLoad_r<bits<3> funct3, string opcodestr, DAGOperand rty,
SchedWrite sw>
: RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd),
- (ins GPRMem:$rs1, simm12_lo:$imm12),
+ (ins BasePtr:$rs1, simm12_lo:$imm12),
opcodestr, "$rd, ${imm12}(${rs1})">,
Sched<[sw, ReadFMemBase]>;
@@ -207,7 +207,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class FPStore_r<bits<3> funct3, string opcodestr, DAGOperand rty,
SchedWrite sw>
: RVInstS<funct3, OPC_STORE_FP, (outs),
- (ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
+ (ins rty:$rs2, BasePtr:$rs1, simm12_lo:$imm12),
opcodestr, "$rs2, ${imm12}(${rs1})">,
Sched<[sw, ReadFStoreData, ReadFMemBase]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 8b52fc965e601..777508f345797 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -272,14 +272,14 @@ class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
- (ins GPRMem:$rs1, simm12_lo:$imm12),
+ (ins BasePtr:$rs1, simm12_lo:$imm12),
opcodestr, "$rd, (${rs1}), ${imm12}"> {
let Constraints = "$rs1_wb = $rs1";
}
class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb),
- (ins GPRMem:$rs1, GPR:$rs2),
+ (ins BasePtr:$rs1, GPR:$rs2),
opcodestr, "$rd, (${rs1}), ${rs2}"> {
let Constraints = "$rs1_wb = $rs1";
}
@@ -333,7 +333,7 @@ class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
class CVLoad_ri<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
- (ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+ (ins BasePtr:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
//===----------------------------------------------------------------------===//
// Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c00acbcb6f40c..8e44f275c903d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -435,7 +435,7 @@ def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, (${rs1})",
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
class QCILoad_ScaleIdx<bits<4> funct4, string opcodestr>
: RVInstRBase<0b111, OPC_CUSTOM_0,
- (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
+ (outs GPR:$rd), (ins BasePtr:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
opcodestr, "$rd, $rs1, $rs2, $shamt"> {
bits<3> shamt;
let Inst{31-28} = funct4;
@@ -447,7 +447,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
// rd corresponds to the source for the store 'rs3' described in the spec.
class QCIStore_ScaleIdx<bits<4> funct4, string opcodestr>
: RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
- (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
+ (ins GPR:$rd, BasePtr:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
opcodestr, "$rd, $rs1, $rs2, $shamt"> {
bits<3> shamt;
let Inst{31-28} = funct4;
@@ -757,7 +757,7 @@ class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, canFoldAsLoad = 1 in
class QCIRVInstEILoad<bits<3> funct3, bits<2> funct2, string opcodestr>
: QCIRVInstEIBase<funct3, funct2, (outs GPR:$rd),
- (ins GPRMem:$rs1, simm26:$imm), opcodestr,
+ (ins BasePtr:$rs1, simm26:$imm), opcodestr,
"$rd, ${imm}(${rs1})">;
class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
@@ -780,7 +780,7 @@ class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
: QCIRVInstESBase<funct3, funct2, (outs),
- (ins GPR:$rs2, GPRMem:$rs1, simm26:$imm),
+ (ins GPR:$rs2, BasePtr:$rs1, simm26:$imm),
opcodestr, "$rs2, ${imm}(${rs1})">;
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
@@ -1389,13 +1389,13 @@ let hasSideEffects = false, mayLoad = true, mayStore = false, Size = 4,
isCodeGenOnly = false in
class PseudoQCAccessLoad_ri<string opcodestr>
: Pseudo<(outs GPR:$rd),
- (ins GPRMem:$rs1, simm12:$imm12, qc_access_symbol:$expr), [],
+ (ins BasePtr:$rs1, simm12:$imm12, qc_access_symbol:$expr), [],
opcodestr, "$rd, ${imm12}(${rs1}), $expr">;
let hasSideEffects = false, mayLoad = false, mayStore = true, Size = 4,
isCodeGenOnly = false in
class PseudoQCAccessStore_rri<string opcodestr>
- : Pseudo<(outs), (ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12, qc_access_symbol:$expr),
+ : Pseudo<(outs), (ins GPR:$rs2, BasePtr:$rs1, simm12:$imm12, qc_access_symbol:$expr),
[], opcodestr, "$rs2, ${imm12}(${rs1}), $expr">;
@@ -1408,15 +1408,15 @@ def PseudoQCAccessLW : PseudoQCAccessLoad_ri<"lw">;
let EmitPriority = 0 in {
def : InstAlias<"lb $rd, (${rs1}), $expr",
- (PseudoQCAccessLB GPR:$rd, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessLB GPR:$rd, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"lbu $rd, (${rs1}), $expr",
- (PseudoQCAccessLB GPR:$rd, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessLB GPR:$rd, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"lh $rd, (${rs1}), $expr",
- (PseudoQCAccessLH GPR:$rd, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessLH GPR:$rd, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"lhu $rd, (${rs1}), $expr",
- (PseudoQCAccessLHU GPR:$rd, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessLHU GPR:$rd, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"lw $rd, (${rs1}), $expr",
- (PseudoQCAccessLW GPR:$rd, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessLW GPR:$rd, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
}
def PseudoQCAccessSW : PseudoQCAccessStore_rri<"sw">;
@@ -1425,11 +1425,11 @@ def PseudoQCAccessSB : PseudoQCAccessStore_rri<"sb">;
let EmitPriority = 0 in {
def : InstAlias<"sb $rs2, (${rs1}), $expr",
- (PseudoQCAccessSB GPR:$rs2, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessSB GPR:$rs2, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"sh $rs2, (${rs1}), $expr",
- (PseudoQCAccessSH GPR:$rs2, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessSH GPR:$rs2, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
def : InstAlias<"sw $rs2, (${rs1}), $expr",
- (PseudoQCAccessSW GPR:$rs2, GPRMem:$rs1, 0, qc_access_symbol:$expr)>;
+ (PseudoQCAccessSW GPR:$rs2, BasePtr:$rs1, 0, qc_access_symbol:$expr)>;
}
}
@@ -1522,12 +1522,12 @@ class QC48StPat<PatFrag StoreOp, RVInst48 Inst>
def AddrRegRegScale7 : AddrRegRegScale<7>;
class QCScaledLdPat<PatFrag LoadOp, RVInst Inst>
- : Pat<(i32 (LoadOp (AddrRegRegScale7 (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt))),
- (Inst GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
+ : Pat<(i32 (LoadOp (AddrRegRegScale7 (i32 BasePtr:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt))),
+ (Inst BasePtr:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
- : Pat<(StoreOp (i32 GPR:$rd), (AddrRegRegScale7 (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
- (Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
+ : Pat<(StoreOp (i32 GPR:$rd), (AddrRegRegScale7 (i32 BasePtr:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
+ (Inst GPR:$rd, BasePtr:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
class QCIMVCCPat<CondCode Cond, QCIMVCC Inst>
: Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
@@ -1912,27 +1912,27 @@ def : CompressPat<(QC_E_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
def : CompressPat<(QC_E_LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
(C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
-def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
- (LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
- (LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
- (LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
- (LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
- (LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_LB GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12),
+ (LB GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_LBU GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12),
+ (LBU GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_LH GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12),
+ (LH GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_LHU GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12),
+ (LHU GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_LW GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12),
+ (LW GPR:$rd, BasePtr:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
def : CompressPat<(QC_E_SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
(C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
-def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
- (SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
- (SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
-def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
- (SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_SB GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12),
+ (SB GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_SH GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12),
+ (SH GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12)>;
+def : CompressPat<(QC_E_SW GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12),
+ (SW GPR:$rs2, BasePtr:$rs1, simm12_lo:$imm12)>;
} // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32]
let Predicates = [HasVendorXqcicm, IsRV32] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index 16f59c0c03c2e..b7e844d5f77b1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -37,7 +37,7 @@ class CBO_r<bits<12> optype, string opcodestr>
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
class Prefetch_ri<bits<5> optype, string opcodestr>
- : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPRMem:$rs1, simm12_lsb00000:$imm12),
+ : RVInstS<0b110, OPC_OP_IMM, (outs), (ins BasePtr:$rs1, simm12_lsb00000:$imm12),
opcodestr, "${imm12}(${rs1})"> {
let Inst{11-7} = 0b00000;
let rs2 = optype;
``````````
</details>
https://github.com/llvm/llvm-project/pull/204215
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