[llvm] [AMDGPU][True16] NFCI. update two lit test for spill v16 (PR #203922)
Guo Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 15 08:15:30 PDT 2026
https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/203922
Follow up from https://github.com/llvm/llvm-project/pull/203589#discussion_r3406309174
>From 98abafa00dbfb838deff370c288f2eab7a5e8125 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Fri, 12 Jun 2026 13:28:37 -0400
Subject: [PATCH 1/2] insert tmp vgpr32 for scratch_load_ubyte_st in sramecc
mode
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 +-
llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll | 46 ++++++++++++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 2dd241c71a285..9700720f0373a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1939,7 +1939,8 @@ void SIRegisterInfo::buildSpillLoadStore(
}
Register FinalValueReg = ValueReg;
- if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR) {
+ if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR ||
+ LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_ST) {
// If we are loading 16-bit value with SRAMECC endabled we need a temp
// 32-bit VGPR to load and extract 16-bits into the final register.
ValueReg =
diff --git a/llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
new file mode 100644
index 0000000000000..6ece8125a1844
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -stop-after=prologepilog < %s | FileCheck %s -check-prefixes=GFX1250-TRUE16
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -stop-after=prologepilog < %s | FileCheck %s -check-prefixes=GFX1250-FAKE16
+
+define amdgpu_kernel void @spill_i16_alu() {
+ ; GFX1250-TRUE16-LABEL: name: spill_i16_alu
+ ; GFX1250-TRUE16: bb.0.entry:
+ ; GFX1250-TRUE16-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; GFX1250-TRUE16-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; GFX1250-TRUE16-NEXT: S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
+ ; GFX1250-TRUE16-NEXT: renamable $vgpr0 = SCRATCH_LOAD_USHORT_ST 0, 0, implicit $exec, implicit $flat_scr :: (volatile dereferenceable load (s16) from %ir.alloca, align 4, addrspace 5)
+ ; GFX1250-TRUE16-NEXT: renamable $vgpr0_lo16 = V_ADD_NC_U16_t16_e64 0, 123, 0, killed $vgpr0_lo16, 0, 0, implicit $exec
+ ; GFX1250-TRUE16-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed $vgpr0_lo16, 2, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, addrspace 5)
+ ; GFX1250-TRUE16-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $vgpr0, clobber, implicit-def dead early-clobber $vgpr1, clobber, implicit-def dead early-clobber $vgpr2, clobber, implicit-def dead early-clobber $vgpr3, clobber, implicit-def dead early-clobber $vgpr4, clobber, implicit-def dead early-clobber $vgpr5, clobber, implicit-def dead early-clobber $vgpr6, clobber, implicit-def dead early-clobber $vgpr7
+ ; GFX1250-TRUE16-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_ST 2, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" "amdgpu-thread-private" load (s16) from %stack.1, addrspace 5)
+ ; GFX1250-TRUE16-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec
+ ; GFX1250-TRUE16-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed renamable $vgpr0_lo16, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store (s16) into %ir.alloca, align 4, addrspace 5)
+ ; GFX1250-TRUE16-NEXT: S_ENDPGM 0
+ ;
+ ; GFX1250-FAKE16-LABEL: name: spill_i16_alu
+ ; GFX1250-FAKE16: bb.0.entry:
+ ; GFX1250-FAKE16-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; GFX1250-FAKE16-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; GFX1250-FAKE16-NEXT: S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
+ ; GFX1250-FAKE16-NEXT: renamable $vgpr0 = SCRATCH_LOAD_USHORT_ST 0, 0, implicit $exec, implicit $flat_scr :: (volatile dereferenceable load (s16) from %ir.alloca, align 4, addrspace 5)
+ ; GFX1250-FAKE16-NEXT: renamable $vgpr0 = V_ADD_NC_U16_fake16_e64 0, 123, 0, killed $vgpr0, 0, 0, implicit $exec
+ ; GFX1250-FAKE16-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr0, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5)
+ ; GFX1250-FAKE16-NEXT: INLINEASM &"", sideeffect attdialect, clobber, implicit-def dead early-clobber $vgpr0, clobber, implicit-def dead early-clobber $vgpr1, clobber, implicit-def dead early-clobber $vgpr2, clobber, implicit-def dead early-clobber $vgpr3, clobber, implicit-def dead early-clobber $vgpr4, clobber, implicit-def dead early-clobber $vgpr5, clobber, implicit-def dead early-clobber $vgpr6, clobber, implicit-def dead early-clobber $vgpr7
+ ; GFX1250-FAKE16-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_ST 4, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" "amdgpu-thread-private" load (s32) from %stack.1, addrspace 5)
+ ; GFX1250-FAKE16-NEXT: SCRATCH_STORE_SHORT_ST killed renamable $vgpr0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store (s16) into %ir.alloca, align 4, addrspace 5)
+ ; GFX1250-FAKE16-NEXT: S_ENDPGM 0
+entry:
+ %alloca = alloca i16, i32 1, align 4, addrspace(5)
+
+ %aptr = getelementptr i16, ptr addrspace(5) %alloca, i32 0
+ %a = load volatile i16, ptr addrspace(5) %aptr
+ %add = add i16 %a, 123
+
+ ; Force %a to spill.
+ call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
+
+ %outptr = getelementptr i16, ptr addrspace(5) %alloca, i32 0
+ store volatile i16 %add, ptr addrspace(5) %outptr
+
+ ret void
+}
>From 33322e23c29ef610c21fb6988b568645a59a7db5 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Mon, 15 Jun 2026 11:13:54 -0400
Subject: [PATCH 2/2] update two tests
---
llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir | 48 +++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
diff --git a/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
new file mode 100644
index 0000000000000..6d70a2d057d62
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
+
+--- |
+ define amdgpu_kernel void @spill_i16_alu() #0 {
+ ret void
+ }
+
+ attributes #0 = { nounwind }
+...
+---
+name: spill_i16_alu
+tracksRegLiveness: true
+noVRegs: true
+machineFunctionInfo:
+ stackPtrOffsetReg: $sgpr32
+ isEntryFunction: true
+stack:
+ - { id: 0, type: default, offset: 0, size: 4, alignment: 4}
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 4}
+body: |
+ bb.0 (%ir-block.0):
+ ; EXPANDED-LABEL: name: spill_i16_alu
+ ; EXPANDED: $vgpr0 = SCRATCH_LOAD_USHORT_ST 0, 0, implicit $exec, implicit $flat_scr :: (volatile dereferenceable load (s16) from %stack.0, align 4, addrspace 5)
+ ; EXPANDED-NEXT: $vgpr0_lo16 = V_ADD_NC_U16_t16_e64 0, 123, 0, killed $vgpr0_lo16, 0, 0, implicit $exec
+ ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed $vgpr0_lo16, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5)
+ ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_ST_t16 4, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" "amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5)
+ ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed renamable $vgpr0_lo16, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store (s16) into %stack.0, align 4, addrspace 5)
+ ; EXPANDED-NEXT: S_ENDPGM 0
+ ;
+ ; SRAMECC-EXPANDED-LABEL: name: spill_i16_alu
+ ; SRAMECC-EXPANDED: S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
+ ; SRAMECC-EXPANDED-NEXT: $vgpr0 = SCRATCH_LOAD_USHORT_ST 0, 0, implicit $exec, implicit $flat_scr :: (volatile dereferenceable load (s16) from %stack.0, align 4, addrspace 5)
+ ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_ADD_NC_U16_t16_e64 0, 123, 0, killed $vgpr0_lo16, 0, 0, implicit $exec
+ ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed $vgpr0_lo16, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5)
+ ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_ST 4, 3, implicit $exec, implicit $flat_scr :: ("amdgpu-last-use" "amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5)
+ ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec
+ ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_ST_t16 killed renamable $vgpr0_lo16, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store (s16) into %stack.0, align 4, addrspace 5)
+ ; SRAMECC-EXPANDED-NEXT: S_ENDPGM 0
+ $vgpr0 = SCRATCH_LOAD_USHORT_SADDR %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile dereferenceable load (s16) from %stack.0, align 4, addrspace 5)
+ $vgpr0_lo16 = V_ADD_NC_U16_t16_e64 0, 123, 0, killed $vgpr0_lo16, 0, 0, implicit $exec
+ SI_SPILL_V16_SAVE killed $vgpr0_lo16, %stack.1, $sgpr32, 0, implicit $exec :: (store (s16) into %stack.1, addrspace 5)
+
+ $vgpr0_lo16 = SI_SPILL_V16_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s16) from %stack.1, addrspace 5)
+ SCRATCH_STORE_SHORT_SADDR_t16 killed renamable $vgpr0_lo16, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store (s16) into %stack.0, align 4, addrspace 5)
+ S_ENDPGM 0
+...
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