[llvm] [MC][TableGen] Pack MCInstrDesc fields into 24 bytes (PR #202647)
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llvm-commits at lists.llvm.org
Mon Jun 15 07:27:50 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: David Zbarsky (dzbarsky)
<details>
<summary>Changes</summary>
Pack the generated `MCInstrDesc` fields after `TSFlags` into two `uint64_t` allocation units, reducing `sizeof(MCInstrDesc)` from 32 to 24 bytes. `NumOperands` uses eight bits, `NumDefs` is derived from a tagged five-bit definition or non-definition count, and instruction sizes below 64 are stored directly while larger multiples of four are supported through 316. TableGen checks every generated range, static assertions check the flag count, operand-info extent, and layout, and the packed fields are private behind accessors.
The 24-byte layout removes 891,632 B of `MCInstrDesc` payload from the measured arm64 release multicall and 82,576 B from `llvm-mca`.
Work towards #<!-- -->202616
AI tool disclosure: Co-authored with OpenAI Codex.
---
Patch is 36.34 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/202647.diff
29 Files Affected:
- (modified) bolt/lib/Core/MCPlusBuilder.cpp (+1-1)
- (modified) bolt/lib/Target/X86/X86MCPlusBuilder.cpp (+5-3)
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+63-15)
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+4-4)
- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (+1-1)
- (modified) llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp (+1-1)
- (modified) llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp (+2-3)
- (modified) llvm/lib/MC/MCInstrDesc.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+4-4)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+3-3)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+3-3)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (+2-2)
- (modified) llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (+1-1)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp (+2-2)
- (modified) llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp (+3-2)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (+1-1)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+1-1)
- (added) llvm/test/TableGen/InstrInfoEmitterErrors.td (+20)
- (modified) llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp (+1-1)
- (modified) llvm/tools/llvm-exegesis/lib/X86/Target.cpp (+6-6)
- (modified) llvm/unittests/CodeGen/LexicalScopesTest.cpp (+11-13)
- (modified) llvm/unittests/MC/CMakeLists.txt (+1-1)
- (added) llvm/unittests/MC/MCInstrDescTest.cpp (+45)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+35-4)
``````````diff
diff --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp
index 0cb4ba1ebfbd7..fef918924e9b3 100644
--- a/bolt/lib/Core/MCPlusBuilder.cpp
+++ b/bolt/lib/Core/MCPlusBuilder.cpp
@@ -546,7 +546,7 @@ bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
- for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
+ for (unsigned I = InstInfo.getNumDefs(); I < InstInfo.getNumOperands(); ++I)
if (MI.getOperand(I).isReg() && MI.getOperand(I).getReg() &&
RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
return true;
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
index 923de64be58c8..6b216590aac13 100644
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -105,7 +105,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
unsigned getCondCode(const MCInst &Inst) const override {
unsigned Opcode = Inst.getOpcode();
if (X86::isJCC(Opcode))
- return Inst.getOperand(Info->get(Opcode).NumOperands - 1).getImm();
+ return Inst.getOperand(Info->get(Opcode).getNumOperands() - 1).getImm();
return X86::COND_INVALID;
}
@@ -2810,7 +2810,8 @@ class X86MCPlusBuilder : public MCPlusBuilder {
MCContext *Ctx) const override {
unsigned InvCC = getInvertedCondCode(getCondCode(Inst));
assert(InvCC != X86::COND_INVALID && "invalid branch instruction");
- Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC);
+ Inst.getOperand(Info->get(Inst.getOpcode()).getNumOperands() - 1)
+ .setImm(InvCC);
Inst.getOperand(0) =
MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
}
@@ -2819,7 +2820,8 @@ class X86MCPlusBuilder : public MCPlusBuilder {
unsigned CC) const override {
if (CC == X86::COND_INVALID)
return false;
- Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC);
+ Inst.getOperand(Info->get(Inst.getOpcode()).getNumOperands() - 1)
+ .setImm(CC);
Inst.getOperand(0) =
MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
return true;
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index da65487ce9c65..5bef4c1507a5e 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -188,6 +188,7 @@ enum Flag {
Trap,
VariadicOpsAreDefs,
Authenticated,
+ NumFlags,
};
} // namespace MCID
@@ -203,23 +204,56 @@ class MCInstrDesc {
// the <Target>Insts table because they rely on knowing their own address to
// find other information elsewhere in the same table.
- uint32_t Opcode; // The opcode number.
- uint16_t NumOperands; // Num of args (may be more if variable_ops)
- uint8_t NumDefs; // Num of args that are definitions
- uint8_t Size; // Number of bytes in encoding.
- uint16_t SchedClass; // enum identifying instr sched class
- uint8_t NumImplicitUses; // Num of regs implicitly used
- uint8_t NumImplicitDefs; // Num of regs implicitly defined
- uint16_t OpInfoOffset; // Offset to info about operands
- uint16_t ImplicitOffset; // Offset to start of implicit op list
- uint64_t Flags; // Flags identifying machine instr class
- uint64_t TSFlags; // Target Specific Flag values
+ uint64_t TSFlags; // Target-specific flag values.
+
+private:
+ static constexpr unsigned NumNonDefsFlag = 1U << 5;
+ static constexpr unsigned NumDefsCountMask = NumNonDefsFlag - 1;
+
+ static constexpr unsigned encodeNumDefs(unsigned NumOperands,
+ unsigned NumDefs) {
+ unsigned NumNonDefs = NumOperands - NumDefs;
+ return NumDefs <= NumNonDefs ? NumDefs : (NumNonDefsFlag | NumNonDefs);
+ }
+
+ // Store sizes below 64 directly and larger sizes in four-byte units.
+ static constexpr unsigned encodeSize(unsigned Size) {
+ return Size < 64 ? Size : 64 + (Size - 64) / 4;
+ }
+
+ uint64_t Flags : 41; // Flags identifying machine instruction classes.
+ uint64_t Opcode : 16; // The opcode number.
+ uint64_t EncodedSize : 7; // The encoded instruction size.
+
+ uint64_t NumOperands : 8;
+ // Store the smaller of the definition and non-definition counts. Bit 5 is
+ // set when bits 0 through 4 contain the non-definition count.
+ uint64_t EncodedNumDefs : 6;
+ uint64_t SchedClass : 13; // enum identifying instr sched class
+ uint64_t NumImplicitUses : 6; // Num of regs implicitly used
+ uint64_t NumImplicitDefs : 6; // Num of regs implicitly defined
+ uint64_t OpInfoOffset : 15; // Offset to info about operands
+ uint64_t ImplicitOffset : 10; // Offset to start of implicit op list
+
+public:
+ constexpr MCInstrDesc(uint32_t Opcode = 0, uint16_t NumOperands = 0,
+ uint8_t NumDefs = 0, uint16_t Size = 0,
+ uint16_t SchedClass = 0, uint8_t NumImplicitUses = 0,
+ uint8_t NumImplicitDefs = 0, uint16_t OpInfoOffset = 0,
+ uint16_t ImplicitOffset = 0, uint64_t Flags = 0,
+ uint64_t TSFlags = 0)
+ : TSFlags(TSFlags), Flags(Flags), Opcode(Opcode),
+ EncodedSize(encodeSize(Size)), NumOperands(NumOperands),
+ EncodedNumDefs(encodeNumDefs(NumOperands, NumDefs)),
+ SchedClass(SchedClass), NumImplicitUses(NumImplicitUses),
+ NumImplicitDefs(NumImplicitDefs), OpInfoOffset(OpInfoOffset),
+ ImplicitOffset(ImplicitOffset) {}
/// Returns the value of the specified operand constraint if
/// it is present. Returns -1 if it is not present.
int getOperandConstraint(unsigned OpNum,
MCOI::OperandConstraint Constraint) const {
- if (OpNum < NumOperands &&
+ if (OpNum < getNumOperands() &&
(operands()[OpNum].Constraints & (1 << Constraint))) {
unsigned ValuePos = 4 + Constraint * 4;
return (int)(operands()[OpNum].Constraints >> ValuePos) & 0x0f;
@@ -239,14 +273,23 @@ class MCInstrDesc {
ArrayRef<MCOperandInfo> operands() const {
auto OpInfo = reinterpret_cast<const MCOperandInfo *>(this + Opcode + 1);
- return ArrayRef(OpInfo + OpInfoOffset, NumOperands);
+ return ArrayRef(OpInfo + OpInfoOffset, getNumOperands());
}
/// Return the number of MachineOperands that are register
/// definitions. Register definitions always occur at the start of the
/// machine operand list. This is the number of "outs" in the .td file,
/// and does not include implicit defs.
- unsigned getNumDefs() const { return NumDefs; }
+ unsigned getNumDefs() const {
+ unsigned Count = EncodedNumDefs & NumDefsCountMask;
+ return EncodedNumDefs & NumNonDefsFlag ? NumOperands - Count : Count;
+ }
+
+ /// Return the number of implicitly used registers.
+ unsigned getNumImplicitUses() const { return NumImplicitUses; }
+
+ /// Return the number of implicitly defined registers.
+ unsigned getNumImplicitDefs() const { return NumImplicitDefs; }
/// Return flags of this instruction.
uint64_t getFlags() const { return Flags; }
@@ -604,7 +647,9 @@ class MCInstrDesc {
/// Return the number of bytes in the encoding of this instruction,
/// or zero if the encoding size cannot be known from the opcode.
- unsigned getSize() const { return Size; }
+ unsigned getSize() const {
+ return EncodedSize < 64 ? EncodedSize : 64 + (EncodedSize - 64) * 4;
+ }
/// Find the index of the first operand in the
/// operand list that is used to represent the predicate. It returns -1 if
@@ -629,6 +674,9 @@ class MCInstrDesc {
const MCRegisterInfo &RI) const;
};
+static_assert(MCID::NumFlags <= 41);
+static_assert(sizeof(MCInstrDesc) == 24);
+
} // end namespace llvm
#endif
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 374c92241b9fb..32f1ffb8eee42 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -100,7 +100,7 @@ void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
DebugLoc DL, bool NoImp)
: MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
- Opcode(TID.Opcode), DebugInstrNum(0), DbgLoc(std::move(DL)) {
+ Opcode(TID.getOpcode()), DebugInstrNum(0), DbgLoc(std::move(DL)) {
// Reserve space for the expected number of operands.
if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
MCID->implicit_uses().size()) {
@@ -142,7 +142,7 @@ void MachineInstr::setDesc(const MCInstrDesc &TID) {
if (getParent())
getMF()->handleChangeDesc(*this, TID);
MCID = &TID;
- Opcode = TID.Opcode;
+ Opcode = TID.getOpcode();
}
void MachineInstr::moveBefore(MachineInstr *MovePos) {
@@ -1719,7 +1719,7 @@ void MachineInstr::copyImplicitOps(MachineFunction &MF,
bool MachineInstr::hasComplexRegisterTies() const {
const MCInstrDesc &MCID = getDesc();
- if (MCID.Opcode == TargetOpcode::STATEPOINT)
+ if (MCID.getOpcode() == TargetOpcode::STATEPOINT)
return true;
for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
const auto &Operand = getOperand(I);
@@ -2396,7 +2396,7 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
"Expected inlined-at fields to agree");
- if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
+ if (MCID.getOpcode() == TargetOpcode::DBG_VALUE) {
assert(DebugOps.size() == 1 &&
"DBG_VALUE must contain exactly one debug operand");
MachineOperand DebugOp = DebugOps[0];
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index c611b837a86b4..876ea5053a53f 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2607,7 +2607,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
- // The first MCID.NumDefs operands must be explicit register defines
+ // The first NumDefs operands must be explicit register definitions.
if (MONum < NumDefs) {
const MCOperandInfo &MCOI = MCID.operands()[MONum];
if (!MO->isReg())
diff --git a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
index 209c6d81f6020..5bb9a28e7760c 100644
--- a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
+++ b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
@@ -176,7 +176,7 @@ void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
// in the scoreboard at the appropriate future cycles.
const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
assert(MCID && "The scheduler must filter non-machineinstrs");
- if (DAG->TII->isZeroCost(MCID->Opcode))
+ if (DAG->TII->isZeroCost(MCID->getOpcode()))
return;
++IssueCount;
diff --git a/llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp b/llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
index 24ae7c21098f9..09479c7e3e25b 100644
--- a/llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
+++ b/llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
@@ -135,9 +135,8 @@ void DWARFCFIAnalysis::update(const MCInst &Inst,
State.update(Directive);
SmallSet<DWARFRegNum, 4> Writes;
- for (unsigned I = 0; I < MCInstInfo.NumImplicitDefs; I++)
- Writes.insert(MCRI->getDwarfRegNum(
- getSuperReg(MCRI, MCInstInfo.implicit_defs()[I]), IsEH));
+ for (MCPhysReg Reg : MCInstInfo.implicit_defs())
+ Writes.insert(MCRI->getDwarfRegNum(getSuperReg(MCRI, Reg), IsEH));
for (unsigned I = 0; I < Inst.getNumOperands(); I++) {
auto &&Op = Inst.getOperand(I);
diff --git a/llvm/lib/MC/MCInstrDesc.cpp b/llvm/lib/MC/MCInstrDesc.cpp
index 99cdb44168ec6..d6f8e61308a82 100644
--- a/llvm/lib/MC/MCInstrDesc.cpp
+++ b/llvm/lib/MC/MCInstrDesc.cpp
@@ -39,12 +39,12 @@ bool MCInstrDesc::hasImplicitDefOfPhysReg(MCRegister Reg,
bool MCInstrDesc::hasExplicitDefOfPhysReg(const MCInst &MI, MCRegister Reg,
const MCRegisterInfo &RI) const {
- for (int i = 0, e = NumDefs; i != e; ++i)
+ for (int i = 0, e = getNumDefs(); i != e; ++i)
if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
return true;
if (variadicOpsAreDefs())
- for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
+ for (int i = getNumOperands() - 1, e = MI.getNumOperands(); i != e; ++i)
if (MI.getOperand(i).isReg() &&
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
return true;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 2a9a31e732a6e..e2c3919da7370 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1388,7 +1388,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
/// Get size of register operand
unsigned getRegOperandSize(const MCInstrDesc &Desc, unsigned OpNo) const {
- assert(OpNo < Desc.NumOperands);
+ assert(OpNo < Desc.getNumOperands());
int16_t RCID = MII.getOpRegClassID(Desc.operands()[OpNo], HwMode);
return getRegBitWidth(RCID) / 8;
}
@@ -9497,7 +9497,7 @@ static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
// 1. This operand is input modifiers
Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
// 2. This is not last operand
- && Desc.NumOperands > (OpNum + 1)
+ && Desc.getNumOperands() > (OpNum + 1)
// 3. Next operand is register class
&& Desc.operands()[OpNum + 1].RegClass != -1
// 4. Next register is not tied to any other operand
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ef9d184555bd6..d8095259bb45f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -257,8 +257,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
// getNamedOperandIdx returns the index for MachineInstrs. Since they
// include the output in the operand list, but SDNodes don't, we need to
// subtract the index by one.
- Offset0Idx -= get(Opc0).NumDefs;
- Offset1Idx -= get(Opc1).NumDefs;
+ Offset0Idx -= get(Opc0).getNumDefs();
+ Offset1Idx -= get(Opc1).getNumDefs();
Offset0 = Load0->getConstantOperandVal(Offset0Idx);
Offset1 = Load1->getConstantOperandVal(Offset1Idx);
return true;
@@ -314,8 +314,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
// getNamedOperandIdx returns the index for MachineInstrs. Since they
// include the output in the operand list, but SDNodes don't, we need to
// subtract the index by one.
- OffIdx0 -= get(Opc0).NumDefs;
- OffIdx1 -= get(Opc1).NumDefs;
+ OffIdx0 -= get(Opc0).getNumDefs();
+ OffIdx1 -= get(Opc1).getNumDefs();
SDValue Off0 = Load0->getOperand(OffIdx0);
SDValue Off1 = Load1->getOperand(OffIdx1);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 831aa9ebb8435..cdf0853a43491 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1316,8 +1316,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const MachineOperand &UseMO,
const MachineOperand &DefMO) const {
assert(UseMO.getParent() == &MI);
- int OpIdx = UseMO.getOperandNo();
- if (OpIdx >= MI.getDesc().NumOperands)
+ unsigned OpIdx = UseMO.getOperandNo();
+ if (OpIdx >= MI.getDesc().getNumOperands())
return false;
return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
@@ -1332,7 +1332,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
int64_t ImmVal) const {
- if (OpIdx >= MI.getDesc().NumOperands)
+ if (OpIdx >= MI.getDesc().getNumOperands())
return false;
if (isCopyInstr(MI)) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 33df51e8a7e07..e8915d1f331ef 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2868,14 +2868,14 @@ bool isInlineValue(MCRegister Reg) {
#undef MAP_REG2REG
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) {
- assert(OpNo < Desc.NumOperands);
+ assert(OpNo < Desc.getNumOperands());
unsigned OpType = Desc.operands()[OpNo].OperandType;
return OpType >= AMDGPU::OPERAND_KIMM_FIRST &&
OpType <= AMDGPU::OPERAND_KIMM_LAST;
}
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
- assert(OpNo < Desc.NumOperands);
+ assert(OpNo < Desc.getNumOperands());
unsigned OpType = Desc.operands()[OpNo].OperandType;
switch (OpType) {
case AMDGPU::OPERAND_REG_IMM_FP32:
@@ -2898,7 +2898,7 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
}
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
- assert(OpNo < Desc.NumOperands);
+ assert(OpNo < Desc.getNumOperands());
unsigned OpType = Desc.operands()[OpNo].OperandType;
return (OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST) ||
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3b1b8673e56a0..2a7573e9ff5fa 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4282,7 +4282,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
- if (isZeroCost(DefMCID.Opcode))
+ if (isZeroCost(DefMCID.getOpcode()))
return 0;
if (!ItinData || ItinData->isEmpty())
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index a4ac7f61713e0..860dd924a3a20 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -7636,7 +7636,7 @@ bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
}
static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
- for (unsigned i = 0; i < MCID.NumOperands; ++i) {
+ for (unsigned i = 0; i < MCID.getNumOperands(); ++i) {
if (ARM::isVpred(MCID.operands()[i].OperandType))
return i;
}
@@ -11199,11 +11199,11 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
assert(MCID.hasOptionalDef() &&
"optionally flag setting instruction missing optional def operand");
- assert(MCID.NumOperands == Inst.getNumOperands() &&
+ assert(MCID.getNumOperands() == Inst.getNumOperands() &&
"operand count mismatch!");
bool IsCPSR = false;
// Check if the instruction has CPSR set.
- for (unsigned OpNo = 0; OpNo < MCID.NumOperands; ++OpNo) {
+ for (unsigned OpNo = 0; OpNo < MCID.getNumOperands(); ++OpNo) {
if (MCID.operands()[OpNo].isOptionalDef() &&
Inst.getOperand(OpNo).isReg() &&
Inst.getOperand(OpNo).getReg() == ARM::CPSR)
@@ -11290,7 +11290,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
break;
}
- for (unsigned I = 0; I < MCID.NumOperands; ++I)
+ for (unsigned I = 0; I < MCID.getNumOperands(); ++I)
if (MCID.operands()[I].RegClass == ARM::rGPRRegClassID) {
// rGPRRegClass excludes PC, and also excluded SP before ARMv8
const auto &Op = Inst.getOperand(I);
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 2fa07ee611d49..45dd019a37f67 10...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/202647
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