[llvm] [SPIR-V] Take ArrayRef instead of owning containers in selection helpers (NFC) (PR #203908)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 15 06:48:33 PDT 2026
https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/203908
Avoid per call heap allocations where call sites pass braced list temporaries
>From 8c4a56df6ef81772bfb6ee3c0fb9e47065084c8d Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 15 Jun 2026 15:46:18 +0200
Subject: [PATCH] [SPIR-V] Take ArrayRef instead of owning containers in
selection helpers (NFC)
Avoid per call heap allocations where call sites pass braced list temporaries
---
llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp | 8 +++-----
llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h | 8 ++++----
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 2 +-
llvm/lib/Target/SPIRV/SPIRVCommandLine.h | 3 ++-
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 6 +++---
llvm/lib/Target/SPIRV/SPIRVUtils.cpp | 12 +++++-------
llvm/lib/Target/SPIRV/SPIRVUtils.h | 12 ++++--------
7 files changed, 22 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp b/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
index c774b873b95a5..e4af82b11e7d8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
@@ -334,11 +334,9 @@ Register SPIRVCombinerHelper::computeDotProduct(Register RowA, Register ColB,
return DotRes;
}
-SmallVector<Register, 16>
-SPIRVCombinerHelper::computeDotProducts(const SmallVector<Register, 4> &RowsA,
- const SmallVector<Register, 4> &ColsB,
- SPIRVTypeInst SpvVecType,
- SPIRVGlobalRegistry *GR) const {
+SmallVector<Register, 16> SPIRVCombinerHelper::computeDotProducts(
+ ArrayRef<Register> RowsA, ArrayRef<Register> ColsB,
+ SPIRVTypeInst SpvVecType, SPIRVGlobalRegistry *GR) const {
SmallVector<Register, 16> ResultScalars;
for (uint32_t J = 0; J < ColsB.size(); ++J) {
for (uint32_t I = 0; I < RowsA.size(); ++I) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h b/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
index ea70c83c2a531..19e2a6901b8f0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
+++ b/llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h
@@ -48,10 +48,10 @@ class SPIRVCombinerHelper : public CombinerHelper {
uint32_t NumCols,
SPIRVTypeInst SpvRowType,
SPIRVGlobalRegistry *GR) const;
- SmallVector<Register, 16>
- computeDotProducts(const SmallVector<Register, 4> &RowsA,
- const SmallVector<Register, 4> &ColsB,
- SPIRVTypeInst SpvVecType, SPIRVGlobalRegistry *GR) const;
+ SmallVector<Register, 16> computeDotProducts(ArrayRef<Register> RowsA,
+ ArrayRef<Register> ColsB,
+ SPIRVTypeInst SpvVecType,
+ SPIRVGlobalRegistry *GR) const;
Register computeDotProduct(Register RowA, Register ColB,
SPIRVTypeInst SpvVecType,
SPIRVGlobalRegistry *GR) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index e39332be50163..057b1c3c6a466 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -236,7 +236,7 @@ bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
}
StringRef
-SPIRVExtensionsParser::checkExtensions(const std::vector<std::string> &ExtNames,
+SPIRVExtensionsParser::checkExtensions(ArrayRef<std::string> ExtNames,
ExtensionSet &AllowedExtensions) {
for (const auto &Ext : ExtNames) {
if (Ext == "all") {
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.h b/llvm/lib/Target/SPIRV/SPIRVCommandLine.h
index 90556bab6aad5..c7ef24b6625a3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.h
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.h
@@ -19,6 +19,7 @@
#include <string>
namespace llvm {
+template <typename T> class ArrayRef;
class StringRef;
class Triple;
@@ -37,7 +38,7 @@ struct SPIRVExtensionsParser : public cl::parser<ExtensionSet> {
///
/// \return Returns a reference to the unknown SPIR-V extension name from the
/// list if present, or an empty StringRef on success.
- static StringRef checkExtensions(const std::vector<std::string> &ExtNames,
+ static StringRef checkExtensions(ArrayRef<std::string> ExtNames,
ExtensionSet &AllowedExtensions);
/// Returns the list of extensions that are valid for a particular
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 8fbde6f08c7c3..b6fc4ad8e1fb4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -149,7 +149,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
const MachineInstr *Init = nullptr) const;
bool selectOpWithSrcs(Register ResVReg, SPIRVTypeInst ResType,
- MachineInstr &I, std::vector<Register> SrcRegs,
+ MachineInstr &I, ArrayRef<Register> SrcRegs,
unsigned Opcode) const;
bool selectUnOp(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
@@ -1608,7 +1608,7 @@ bool SPIRVInstructionSelector::selectSincos(Register ResVReg,
bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
SPIRVTypeInst ResType,
MachineInstr &I,
- std::vector<Register> Srcs,
+ ArrayRef<Register> Srcs,
unsigned Opcode) const {
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
.addDef(ResVReg)
@@ -3836,7 +3836,7 @@ bool SPIRVInstructionSelector::handle64BitOverflow(
}
// Join all the resulting registers back into the return type in order
// (ie i32x2, i32x2, i32x1 -> i32x5)
- return selectOpWithSrcs(ResVReg, ResType, I, std::move(PartialRegs),
+ return selectOpWithSrcs(ResVReg, ResType, I, PartialRegs,
SPIRV::OpCompositeConstruct);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
index 2b48986826b6a..e7eed8d53acd2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
@@ -241,7 +241,7 @@ void buildOpName(Register Target, const StringRef &Name, MachineInstr &I,
}
static void finishBuildOpDecorate(MachineInstrBuilder &MIB,
- const std::vector<uint32_t> &DecArgs,
+ ArrayRef<uint32_t> DecArgs,
StringRef StrImm) {
if (!StrImm.empty())
addStringImm(StrImm, MIB);
@@ -251,7 +251,7 @@ static void finishBuildOpDecorate(MachineInstrBuilder &MIB,
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
SPIRV::Decoration::Decoration Dec,
- const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm) {
auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate)
.addUse(Reg)
.addImm(static_cast<uint32_t>(Dec));
@@ -260,7 +260,7 @@ void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
SPIRV::Decoration::Decoration Dec,
- const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm) {
MachineBasicBlock &MBB = *I.getParent();
auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpDecorate))
.addUse(Reg)
@@ -270,8 +270,7 @@ void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
SPIRV::Decoration::Decoration Dec, uint32_t Member,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm) {
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm) {
auto MIB = MIRBuilder.buildInstr(SPIRV::OpMemberDecorate)
.addUse(Reg)
.addImm(Member)
@@ -282,8 +281,7 @@ void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
void buildOpMemberDecorate(Register Reg, MachineInstr &I,
const SPIRVInstrInfo &TII,
SPIRV::Decoration::Decoration Dec, uint32_t Member,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm) {
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm) {
MachineBasicBlock &MBB = *I.getParent();
auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemberDecorate))
.addUse(Reg)
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h
index 0d3a920580043..6e9254457a0b9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.h
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h
@@ -200,23 +200,19 @@ void buildOpName(Register Target, const StringRef &Name, MachineInstr &I,
// Add an OpDecorate instruction for the given Reg.
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
SPIRV::Decoration::Decoration Dec,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm = "");
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
SPIRV::Decoration::Decoration Dec,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm = "");
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
// Add an OpDecorate instruction for the given Reg.
void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
SPIRV::Decoration::Decoration Dec, uint32_t Member,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm = "");
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
void buildOpMemberDecorate(Register Reg, MachineInstr &I,
const SPIRVInstrInfo &TII,
SPIRV::Decoration::Decoration Dec, uint32_t Member,
- const std::vector<uint32_t> &DecArgs,
- StringRef StrImm = "");
+ ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
// Add an OpDecorate instruction by "spirv.Decorations" metadata node.
void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder,
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