[llvm] [SPIR-V] Fix correction shift for i8 bitreverse in shader mode (PR #203829)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-spir-v

Author: Arseniy Obolenskiy (aobolensk)

<details>
<summary>Changes</summary>

selectBitreverse16 hardcoded the post-reverse shift to 16, but it also handles i8, where the reversed bits land in [31:24] and a shift of 16 truncated to always 0

Compute the shift as `32 - bitwidth` instead

---
Full diff: https://github.com/llvm/llvm-project/pull/203829.diff


2 Files Affected:

- (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+3-1) 
- (modified) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll (+2-1) 


``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 8fbde6f08c7c3..12d450fd9742a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -3723,7 +3723,9 @@ bool SPIRVInstructionSelector::selectBitreverse16(Register ResVReg,
                                                   MachineInstr &I,
                                                   Register Op) const {
   SPIRVTypeInst Int32Type = GR.getOrCreateSPIRVIntegerType(32, I, TII);
-  Register ShiftConst = GR.getOrCreateConstInt(16, I, Int32Type, TII);
+  const unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
+  Register ShiftConst =
+      GR.getOrCreateConstInt(32 - BitWidth, I, Int32Type, TII);
   unsigned ShiftOp = SPIRV::OpShiftRightLogicalS;
 
   const unsigned N = GR.getScalarOrVectorComponentCount(ResType);
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
index 28576c3c57dc5..fd124c5a47d20 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
@@ -14,6 +14,7 @@
 ;CHECK-DAG: %[[#vec_int_64x4:]] = OpTypeVector %[[#int_64]] 4
 ;CHECK-DAG: %[[#vec_int_16:]] = OpTypeVector %[[#int_16]] 2
 
+;CHECK-DAG: %[[#const_24:]] = OpConstant %[[#int_32]] 24
 ;CHECK-DAG: %[[#const_16:]] = OpConstant %[[#int_32]] 16
 ;CHECK-DAG: %[[#const_two:]] = OpConstant %[[#int_64]] 2
 ;CHECK-DAG: %[[#composite:]] = OpConstantComposite %[[#vec_int_32]] %[[#const_16]] %[[#const_16]] 
@@ -33,7 +34,7 @@ entry:
 ; CHECK: %[[#param:]] = OpFunctionParameter %[[#int_8]]
 ; CHECK: %[[#conversion:]] = OpUConvert %[[#int_32]] %[[#param]]
 ; CHECK-NEXT: %[[#bitrev:]] = OpBitReverse %[[#int_32]] %[[#conversion]]
-; CHECK-NEXT: %[[#shift:]] = OpShiftRightLogical %[[#int_32]] %[[#bitrev]] %[[#const_16]]
+; CHECK-NEXT: %[[#shift:]] = OpShiftRightLogical %[[#int_32]] %[[#bitrev]] %[[#const_24]]
 ; CHECK-NEXT: %[[#]] = OpUConvert %[[#int_8]] %[[#shift]]
   %elt.bitreverse = call i8 @llvm.bitreverse.i8(i8 %a)
   ret i8 %elt.bitreverse

``````````

</details>


https://github.com/llvm/llvm-project/pull/203829