[llvm] [X86][SSE] Improve ISD::FP_TO_*INT_SAT vector lowering (PR #199416)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 14 06:51:59 PDT 2026
https://github.com/Panadulek updated https://github.com/llvm/llvm-project/pull/199416
>From 4f78e44a063df6c71b7e414c74aac2761fc4627e Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 24 May 2026 03:20:27 +0200
Subject: [PATCH 01/11] Fix #51923
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5e2a4888f4ddc..404f9e4045afd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -319,6 +319,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
}
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v4i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v4i32, Custom);
}
if (Subtarget.hasAVX10_2()) {
for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v32i8}) {
@@ -22874,7 +22876,22 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
dl, VecI16VT, Src);
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
}
+ else if(DstVT == MVT::v4i32 && Subtarget.hasSSE2())
+ {
+ const bool isSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
+ SDValue src = Op.getOperand(0);
+ EVT SrcVT = Src.getValueType();
+ SDLoc dl(Op);
+ double MaxVal = IsSigned ? 2147483520.0 : 4294967040.0;
+ double MinVal = IsSigned ? -2147483648.0 : 0.0;
+ SDValue MaxC = DAG.getConstantFP(MaxVal, dl, SrcVT);
+ SDValue MinC = DAG.getConstantFP(MinVal, dl, SrcVT);
+ SDValue ClampedBottom = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, MinC);
+ SDValue ClampedTop = DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
+ unsigned CastOpc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
+ return DAG.getNode(CastOpc, dl, DstVT, ClampedTop);
+ }
// This code is only for floats and doubles. Fall back to generic code for
// anything else.
if (!isScalarFPTypeInSSEReg(SrcVT) || isBF16orSoftF16(SrcVT, Subtarget))
>From 5134f1524e8aa8ca5bfd0c866a28565b8cf469a9 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 24 May 2026 03:49:34 +0200
Subject: [PATCH 02/11] code clean
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 29 ++++++++++++++-----------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 404f9e4045afd..3fae2a24332a5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22875,22 +22875,25 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2IBS : X86ISD::CVTTP2IUBS,
dl, VecI16VT, Src);
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
- }
- else if(DstVT == MVT::v4i32 && Subtarget.hasSSE2())
- {
- const bool isSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
- SDValue src = Op.getOperand(0);
- EVT SrcVT = Src.getValueType();
- SDLoc dl(Op);
- double MaxVal = IsSigned ? 2147483520.0 : 4294967040.0;
- double MinVal = IsSigned ? -2147483648.0 : 0.0;
- SDValue MaxC = DAG.getConstantFP(MaxVal, dl, SrcVT);
- SDValue MinC = DAG.getConstantFP(MinVal, dl, SrcVT);
+ } else if (DstVT == MVT::v4i32 && Subtarget.hasSSE2()) {
+ unsigned SatWidth = SatVT.getScalarSizeInBits();
+ APInt MinInt = IsSigned ? APInt::getSignedMinValue(SatWidth)
+ : APInt::getMinValue(SatWidth);
+ APInt MaxInt = IsSigned ? APInt::getSignedMaxValue(SatWidth)
+ : APInt::getMaxValue(SatWidth);
+
+ const fltSemantics &Sem = SrcVT.getFltSemantics();
+ APFloat MinFloat(Sem);
+ MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero);
+ APFloat MaxFloat(Sem);
+ MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero);
+
+ SDValue MaxC = DAG.getConstantFP(MaxFloat, dl, SrcVT);
+ SDValue MinC = DAG.getConstantFP(MinFloat, dl, SrcVT);
SDValue ClampedBottom = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, MinC);
SDValue ClampedTop = DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
- unsigned CastOpc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
- return DAG.getNode(CastOpc, dl, DstVT, ClampedTop);
+ return DAG.getNode(FpToIntOpcode, dl, DstVT, ClampedTop);
}
// This code is only for floats and doubles. Fall back to generic code for
// anything else.
>From 6be04df2b92a088fa573cbeaf82524c7e9fd2581 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 24 May 2026 05:11:07 +0200
Subject: [PATCH 03/11] [X86] Optimize vector FP_TO_INT_SAT lowering for v4i32
on SSE2.
This replaces the costly scalarization fallback with precise vectorized boundary clamping and native
conversions.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 66 +-
.../CodeGen/X86/fp-to-int-sat-vector-sse2.ll | 113 ++++
llvm/test/CodeGen/X86/fpclamptosat_vec.ll | 630 +++++++-----------
.../test/CodeGen/X86/fptosi-sat-vector-128.ll | 129 +---
.../test/CodeGen/X86/fptoui-sat-vector-128.ll | 125 +---
5 files changed, 455 insertions(+), 608 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/fp-to-int-sat-vector-sse2.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3fae2a24332a5..dade49786e072 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22877,6 +22877,45 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
} else if (DstVT == MVT::v4i32 && Subtarget.hasSSE2()) {
unsigned SatWidth = SatVT.getScalarSizeInBits();
+ assert(SatWidth <= 32 && "Expected saturation width no wider than result element");
+
+ if (SatWidth == 32) {
+ if (IsSigned) {
+ // Direct conversion handles in-range and negative overflow correctly.
+ SDValue Cvt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
+
+ // Detect positive overflow (src >= 2^31) and saturate to INT_MAX.
+ APFloat PosOvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
+ PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32), /*IsSigned=*/true, APFloat::rmTowardZero);
+ PosOvfBoundFlt.changeSign(); // Flips -2^31 to +2^31
+ SDValue PosOvfBound = DAG.getConstantFP(PosOvfBoundFlt, dl, SrcVT);
+ SDValue PosOvf = DAG.getSetCC(dl, DstVT, Src, PosOvfBound, ISD::SETOGE);
+ SDValue IntMax = DAG.getConstant(APInt::getSignedMaxValue(32), dl, DstVT);
+ SDValue Fixed = DAG.getSelect(dl, DstVT, PosOvf, IntMax, Cvt);
+
+ // Detect NaN and map to 0.
+ SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
+ SDValue Zero = DAG.getConstant(0, dl, DstVT);
+ return DAG.getSelect(dl, DstVT, IsNaN, Zero, Fixed);
+ } else {
+ // Clamp negative values and NaN to 0. FMAX maps NaN to 0.0.
+ SDValue ZeroFP = DAG.getConstantFP(0.0, dl, SrcVT);
+ SDValue Clamped = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, ZeroFP);
+
+ // Detect overflow (src >= 2^32) to saturate to UINT_MAX.
+ APFloat OvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
+ OvfBoundFlt.convertFromAPInt(APInt::getOneBitSet(33, 32), /*IsSigned=*/false, APFloat::rmTowardZero);
+ SDValue OvfBound = DAG.getConstantFP(OvfBoundFlt, dl, SrcVT);
+ SDValue IsOvf = DAG.getSetCC(dl, DstVT, Clamped, OvfBound, ISD::SETOGE);
+
+ SDValue Cvt = DAG.getNode(ISD::FP_TO_UINT, dl, DstVT, Clamped);
+ SDValue UintMax = DAG.getConstant(APInt::getMaxValue(32), dl, DstVT);
+
+ // Apply saturation for overflow.
+ return DAG.getSelect(dl, DstVT, IsOvf, UintMax, Cvt);
+ }
+ }
+
APInt MinInt = IsSigned ? APInt::getSignedMinValue(SatWidth)
: APInt::getMinValue(SatWidth);
APInt MaxInt = IsSigned ? APInt::getSignedMaxValue(SatWidth)
@@ -22884,16 +22923,37 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
const fltSemantics &Sem = SrcVT.getFltSemantics();
APFloat MinFloat(Sem);
- MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero);
APFloat MaxFloat(Sem);
- MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero);
+ // Only use the FMAX/FMIN clamp path when both bounds are exactly
+ // representable in the source float type. If either is inexact, fall back
+ // to generic lowering.
+ bool AreExactFloatBounds =
+ !(MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero) &
+ APFloat::opInexact) &&
+ !(MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero) &
+ APFloat::opInexact);
+ if (!AreExactFloatBounds)
+ return SDValue();
SDValue MaxC = DAG.getConstantFP(MaxFloat, dl, SrcVT);
SDValue MinC = DAG.getConstantFP(MinFloat, dl, SrcVT);
+ // Clamp from below. X86ISD::FMAX returns the second operand when either
+ // input is NaN, so NaN maps to MinC here.
SDValue ClampedBottom = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, MinC);
+ // Clamp from above. NaN (now MinC) is already in range and passes through.
SDValue ClampedTop = DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
- return DAG.getNode(FpToIntOpcode, dl, DstVT, ClampedTop);
+ SDValue Result = DAG.getNode(FpToIntOpcode, dl, DstVT, ClampedTop);
+
+ // For signed saturation, NaN was mapped to MinC, so FP_TO_SINT produces
+ // INT_MIN. ISD::FP_TO_SINT_SAT requires NaN -> 0; fix with a zero-select.
+ // For unsigned saturation, MinC == 0.0, so NaN -> 0.0 -> 0: already correct.
+ if (IsSigned) {
+ SDValue Zero = DAG.getConstant(0, dl, DstVT);
+ SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
+ return DAG.getSelect(dl, DstVT, IsNaN, Zero, Result);
+ }
+ return Result;
}
// This code is only for floats and doubles. Fall back to generic code for
// anything else.
diff --git a/llvm/test/CodeGen/X86/fp-to-int-sat-vector-sse2.ll b/llvm/test/CodeGen/X86/fp-to-int-sat-vector-sse2.ll
new file mode 100644
index 0000000000000..b9ae1157f991f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp-to-int-sat-vector-sse2.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64 -mattr=+sse2,-avx | FileCheck %s --check-prefix=SSE2
+
+declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)
+declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)
+
+; 1. Base case variables
+define <4 x i32> @test_signed_var(<4 x float> %f) {
+; SSE2-LABEL: test_signed_var:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; SSE2-NEXT: cmpleps %xmm0, %xmm1
+; SSE2-NEXT: cvttps2dq %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm1, %xmm3
+; SSE2-NEXT: andnps %xmm2, %xmm3
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: orps %xmm3, %xmm1
+; SSE2-NEXT: cmpunordps %xmm0, %xmm0
+; SSE2-NEXT: andnps %xmm1, %xmm0
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f)
+ ret <4 x i32> %x
+}
+
+define <4 x i32> @test_unsigned_var(<4 x float> %f) {
+; SSE2-LABEL: test_unsigned_var:
+; SSE2: # %bb.0:
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: maxps %xmm1, %xmm0
+; SSE2-NEXT: cvttps2dq %xmm0, %xmm2
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9]
+; SSE2-NEXT: cmpleps %xmm0, %xmm1
+; SSE2-NEXT: orps %xmm2, %xmm1
+; SSE2-NEXT: psrad $31, %xmm2
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %f)
+ ret <4 x i32> %x
+}
+
+; 2. Signed edge cases
+define <4 x i32> @test_signed_edge1() {
+ ; NaN, +Inf, -Inf, 0.0
+; SSE2-LABEL: test_signed_edge1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: cvttps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: movaps {{.*#+}} xmm0 = [u,u,NaN,u]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
+; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF0000000000000, float 0xFFF0000000000000, float 0.0>)
+ ret <4 x i32> %x
+}
+
+define <4 x i32> @test_signed_edge2() {
+ ; exact limits and slight overflow
+ ; 2^31, < -2^31, max f32 < 2^31, -2^31
+; SSE2-LABEL: test_signed_edge2:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]
+; SSE2-NEXT: cvttps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> <float 2147483648.0, float -2147483904.0, float 2147483520.0, float -2147483648.0>)
+ ret <4 x i32> %x
+}
+
+; 3. Unsigned edge cases
+define <4 x i32> @test_unsigned_edge1() {
+ ; NaN, -1.0, +Inf, 0.0
+; SSE2-LABEL: test_unsigned_edge1:
+; SSE2: # %bb.0:
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [NaN,-1.0E+0,+Inf,0.0E+0]
+; SSE2-NEXT: maxps %xmm0, %xmm1
+; SSE2-NEXT: cvttps2dq %xmm1, %xmm2
+; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9]
+; SSE2-NEXT: cmpleps %xmm1, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: psrad $31, %xmm2
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
+; SSE2-NEXT: pand %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> <float 0x7FF8000000000000, float -1.0, float 0x7FF0000000000000, float 0.0>)
+ ret <4 x i32> %x
+}
+
+define <4 x i32> @test_unsigned_edge2() {
+ ; slight below zero, > 2^32, max f32 < 2^32, 2^32 exact
+; SSE2-LABEL: test_unsigned_edge2:
+; SSE2: # %bb.0:
+; SSE2-NEXT: xorps %xmm0, %xmm0
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [-5.0E-1,4.2949673E+9,4.29496704E+9,4.2949673E+9]
+; SSE2-NEXT: maxps %xmm0, %xmm1
+; SSE2-NEXT: cvttps2dq %xmm1, %xmm2
+; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9]
+; SSE2-NEXT: cmpleps %xmm1, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: psrad $31, %xmm2
+; SSE2-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
+; SSE2-NEXT: pand %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: retq
+ %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> <float -0.5, float 4294967296.0, float 4294967040.0, float 4294967296.0>)
+ ret <4 x i32> %x
+}
diff --git a/llvm/test/CodeGen/X86/fpclamptosat_vec.ll b/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
index 991ce33e58b4c..f8d7eece7c70c 100644
--- a/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
@@ -227,106 +227,26 @@ entry:
define <4 x i32> @stest_f32i32(<4 x float> %x) nounwind {
; SSE-LABEL: stest_f32i32:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; SSE-NEXT: cvttss2si %xmm1, %rax
-; SSE-NEXT: movq %rax, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: cvttss2si %xmm2, %rax
-; SSE-NEXT: movq %rax, %xmm2
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm4
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm4, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm7, %xmm8
-; SSE-NEXT: pcmpgtd %xmm1, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm9
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm8[1,1,3,3]
-; SSE-NEXT: por %xmm9, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm4
-; SSE-NEXT: pandn %xmm3, %xmm1
-; SSE-NEXT: por %xmm4, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm4
-; SSE-NEXT: pxor %xmm0, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: pcmpgtd %xmm4, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm4, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm3, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: movdqa %xmm5, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm5
-; SSE-NEXT: pandn %xmm2, %xmm3
-; SSE-NEXT: por %xmm5, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
-; SSE-NEXT: pcmpgtd %xmm7, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; SSE-NEXT: cmpleps %xmm0, %xmm1
+; SSE-NEXT: cvttps2dq %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm3
+; SSE-NEXT: andnps %xmm2, %xmm3
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: orps %xmm3, %xmm1
+; SSE-NEXT: cmpunordps %xmm0, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f32i32:
; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rax, %xmm1
-; AVX2-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX2-NEXT: vcvttss2si %xmm2, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
-; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
-; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; AVX2-NEXT: vcmpleps %xmm0, %xmm1, %xmm1
+; AVX2-NEXT: vcvttps2dq %xmm0, %xmm2
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vblendvps %xmm1, %xmm3, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX2-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: stest_f32i32:
@@ -604,130 +524,121 @@ entry:
define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; SSE-LABEL: stest_f16i32:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
+; SSE-NEXT: pushq %rbp
+; SSE-NEXT: pushq %r14
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: subq $64, %rsp
+; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrld $16, %xmm1
; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
-; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; SSE-NEXT: psrlq $48, %xmm0
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: xorl %r14d, %r14d
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: punpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm3 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm3, %xmm8
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm4, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm5, %xmm6
-; SSE-NEXT: pcmpgtd %xmm1, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm8
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm6
-; SSE-NEXT: pcmpgtd %xmm3, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: movdqa %xmm4, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm4
-; SSE-NEXT: pandn %xmm2, %xmm3
-; SSE-NEXT: por %xmm4, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
-; SSE-NEXT: pcmpgtd %xmm7, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
-; SSE-NEXT: addq $72, %rsp
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm1
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT: punpcklqdq (%rsp), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
+; SSE-NEXT: addq $64, %rsp
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: popq %r14
+; SSE-NEXT: popq %rbp
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f16i32:
; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: vpsrlq $48, %xmm0, %xmm1
-; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rcx
-; AVX2-NEXT: vcvtph2ps %xmm0, %xmm1
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
+; AVX2-NEXT: vcvtph2ps %xmm1, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %esi
+; AVX2-NEXT: vmovss {{.*#+}} xmm1 = [-2.14748365E+9,0.0E+0,0.0E+0,0.0E+0]
+; AVX2-NEXT: vucomiss %xmm1, %xmm3
+; AVX2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vmovss {{.*#+}} xmm2 = [2.14748352E+9,0.0E+0,0.0E+0,0.0E+0]
+; AVX2-NEXT: vucomiss %xmm2, %xmm3
+; AVX2-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: xorl %edx, %edx
+; AVX2-NEXT: vucomiss %xmm3, %xmm3
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vcvtph2ps %xmm0, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %edi
+; AVX2-NEXT: vucomiss %xmm1, %xmm3
+; AVX2-NEXT: cmovbl %eax, %edi
+; AVX2-NEXT: vucomiss %xmm2, %xmm3
+; AVX2-NEXT: cmoval %ecx, %edi
+; AVX2-NEXT: vucomiss %xmm3, %xmm3
+; AVX2-NEXT: cmovpl %edx, %edi
+; AVX2-NEXT: vmovd %edi, %xmm3
+; AVX2-NEXT: vpinsrd $1, %esi, %xmm3, %xmm3
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4
+; AVX2-NEXT: vcvttss2si %xmm4, %esi
+; AVX2-NEXT: vucomiss %xmm1, %xmm4
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vucomiss %xmm2, %xmm4
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: vucomiss %xmm4, %xmm4
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vpinsrd $2, %esi, %xmm3, %xmm3
+; AVX2-NEXT: vpsrlq $48, %xmm0, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
-; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
-; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: vcvttss2si %xmm0, %esi
+; AVX2-NEXT: vucomiss %xmm1, %xmm0
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vucomiss %xmm2, %xmm0
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: vucomiss %xmm0, %xmm0
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vpinsrd $3, %esi, %xmm3, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: stest_f16i32:
@@ -2846,106 +2757,26 @@ entry:
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) nounwind {
; SSE-LABEL: stest_f32i32_mm:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; SSE-NEXT: cvttss2si %xmm1, %rax
-; SSE-NEXT: movq %rax, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: cvttss2si %xmm2, %rax
-; SSE-NEXT: movq %rax, %xmm2
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm5, %xmm5
-; SSE-NEXT: pcmpeqd %xmm5, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm6, %xmm7
-; SSE-NEXT: pcmpgtd %xmm1, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483647,2147483647]
-; SSE-NEXT: pand %xmm1, %xmm3
-; SSE-NEXT: pandn %xmm4, %xmm1
-; SSE-NEXT: por %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm7
-; SSE-NEXT: pcmpgtd %xmm3, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
-; SSE-NEXT: pand %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm4, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm4, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm6, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm2[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: pand %xmm2, %xmm5
-; SSE-NEXT: pandn %xmm3, %xmm2
-; SSE-NEXT: por %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm5
-; SSE-NEXT: pcmpgtd %xmm6, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm4, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm3, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
+; SSE-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; SSE-NEXT: cmpleps %xmm0, %xmm1
+; SSE-NEXT: cvttps2dq %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm3
+; SSE-NEXT: andnps %xmm2, %xmm3
+; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: orps %xmm3, %xmm1
+; SSE-NEXT: cmpunordps %xmm0, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f32i32_mm:
; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rax, %xmm1
-; AVX2-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX2-NEXT: vcvttss2si %xmm2, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
-; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
-; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; AVX2-NEXT: vcmpleps %xmm0, %xmm1, %xmm1
+; AVX2-NEXT: vcvttps2dq %xmm0, %xmm2
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vblendvps %xmm1, %xmm3, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX2-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: stest_f32i32_mm:
@@ -3218,130 +3049,121 @@ entry:
define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-LABEL: stest_f16i32_mm:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
+; SSE-NEXT: pushq %rbp
+; SSE-NEXT: pushq %r14
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: subq $64, %rsp
+; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrld $16, %xmm1
; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
-; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; SSE-NEXT: psrlq $48, %xmm0
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: xorl %r14d, %r14d
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: punpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm2 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm7
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm3, %xmm3
-; SSE-NEXT: pcmpeqd %xmm3, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm4, %xmm5
-; SSE-NEXT: pcmpgtd %xmm1, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm2, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm6, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
-; SSE-NEXT: pand %xmm1, %xmm7
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm5
-; SSE-NEXT: pxor %xmm0, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm3, %xmm6
-; SSE-NEXT: pcmpgtd %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm4, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm5
-; SSE-NEXT: pcmpeqd %xmm5, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm6, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm2[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: pand %xmm2, %xmm4
-; SSE-NEXT: pandn %xmm3, %xmm2
-; SSE-NEXT: por %xmm4, %xmm2
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm4
-; SSE-NEXT: pcmpgtd %xmm6, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm3, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
-; SSE-NEXT: addq $72, %rsp
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: cvttss2si %xmm0, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmovbl %ebx, %eax
+; SSE-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cmoval %ebp, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm0
+; SSE-NEXT: cmovpl %r14d, %eax
+; SSE-NEXT: movd %eax, %xmm1
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT: punpcklqdq (%rsp), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
+; SSE-NEXT: addq $64, %rsp
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: popq %r14
+; SSE-NEXT: popq %rbp
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f16i32_mm:
; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: vpsrlq $48, %xmm0, %xmm1
-; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rcx
-; AVX2-NEXT: vcvtph2ps %xmm0, %xmm1
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
+; AVX2-NEXT: vcvtph2ps %xmm1, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %esi
+; AVX2-NEXT: vmovss {{.*#+}} xmm1 = [-2.14748365E+9,0.0E+0,0.0E+0,0.0E+0]
+; AVX2-NEXT: vucomiss %xmm1, %xmm3
+; AVX2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vmovss {{.*#+}} xmm2 = [2.14748352E+9,0.0E+0,0.0E+0,0.0E+0]
+; AVX2-NEXT: vucomiss %xmm2, %xmm3
+; AVX2-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: xorl %edx, %edx
+; AVX2-NEXT: vucomiss %xmm3, %xmm3
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vcvtph2ps %xmm0, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %edi
+; AVX2-NEXT: vucomiss %xmm1, %xmm3
+; AVX2-NEXT: cmovbl %eax, %edi
+; AVX2-NEXT: vucomiss %xmm2, %xmm3
+; AVX2-NEXT: cmoval %ecx, %edi
+; AVX2-NEXT: vucomiss %xmm3, %xmm3
+; AVX2-NEXT: cmovpl %edx, %edi
+; AVX2-NEXT: vmovd %edi, %xmm3
+; AVX2-NEXT: vpinsrd $1, %esi, %xmm3, %xmm3
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4
+; AVX2-NEXT: vcvttss2si %xmm4, %esi
+; AVX2-NEXT: vucomiss %xmm1, %xmm4
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vucomiss %xmm2, %xmm4
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: vucomiss %xmm4, %xmm4
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vpinsrd $2, %esi, %xmm3, %xmm3
+; AVX2-NEXT: vpsrlq $48, %xmm0, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vcvttss2si %xmm0, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
-; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
-; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: vcvttss2si %xmm0, %esi
+; AVX2-NEXT: vucomiss %xmm1, %xmm0
+; AVX2-NEXT: cmovbl %eax, %esi
+; AVX2-NEXT: vucomiss %xmm2, %xmm0
+; AVX2-NEXT: cmoval %ecx, %esi
+; AVX2-NEXT: vucomiss %xmm0, %xmm0
+; AVX2-NEXT: cmovpl %edx, %esi
+; AVX2-NEXT: vpinsrd $3, %esi, %xmm3, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: stest_f16i32_mm:
diff --git a/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll b/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
index 0183d7a7d0026..b197a2011c01c 100644
--- a/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
+++ b/llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
@@ -16,42 +16,12 @@ define <4 x i1> @test_signed_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i1_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: movss {{.*#+}} xmm2 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ucomiss %xmm1, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm4
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
-; CHECK-NEXT: ucomiss %xmm4, %xmm4
-; CHECK-NEXT: maxss %xmm2, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm4
-; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %ecx
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: maxss %xmm2, %xmm0
-; CHECK-NEXT: minss %xmm3, %xmm0
-; CHECK-NEXT: cvttss2si %xmm0, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: maxps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: minps %xmm2, %xmm1
+; CHECK-NEXT: cvttps2dq %xmm1, %xmm1
+; CHECK-NEXT: cmpunordps %xmm0, %xmm0
+; CHECK-NEXT: andnps %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> %f)
ret <4 x i1> %x
@@ -61,42 +31,12 @@ define <4 x i1> @test_freeze_signed_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_freeze_signed_v4i1_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: movss {{.*#+}} xmm2 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ucomiss %xmm1, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm4
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
-; CHECK-NEXT: ucomiss %xmm4, %xmm4
-; CHECK-NEXT: maxss %xmm2, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm4
-; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %ecx
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: maxss %xmm2, %xmm0
-; CHECK-NEXT: minss %xmm3, %xmm0
-; CHECK-NEXT: cvttss2si %xmm0, %ecx
-; CHECK-NEXT: cmovpl %eax, %ecx
-; CHECK-NEXT: movd %ecx, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: maxps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: minps %xmm2, %xmm1
+; CHECK-NEXT: cvttps2dq %xmm1, %xmm1
+; CHECK-NEXT: cmpunordps %xmm0, %xmm0
+; CHECK-NEXT: andnps %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> %f)
%y = freeze <4 x i1> %x
@@ -187,42 +127,15 @@ define <4 x i16> @test_signed_v4i16_v4f32(<4 x float> %f) nounwind {
define <4 x i32> @test_signed_v4i32_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: cvttss2si %xmm1, %edx
-; CHECK-NEXT: movss {{.*#+}} xmm2 = [2.14748352E+9,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: ucomiss %xmm2, %xmm1
-; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-NEXT: cmoval %eax, %edx
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: ucomiss %xmm1, %xmm1
-; CHECK-NEXT: cmovpl %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm3
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
-; CHECK-NEXT: cvttss2si %xmm3, %edx
-; CHECK-NEXT: ucomiss %xmm2, %xmm3
-; CHECK-NEXT: cmoval %eax, %edx
-; CHECK-NEXT: ucomiss %xmm3, %xmm3
-; CHECK-NEXT: cmovpl %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm3
-; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
-; CHECK-NEXT: cvttss2si %xmm0, %edx
-; CHECK-NEXT: ucomiss %xmm2, %xmm0
-; CHECK-NEXT: cmoval %eax, %edx
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: cmovpl %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: cvttss2si %xmm0, %edx
-; CHECK-NEXT: ucomiss %xmm2, %xmm0
-; CHECK-NEXT: cmoval %eax, %edx
-; CHECK-NEXT: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: cmovpl %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; CHECK-NEXT: cmpleps %xmm0, %xmm1
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm2
+; CHECK-NEXT: movaps %xmm1, %xmm3
+; CHECK-NEXT: andnps %xmm2, %xmm3
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: orps %xmm3, %xmm1
+; CHECK-NEXT: cmpunordps %xmm0, %xmm0
+; CHECK-NEXT: andnps %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f)
ret <4 x i32> %x
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
index 578eaa06ca7d3..22753a154b36c 100644
--- a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
+++ b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
@@ -15,34 +15,16 @@ declare <4 x i128> @llvm.fptoui.sat.v4i128.v4f32(<4 x float>)
define <4 x i1> @test_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v4i1_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: xorps %xmm2, %xmm2
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: movss {{.*#+}} xmm3 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %eax
-; CHECK-NEXT: movd %eax, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm4
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
-; CHECK-NEXT: maxss %xmm2, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %eax
-; CHECK-NEXT: movd %eax, %xmm4
-; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %eax
-; CHECK-NEXT: movd %eax, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: maxss %xmm2, %xmm0
-; CHECK-NEXT: minss %xmm3, %xmm0
-; CHECK-NEXT: cvttss2si %xmm0, %eax
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: maxps %xmm1, %xmm0
+; CHECK-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: psrad $31, %xmm2
+; CHECK-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
+; CHECK-NEXT: pand %xmm2, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> %f)
ret <4 x i1> %x
@@ -51,34 +33,16 @@ define <4 x i1> @test_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
define <4 x i1> @test_freeze_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_freeze_unsigned_v4i1_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: xorps %xmm2, %xmm2
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: movss {{.*#+}} xmm3 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %eax
-; CHECK-NEXT: movd %eax, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm4
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
-; CHECK-NEXT: maxss %xmm2, %xmm4
-; CHECK-NEXT: minss %xmm3, %xmm4
-; CHECK-NEXT: cvttss2si %xmm4, %eax
-; CHECK-NEXT: movd %eax, %xmm4
-; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: maxss %xmm2, %xmm1
-; CHECK-NEXT: minss %xmm3, %xmm1
-; CHECK-NEXT: cvttss2si %xmm1, %eax
-; CHECK-NEXT: movd %eax, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: maxss %xmm2, %xmm0
-; CHECK-NEXT: minss %xmm3, %xmm0
-; CHECK-NEXT: cvttss2si %xmm0, %eax
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: maxps %xmm1, %xmm0
+; CHECK-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: psrad $31, %xmm2
+; CHECK-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
+; CHECK-NEXT: pand %xmm2, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> %f)
%y = freeze <4 x i1> %x
@@ -169,43 +133,18 @@ define <4 x i16> @test_unsigned_v4i16_v4f32(<4 x float> %f) nounwind {
define <4 x i32> @test_unsigned_v4i32_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v4i32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; CHECK-NEXT: cvttss2si %xmm1, %rdx
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorps %xmm2, %xmm2
-; CHECK-NEXT: ucomiss %xmm2, %xmm1
-; CHECK-NEXT: cmovbl %eax, %edx
-; CHECK-NEXT: movss {{.*#+}} xmm3 = [4.29496704E+9,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-NEXT: ucomiss %xmm3, %xmm1
-; CHECK-NEXT: movl $-1, %ecx
-; CHECK-NEXT: cmoval %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm4
-; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
-; CHECK-NEXT: cvttss2si %xmm4, %rdx
-; CHECK-NEXT: ucomiss %xmm2, %xmm4
-; CHECK-NEXT: cmovbl %eax, %edx
-; CHECK-NEXT: ucomiss %xmm3, %xmm4
-; CHECK-NEXT: cmoval %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm4
-; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
-; CHECK-NEXT: cvttss2si %xmm0, %rdx
-; CHECK-NEXT: ucomiss %xmm2, %xmm0
-; CHECK-NEXT: cmovbl %eax, %edx
-; CHECK-NEXT: ucomiss %xmm3, %xmm0
-; CHECK-NEXT: cmoval %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm1
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; CHECK-NEXT: cvttss2si %xmm0, %rdx
-; CHECK-NEXT: ucomiss %xmm2, %xmm0
-; CHECK-NEXT: cmovbl %eax, %edx
-; CHECK-NEXT: ucomiss %xmm3, %xmm0
-; CHECK-NEXT: cmoval %ecx, %edx
-; CHECK-NEXT: movd %edx, %xmm0
-; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: maxps %xmm1, %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm2
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9]
+; CHECK-NEXT: cmpleps %xmm0, %xmm1
+; CHECK-NEXT: orps %xmm2, %xmm1
+; CHECK-NEXT: psrad $31, %xmm2
+; CHECK-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
+; CHECK-NEXT: pand %xmm2, %xmm0
+; CHECK-NEXT: orps %xmm0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %f)
ret <4 x i32> %x
>From 33a3dd5fa662084ed5c222f2702ddc9b17fabb65 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 24 May 2026 14:43:17 +0200
Subject: [PATCH 04/11] Remove unecessary comments
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dade49786e072..ef6a41712b18f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22881,37 +22881,26 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
if (SatWidth == 32) {
if (IsSigned) {
- // Direct conversion handles in-range and negative overflow correctly.
SDValue Cvt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
-
- // Detect positive overflow (src >= 2^31) and saturate to INT_MAX.
APFloat PosOvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32), /*IsSigned=*/true, APFloat::rmTowardZero);
- PosOvfBoundFlt.changeSign(); // Flips -2^31 to +2^31
+ PosOvfBoundFlt.changeSign();
SDValue PosOvfBound = DAG.getConstantFP(PosOvfBoundFlt, dl, SrcVT);
SDValue PosOvf = DAG.getSetCC(dl, DstVT, Src, PosOvfBound, ISD::SETOGE);
SDValue IntMax = DAG.getConstant(APInt::getSignedMaxValue(32), dl, DstVT);
SDValue Fixed = DAG.getSelect(dl, DstVT, PosOvf, IntMax, Cvt);
-
- // Detect NaN and map to 0.
SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
SDValue Zero = DAG.getConstant(0, dl, DstVT);
return DAG.getSelect(dl, DstVT, IsNaN, Zero, Fixed);
} else {
- // Clamp negative values and NaN to 0. FMAX maps NaN to 0.0.
SDValue ZeroFP = DAG.getConstantFP(0.0, dl, SrcVT);
SDValue Clamped = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, ZeroFP);
-
- // Detect overflow (src >= 2^32) to saturate to UINT_MAX.
APFloat OvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
OvfBoundFlt.convertFromAPInt(APInt::getOneBitSet(33, 32), /*IsSigned=*/false, APFloat::rmTowardZero);
SDValue OvfBound = DAG.getConstantFP(OvfBoundFlt, dl, SrcVT);
SDValue IsOvf = DAG.getSetCC(dl, DstVT, Clamped, OvfBound, ISD::SETOGE);
-
SDValue Cvt = DAG.getNode(ISD::FP_TO_UINT, dl, DstVT, Clamped);
SDValue UintMax = DAG.getConstant(APInt::getMaxValue(32), dl, DstVT);
-
- // Apply saturation for overflow.
return DAG.getSelect(dl, DstVT, IsOvf, UintMax, Cvt);
}
}
>From c68ba79280353010bd6e56b0bcb85888b82d2573 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Mon, 25 May 2026 16:55:56 +0200
Subject: [PATCH 05/11] fix test
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 9 ++++++++-
llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll | 12 ------------
2 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ef6a41712b18f..f92edd4d24106 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22932,7 +22932,14 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
SDValue ClampedBottom = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, MinC);
// Clamp from above. NaN (now MinC) is already in range and passes through.
SDValue ClampedTop = DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
- SDValue Result = DAG.getNode(FpToIntOpcode, dl, DstVT, ClampedTop);
+
+ // For smaller widths, the max unsigned value fits in a signed 32-bit int.
+ // Use FP_TO_SINT instead of FP_TO_UINT to avoid expensive legalization.
+ unsigned CastOpc = FpToIntOpcode;
+ if (!IsSigned && SatWidth < 32)
+ CastOpc = ISD::FP_TO_SINT;
+
+ SDValue Result = DAG.getNode(CastOpc, dl, DstVT, ClampedTop);
// For signed saturation, NaN was mapped to MinC, so FP_TO_SINT produces
// INT_MIN. ISD::FP_TO_SINT_SAT requires NaN -> 0; fix with a zero-select.
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
index 22753a154b36c..9b1ed3989f086 100644
--- a/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
+++ b/llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
@@ -18,13 +18,7 @@ define <4 x i1> @test_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: maxps %xmm1, %xmm0
; CHECK-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cvttps2dq %xmm0, %xmm1
-; CHECK-NEXT: movdqa %xmm1, %xmm2
-; CHECK-NEXT: psrad $31, %xmm2
-; CHECK-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
-; CHECK-NEXT: pand %xmm2, %xmm0
-; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> %f)
ret <4 x i1> %x
@@ -36,13 +30,7 @@ define <4 x i1> @test_freeze_unsigned_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: maxps %xmm1, %xmm0
; CHECK-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: cvttps2dq %xmm0, %xmm1
-; CHECK-NEXT: movdqa %xmm1, %xmm2
-; CHECK-NEXT: psrad $31, %xmm2
-; CHECK-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
-; CHECK-NEXT: pand %xmm2, %xmm0
-; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> %f)
%y = freeze <4 x i1> %x
>From e2e20ccccbf44402849fdb4d211d231e53333cc5 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Mon, 25 May 2026 17:25:46 +0200
Subject: [PATCH 06/11] git format
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f92edd4d24106..b2ba179d56bea 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22877,17 +22877,21 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
} else if (DstVT == MVT::v4i32 && Subtarget.hasSSE2()) {
unsigned SatWidth = SatVT.getScalarSizeInBits();
- assert(SatWidth <= 32 && "Expected saturation width no wider than result element");
+ assert(SatWidth <= 32 &&
+ "Expected saturation width no wider than result element");
if (SatWidth == 32) {
if (IsSigned) {
SDValue Cvt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
APFloat PosOvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
- PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32), /*IsSigned=*/true, APFloat::rmTowardZero);
+ PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32),
+ /*IsSigned=*/true,
+ APFloat::rmTowardZero);
PosOvfBoundFlt.changeSign();
SDValue PosOvfBound = DAG.getConstantFP(PosOvfBoundFlt, dl, SrcVT);
SDValue PosOvf = DAG.getSetCC(dl, DstVT, Src, PosOvfBound, ISD::SETOGE);
- SDValue IntMax = DAG.getConstant(APInt::getSignedMaxValue(32), dl, DstVT);
+ SDValue IntMax =
+ DAG.getConstant(APInt::getSignedMaxValue(32), dl, DstVT);
SDValue Fixed = DAG.getSelect(dl, DstVT, PosOvf, IntMax, Cvt);
SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
SDValue Zero = DAG.getConstant(0, dl, DstVT);
@@ -22896,7 +22900,8 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
SDValue ZeroFP = DAG.getConstantFP(0.0, dl, SrcVT);
SDValue Clamped = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, ZeroFP);
APFloat OvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
- OvfBoundFlt.convertFromAPInt(APInt::getOneBitSet(33, 32), /*IsSigned=*/false, APFloat::rmTowardZero);
+ OvfBoundFlt.convertFromAPInt(APInt::getOneBitSet(33, 32),
+ /*IsSigned=*/false, APFloat::rmTowardZero);
SDValue OvfBound = DAG.getConstantFP(OvfBoundFlt, dl, SrcVT);
SDValue IsOvf = DAG.getSetCC(dl, DstVT, Clamped, OvfBound, ISD::SETOGE);
SDValue Cvt = DAG.getNode(ISD::FP_TO_UINT, dl, DstVT, Clamped);
@@ -22931,8 +22936,9 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
// input is NaN, so NaN maps to MinC here.
SDValue ClampedBottom = DAG.getNode(X86ISD::FMAX, dl, SrcVT, Src, MinC);
// Clamp from above. NaN (now MinC) is already in range and passes through.
- SDValue ClampedTop = DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
-
+ SDValue ClampedTop =
+ DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
+
// For smaller widths, the max unsigned value fits in a signed 32-bit int.
// Use FP_TO_SINT instead of FP_TO_UINT to avoid expensive legalization.
unsigned CastOpc = FpToIntOpcode;
@@ -22943,7 +22949,8 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
// For signed saturation, NaN was mapped to MinC, so FP_TO_SINT produces
// INT_MIN. ISD::FP_TO_SINT_SAT requires NaN -> 0; fix with a zero-select.
- // For unsigned saturation, MinC == 0.0, so NaN -> 0.0 -> 0: already correct.
+ // For unsigned saturation, MinC == 0.0, so NaN -> 0.0 -> 0: already
+ // correct.
if (IsSigned) {
SDValue Zero = DAG.getConstant(0, dl, DstVT);
SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
>From 1e0ec63f3f5c83347f68cb1f6283e27de7686f95 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Tue, 9 Jun 2026 20:39:54 +0200
Subject: [PATCH 07/11] implement suggestions from review
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b2ba179d56bea..1c2b815a8d820 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22875,14 +22875,19 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2IBS : X86ISD::CVTTP2IUBS,
dl, VecI16VT, Src);
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
- } else if (DstVT == MVT::v4i32 && Subtarget.hasSSE2()) {
+ }
+ if ((DstVT == MVT::v4i32 && Subtarget.hasSSE2()) ||
+ (DstVT == MVT::v8i32 && Subtarget.hasAVX()) ||
+ (DstVT == MVT::v16i32 && Subtarget.hasAVX512())) {
unsigned SatWidth = SatVT.getScalarSizeInBits();
assert(SatWidth <= 32 &&
"Expected saturation width no wider than result element");
if (SatWidth == 32) {
if (IsSigned) {
- SDValue Cvt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
+ // Use X86ISD::CVTTP2SI (CVTTPS2DQ/CVTTPD2DQ) which has defined
+ // out-of-range behavior: maps overflow and NaN to 0x80000000 (INT_MIN).
+ SDValue Cvt = DAG.getNode(X86ISD::CVTTP2SI, dl, DstVT, Src);
APFloat PosOvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32),
/*IsSigned=*/true,
@@ -22904,7 +22909,16 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
/*IsSigned=*/false, APFloat::rmTowardZero);
SDValue OvfBound = DAG.getConstantFP(OvfBoundFlt, dl, SrcVT);
SDValue IsOvf = DAG.getSetCC(dl, DstVT, Clamped, OvfBound, ISD::SETOGE);
- SDValue Cvt = DAG.getNode(ISD::FP_TO_UINT, dl, DstVT, Clamped);
+ // v16i32 (512-bit, AVX512): use X86ISD::CVTTP2UI (VCVTTPS2UDQZ).
+ // v4i32 (128-bit, SSE) and v8i32 (256-bit, AVX) are already covered
+ // by CVTTPS2DQ/VCVTTPS2DQ via expandFP_TO_UINT_SSE — no AVX512VL
+ // needed.
+ SDValue Cvt;
+ if (DstVT == MVT::v16i32)
+ Cvt = DAG.getNode(X86ISD::CVTTP2UI, dl, DstVT, Clamped);
+ else
+ Cvt = expandFP_TO_UINT_SSE(DstVT.getSimpleVT(), Clamped, dl, DAG,
+ Subtarget);
SDValue UintMax = DAG.getConstant(APInt::getMaxValue(32), dl, DstVT);
return DAG.getSelect(dl, DstVT, IsOvf, UintMax, Cvt);
}
>From d6e10b59a1b3ed4d0e06427cbcd415f62d93fbb7 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 14 Jun 2026 00:29:44 +0200
Subject: [PATCH 08/11] Enable support for avx and avx512, and use CVTTP2SI
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1c2b815a8d820..91e6ad472c0f0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -322,6 +322,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v4i32, Custom);
setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v4i32, Custom);
}
+ if (Subtarget.hasAVX()) {
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v8i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v8i32, Custom);
+ }
+ if (Subtarget.hasAVX512()) {
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v16i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v16i32, Custom);
+ }
if (Subtarget.hasAVX10_2()) {
for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v32i8}) {
setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
@@ -22954,12 +22962,9 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
// For smaller widths, the max unsigned value fits in a signed 32-bit int.
- // Use FP_TO_SINT instead of FP_TO_UINT to avoid expensive legalization.
- unsigned CastOpc = FpToIntOpcode;
- if (!IsSigned && SatWidth < 32)
- CastOpc = ISD::FP_TO_SINT;
-
- SDValue Result = DAG.getNode(CastOpc, dl, DstVT, ClampedTop);
+ // Use X86ISD::CVTTP2SI instead of FP_TO_UINT to avoid expensive legalization
+ // and guarantee the out-of-range behavior.
+ SDValue Result = DAG.getNode(X86ISD::CVTTP2SI, dl, DstVT, ClampedTop);
// For signed saturation, NaN was mapped to MinC, so FP_TO_SINT produces
// INT_MIN. ISD::FP_TO_SINT_SAT requires NaN -> 0; fix with a zero-select.
>From df475e99f433640ea20fa62913d22726dd675e83 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 14 Jun 2026 01:18:31 +0200
Subject: [PATCH 09/11] fix some fail cases
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 48 +-
.../test/CodeGen/X86/fptosi-sat-vector-256.ll | 2242 ++++++++++
.../test/CodeGen/X86/fptosi-sat-vector-512.ll | 3601 +++++++++++++++++
.../test/CodeGen/X86/fptoui-sat-vector-256.ll | 2204 ++++++++++
.../test/CodeGen/X86/fptoui-sat-vector-512.ll | 3094 ++++++++++++++
5 files changed, 11177 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/fptosi-sat-vector-256.ll
create mode 100644 llvm/test/CodeGen/X86/fptosi-sat-vector-512.ll
create mode 100644 llvm/test/CodeGen/X86/fptoui-sat-vector-256.ll
create mode 100644 llvm/test/CodeGen/X86/fptoui-sat-vector-512.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 91e6ad472c0f0..d838031371a89 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22891,7 +22891,8 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
assert(SatWidth <= 32 &&
"Expected saturation width no wider than result element");
- if (SatWidth == 32) {
+ if (SatWidth == 32 && (SrcVT.getScalarType() == MVT::f32 ||
+ SrcVT.getScalarType() == MVT::f64)) {
if (IsSigned) {
// Use X86ISD::CVTTP2SI (CVTTPS2DQ/CVTTPD2DQ) which has defined
// out-of-range behavior: maps overflow and NaN to 0x80000000 (INT_MIN).
@@ -22902,12 +22903,23 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
APFloat::rmTowardZero);
PosOvfBoundFlt.changeSign();
SDValue PosOvfBound = DAG.getConstantFP(PosOvfBoundFlt, dl, SrcVT);
- SDValue PosOvf = DAG.getSetCC(dl, DstVT, Src, PosOvfBound, ISD::SETOGE);
+ EVT CCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
+ EVT SelCCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT);
+
+ SDValue PosOvf = DAG.getSetCC(dl, CCVT, Src, PosOvfBound, ISD::SETOGE);
+ SDValue IsNaN = DAG.getSetCC(dl, CCVT, Src, Src, ISD::SETUO);
+
+ if (CCVT != SelCCVT) {
+ PosOvf = DAG.getNode(ISD::TRUNCATE, dl, SelCCVT, PosOvf);
+ IsNaN = DAG.getNode(ISD::TRUNCATE, dl, SelCCVT, IsNaN);
+ }
+
SDValue IntMax =
DAG.getConstant(APInt::getSignedMaxValue(32), dl, DstVT);
- SDValue Fixed = DAG.getSelect(dl, DstVT, PosOvf, IntMax, Cvt);
- SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
SDValue Zero = DAG.getConstant(0, dl, DstVT);
+ SDValue Fixed = DAG.getSelect(dl, DstVT, PosOvf, IntMax, Cvt);
return DAG.getSelect(dl, DstVT, IsNaN, Zero, Fixed);
} else {
SDValue ZeroFP = DAG.getConstantFP(0.0, dl, SrcVT);
@@ -22916,7 +22928,13 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
OvfBoundFlt.convertFromAPInt(APInt::getOneBitSet(33, 32),
/*IsSigned=*/false, APFloat::rmTowardZero);
SDValue OvfBound = DAG.getConstantFP(OvfBoundFlt, dl, SrcVT);
- SDValue IsOvf = DAG.getSetCC(dl, DstVT, Clamped, OvfBound, ISD::SETOGE);
+ EVT CCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
+ SDValue IsOvf = DAG.getSetCC(dl, CCVT, Clamped, OvfBound, ISD::SETOGE);
+ EVT SelCCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT);
+ if (CCVT != SelCCVT)
+ IsOvf = DAG.getNode(ISD::TRUNCATE, dl, SelCCVT, IsOvf);
// v16i32 (512-bit, AVX512): use X86ISD::CVTTP2UI (VCVTTPS2UDQZ).
// v4i32 (128-bit, SSE) and v8i32 (256-bit, AVX) are already covered
// by CVTTPS2DQ/VCVTTPS2DQ via expandFP_TO_UINT_SSE — no AVX512VL
@@ -22944,10 +22962,10 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
// representable in the source float type. If either is inexact, fall back
// to generic lowering.
bool AreExactFloatBounds =
- !(MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero) &
- APFloat::opInexact) &&
- !(MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero) &
- APFloat::opInexact);
+ MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero) ==
+ APFloat::opOK &&
+ MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero) ==
+ APFloat::opOK;
if (!AreExactFloatBounds)
return SDValue();
@@ -22962,8 +22980,8 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
DAG.getNode(X86ISD::FMIN, dl, SrcVT, ClampedBottom, MaxC);
// For smaller widths, the max unsigned value fits in a signed 32-bit int.
- // Use X86ISD::CVTTP2SI instead of FP_TO_UINT to avoid expensive legalization
- // and guarantee the out-of-range behavior.
+ // Use X86ISD::CVTTP2SI instead of FP_TO_UINT to avoid expensive
+ // legalization and guarantee the out-of-range behavior.
SDValue Result = DAG.getNode(X86ISD::CVTTP2SI, dl, DstVT, ClampedTop);
// For signed saturation, NaN was mapped to MinC, so FP_TO_SINT produces
@@ -22972,7 +22990,13 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
// correct.
if (IsSigned) {
SDValue Zero = DAG.getConstant(0, dl, DstVT);
- SDValue IsNaN = DAG.getSetCC(dl, DstVT, Src, Src, ISD::SETUO);
+ EVT CCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
+ SDValue IsNaN = DAG.getSetCC(dl, CCVT, Src, Src, ISD::SETUO);
+ EVT SelCCVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT);
+ if (CCVT != SelCCVT)
+ IsNaN = DAG.getNode(ISD::TRUNCATE, dl, SelCCVT, IsNaN);
return DAG.getSelect(dl, DstVT, IsNaN, Zero, Result);
}
return Result;
diff --git a/llvm/test/CodeGen/X86/fptosi-sat-vector-256.ll b/llvm/test/CodeGen/X86/fptosi-sat-vector-256.ll
new file mode 100644
index 0000000000000..474a4f9733d9b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fptosi-sat-vector-256.ll
@@ -0,0 +1,2242 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s
+
+;
+; 32-bit float to signed integer
+;
+
+declare <8 x i1> @llvm.fptosi.sat.v8i1.v8f32(<8 x float>)
+declare <8 x i8> @llvm.fptosi.sat.v8i8.v8f32(<8 x float>)
+declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f32(<8 x float>)
+declare <8 x i32> @llvm.fptosi.sat.v8i32.v8f32(<8 x float>)
+declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float>)
+declare <8 x i128> @llvm.fptosi.sat.v8i128.v8f32(<8 x float>)
+
+define <8 x i1> @test_signed_v8i1_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i1_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f32(<8 x float> %f)
+ ret <8 x i1> %x
+}
+
+define <8 x i1> @test_freeze_signed_v8i1_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_freeze_signed_v8i1_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f32(<8 x float> %f)
+ %y = freeze <8 x i1> %x
+ ret <8 x i1> %y
+}
+
+define <8 x i8> @test_signed_v8i8_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i8_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.28E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.27E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i8> @llvm.fptosi.sat.v8i8.v8f32(<8 x float> %f)
+ ret <8 x i8> %x
+}
+
+define <8 x i16> @test_signed_v8i16_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i16_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-3.2768E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [3.2767E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f32(<8 x float> %f)
+ ret <8 x i16> %x
+}
+
+define <8 x i32> @test_signed_v8i32_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i32_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vbroadcastss {{.*#+}} ymm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; CHECK-NEXT: vcmpleps %ymm0, %ymm1, %ymm1
+; CHECK-NEXT: vcvttps2dq %ymm0, %ymm2
+; CHECK-NEXT: vbroadcastss {{.*#+}} ymm3 = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT: vblendvps %ymm1, %ymm3, %ymm2, %ymm1
+; CHECK-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
+; CHECK-NEXT: vandnps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f32(<8 x float> %f)
+ ret <8 x i32> %x
+}
+
+define <8 x i64> @test_signed_v8i64_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i64_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm2, %rdx
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [9.22337149E+18,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: vucomiss %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vshufps {{.*#+}} xmm3 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm1
+; CHECK-NEXT: vmovdqa %ymm2, %ymm0
+; CHECK-NEXT: retq
+ %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %f)
+ ret <8 x i64> %x
+}
+
+define <8 x i128> @test_signed_v8i128_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i128_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $168, %rsp
+; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbp # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: movq $-1, %r13
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: movq %rbp, %r13
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %r13, %rbp
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rbp
+; CHECK-NEXT: movq %r15, %r13
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rbp
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %r14
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %r15
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r13, %r15
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %r14
+; CHECK-NEXT: cmovpq %r12, %r15
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %r13
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %r13
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %r12
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %r12
+; CHECK-NEXT: cmovpq %rax, %r13
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 72(%rbx)
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq %r13, 8(%rbx)
+; CHECK-NEXT: movq %r12, (%rbx)
+; CHECK-NEXT: movq %r15, 120(%rbx)
+; CHECK-NEXT: movq %r14, 112(%rbx)
+; CHECK-NEXT: movq %rbp, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $168, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <8 x i128> @llvm.fptosi.sat.v8i128.v8f32(<8 x float> %f)
+ ret <8 x i128> %x
+}
+
+;
+; 64-bit float to signed integer
+;
+
+declare <4 x i1> @llvm.fptosi.sat.v4i1.v4f64(<4 x double>)
+declare <4 x i8> @llvm.fptosi.sat.v4i8.v4f64(<4 x double>)
+declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f64(<4 x double>)
+declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>)
+declare <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double>)
+declare <4 x i128> @llvm.fptosi.sat.v4i128.v4f64(<4 x double>)
+
+define <4 x i1> @test_signed_v4i1_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i1_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm1
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
+; CHECK-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0]
+; CHECK-NEXT: vmaxpd %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminpd %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f64(<4 x double> %f)
+ ret <4 x i1> %x
+}
+
+define <4 x i8> @test_signed_v4i8_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [-1.28E+2,0.0E+0]
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [1.27E+2,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i8> @llvm.fptosi.sat.v4i8.v4f64(<4 x double> %f)
+ ret <4 x i8> %x
+}
+
+define <4 x i16> @test_signed_v4i16_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [-3.2768E+4,0.0E+0]
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [3.2767E+4,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f64(<4 x double> %f)
+ ret <4 x i16> %x
+}
+
+define <4 x i32> @test_signed_v4i32_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i32_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm1 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
+; CHECK-NEXT: vcmplepd %ymm0, %ymm1, %ymm1
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
+; CHECK-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm2
+; CHECK-NEXT: vbroadcastss {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT: vblendvps %xmm1, %xmm3, %xmm2, %xmm1
+; CHECK-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %f)
+ ret <4 x i32> %x
+}
+
+define <4 x i64> @test_signed_v4i64_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i64_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %rdx
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [9.2233720368547748E+18,0.0E+0]
+; CHECK-NEXT: vucomisd %xmm2, %xmm1
+; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: vucomisd %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm1, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm1
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm1
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
+; CHECK-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double> %f)
+ ret <4 x i64> %x
+}
+
+define <4 x i128> @test_signed_v4i128_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v4i128_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $88, %rsp
+; CHECK-NEXT: vmovupd %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %r15
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rbp, %r15
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %r15
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %r12
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %rbp, %r13
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r12
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %r12
+; CHECK-NEXT: cmovpq %r14, %r13
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rax, %rbp
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %rbp
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %r14
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %r14
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rbp
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %rbp
+; CHECK-NEXT: cmovpq %rax, %r14
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 40(%rbx)
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq %r14, 8(%rbx)
+; CHECK-NEXT: movq %rbp, (%rbx)
+; CHECK-NEXT: movq %r13, 56(%rbx)
+; CHECK-NEXT: movq %r12, 48(%rbx)
+; CHECK-NEXT: movq %r15, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $88, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <4 x i128> @llvm.fptosi.sat.v4i128.v4f64(<4 x double> %f)
+ ret <4 x i128> %x
+}
+
+;
+; 16-bit float to signed integer
+;
+
+declare <16 x i1> @llvm.fptosi.sat.v16i1.v16f16(<16 x half>)
+declare <16 x i8> @llvm.fptosi.sat.v16i8.v16f16(<16 x half>)
+declare <16 x i16> @llvm.fptosi.sat.v16i16.v16f16(<16 x half>)
+declare <16 x i32> @llvm.fptosi.sat.v16i32.v16f16(<16 x half>)
+declare <16 x i64> @llvm.fptosi.sat.v16i64.v16f16(<16 x half>)
+declare <16 x i128> @llvm.fptosi.sat.v16i128.v16f16(<16 x half>)
+
+define <16 x i1> @test_signed_v16i1_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i1_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $56, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ebp
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %ebp
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrb $1, %ebp, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; CHECK-NEXT: addq $56, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f16(<16 x half> %f)
+ ret <16 x i1> %x
+}
+
+define <16 x i8> @test_signed_v16i8_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i8_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $56, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ebp
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %ebp
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrb $1, %ebp, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; CHECK-NEXT: addq $56, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i8> @llvm.fptosi.sat.v16i8.v16f16(<16 x half> %f)
+ ret <16 x i8> %x
+}
+
+define <16 x i16> @test_signed_v16i16_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i16_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $72, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ebp
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %ebp
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrw $1, %ebp, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ebp
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %ebp
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrw $1, %ebp, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmaxss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %ebx, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: addq $72, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i16> @llvm.fptosi.sat.v16i16.v16f16(<16 x half> %f)
+ ret <16 x i16> %x
+}
+
+define <16 x i32> @test_signed_v16i32_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i32_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $104, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
+; CHECK-NEXT: cmovbl %ebx, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
+; CHECK-NEXT: cmoval %ebp, %r15d
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %r15d
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r15d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r15d
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %r15d
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r15d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r15d
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %r15d
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r15d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r15d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r15d
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %r15d
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r15d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %r14d, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, (%rsp), %ymm0, %ymm1 # 16-byte Folded Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: addq $104, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i32> @llvm.fptosi.sat.v16i32.v16f16(<16 x half> %f)
+ ret <16 x i32> %x
+}
+
+define <16 x i64> @test_signed_v16i64_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i64_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $160, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, (%rsp) # 32-byte Spill
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r14 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: xorl %r15d, %r15d
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r15, %rax
+; CHECK-NEXT: vmovq %rax, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm3 # 16-byte Folded Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload
+; CHECK-NEXT: addq $160, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: retq
+ %x = call <16 x i64> @llvm.fptosi.sat.v16i64.v16f16(<16 x half> %f)
+ ret <16 x i64> %x
+}
+
+define <16 x i128> @test_signed_v16i128_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i128_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $264, %rsp # imm = 0x108
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbp # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: movq $-1, %r12
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r12, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss (%rsp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r12
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %r14
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %r14
+; CHECK-NEXT: movq %r15, %rbp
+; CHECK-NEXT: cmovaq %r12, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %r14
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r15
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %r15
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %rbp, %r12
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %r15
+; CHECK-NEXT: cmovpq %r13, %r12
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rbp
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rbp
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %r13
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %r13
+; CHECK-NEXT: cmovpq %rax, %rbp
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 136(%rbx)
+; CHECK-NEXT: movq %rax, 128(%rbx)
+; CHECK-NEXT: movq %rbp, 8(%rbx)
+; CHECK-NEXT: movq %r13, (%rbx)
+; CHECK-NEXT: movq %r12, 248(%rbx)
+; CHECK-NEXT: movq %r15, 240(%rbx)
+; CHECK-NEXT: movq %r14, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 200(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 72(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $264, %rsp # imm = 0x108
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i128> @llvm.fptosi.sat.v16i128.v16f16(<16 x half> %f)
+ ret <16 x i128> %x
+}
diff --git a/llvm/test/CodeGen/X86/fptosi-sat-vector-512.ll b/llvm/test/CodeGen/X86/fptosi-sat-vector-512.ll
new file mode 100644
index 0000000000000..6c8100e14d2c7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fptosi-sat-vector-512.ll
@@ -0,0 +1,3601 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s
+
+;
+; 32-bit float to signed integer
+;
+
+declare <16 x i1> @llvm.fptosi.sat.v16i1.v16f32(<16 x float>)
+declare <16 x i8> @llvm.fptosi.sat.v16i8.v16f32(<16 x float>)
+declare <16 x i16> @llvm.fptosi.sat.v16i16.v16f32(<16 x float>)
+declare <16 x i32> @llvm.fptosi.sat.v16i32.v16f32(<16 x float>)
+declare <16 x i64> @llvm.fptosi.sat.v16i64.v16f32(<16 x float>)
+declare <16 x i128> @llvm.fptosi.sat.v16i128.v16f32(<16 x float>)
+
+define <16 x i1> @test_signed_v16i1_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i1_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f32(<16 x float> %f)
+ ret <16 x i1> %x
+}
+
+define <16 x i1> @test_freeze_signed_v16i1_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_freeze_signed_v16i1_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f32(<16 x float> %f)
+ %y = freeze <16 x i1> %x
+ ret <16 x i1> %y
+}
+
+define <16 x i8> @test_signed_v16i8_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i8_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.28E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.27E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i8> @llvm.fptosi.sat.v16i8.v16f32(<16 x float> %f)
+ ret <16 x i8> %x
+}
+
+define <16 x i16> @test_signed_v16i16_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i16_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm3[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-3.2768E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [3.2767E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vmaxss %xmm3, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm3, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm4, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <16 x i16> @llvm.fptosi.sat.v16i16.v16f32(<16 x float> %f)
+ ret <16 x i16> %x
+}
+
+define <16 x i32> @test_signed_v16i32_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i32_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcmpgeps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
+; CHECK-NEXT: vcvttps2dq %zmm0, %zmm1
+; CHECK-NEXT: vpbroadcastd {{.*#+}} zmm1 {%k1} = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT: vcmpunordps %zmm0, %zmm0, %k0
+; CHECK-NEXT: knotw %k0, %k1
+; CHECK-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %x = call <16 x i32> @llvm.fptosi.sat.v16i32.v16f32(<16 x float> %f)
+ ret <16 x i32> %x
+}
+
+define <16 x i64> @test_signed_v16i64_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i64_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm3 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [9.22337149E+18,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vcvttss2si %xmm2, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm2, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm4[0],xmm2[0]
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm3 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvttss2si %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm3, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm3[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm3, %ymm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2si %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2si %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2si %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm5[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm1
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %x = call <16 x i64> @llvm.fptosi.sat.v16i64.v16f32(<16 x float> %f)
+ ret <16 x i64> %x
+}
+
+define <16 x i128> @test_signed_v16i128_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_signed_v16i128_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $360, %rsp # imm = 0x168
+; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbp # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: movq $-1, %r12
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r12, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r12
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: cmovbq %rbp, %r14
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %r14
+; CHECK-NEXT: movq %r15, %rbp
+; CHECK-NEXT: cmovaq %r12, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r13, %r14
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r15
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r13, %r15
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %rbp, %r12
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r13, %r15
+; CHECK-NEXT: cmovpq %r13, %r12
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rbp
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rbp
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %r13
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %r13
+; CHECK-NEXT: cmovpq %rax, %rbp
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 200(%rbx)
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq %rbp, 136(%rbx)
+; CHECK-NEXT: movq %r13, 128(%rbx)
+; CHECK-NEXT: movq %r12, 72(%rbx)
+; CHECK-NEXT: movq %r15, 64(%rbx)
+; CHECK-NEXT: movq %r14, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 248(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 240(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $360, %rsp # imm = 0x168
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i128> @llvm.fptosi.sat.v16i128.v16f32(<16 x float> %f)
+ ret <16 x i128> %x
+}
+
+;
+; 64-bit float to signed integer
+;
+
+declare <8 x i1> @llvm.fptosi.sat.v8i1.v8f64(<8 x double>)
+declare <8 x i8> @llvm.fptosi.sat.v8i8.v8f64(<8 x double>)
+declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f64(<8 x double>)
+declare <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double>)
+declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double>)
+declare <8 x i128> @llvm.fptosi.sat.v8i128.v8f64(<8 x double>)
+
+define <8 x i1> @test_signed_v8i1_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i1_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [-1.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vpmovzxbq {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,xmm0[4],zero,zero,zero,zero,zero,zero,zero,xmm0[5],zero,zero,zero,zero,zero,zero,zero,xmm0[6],zero,zero,zero,zero,zero,zero,zero,xmm0[7],zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
+; CHECK-NEXT: vpmovm2w %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f64(<8 x double> %f)
+ ret <8 x i1> %x
+}
+
+define <8 x i8> @test_signed_v8i8_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i8_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [-1.28E+2,0.0E+0]
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [1.27E+2,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i8> @llvm.fptosi.sat.v8i8.v8f64(<8 x double> %f)
+ ret <8 x i8> %x
+}
+
+define <8 x i16> @test_signed_v8i16_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i16_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [-3.2768E+4,0.0E+0]
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [3.2767E+4,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f64(<8 x double> %f)
+ ret <8 x i16> %x
+}
+
+define <8 x i32> @test_signed_v8i32_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i32_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcmpgepd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
+; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm1
+; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 {%k1} = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT: vcmpunordpd %zmm0, %zmm0, %k0
+; CHECK-NEXT: knotb %k0, %k1
+; CHECK-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %x = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double> %f)
+ ret <8 x i32> %x
+}
+
+define <8 x i64> @test_signed_v8i64_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i64_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm2
+; CHECK-NEXT: vcvttsd2si %xmm2, %rdx
+; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547748E+18,0.0E+0]
+; CHECK-NEXT: vucomisd %xmm1, %xmm2
+; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: vucomisd %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm2, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm2
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vcvttsd2si %xmm3, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm3 = xmm3[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm3, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
+; CHECK-NEXT: vcvttsd2si %xmm3, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm3 = xmm3[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm3, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm3, %xmm3
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vcvttsd2si %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double> %f)
+ ret <8 x i64> %x
+}
+
+define <8 x i128> @test_signed_v8i128_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_signed_v8i128_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $216, %rsp
+; CHECK-NEXT: vmovupd %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbp # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: movq $-1, %r13
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovupd %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: movq %rbp, %r13
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: cmovbq %r13, %rbp
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rbp
+; CHECK-NEXT: movq %r15, %r13
+; CHECK-NEXT: cmovaq %r14, %rax
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r12, %rbp
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r12, %r14
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %r15
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r13, %r15
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r14
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r12, %r14
+; CHECK-NEXT: cmovpq %r12, %r15
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %r13
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %r13
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %r12
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %r12
+; CHECK-NEXT: cmovpq %rax, %r13
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixdfti at PLT
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomisd %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 104(%rbx)
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq %r13, 72(%rbx)
+; CHECK-NEXT: movq %r12, 64(%rbx)
+; CHECK-NEXT: movq %r15, 40(%rbx)
+; CHECK-NEXT: movq %r14, 32(%rbx)
+; CHECK-NEXT: movq %rbp, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $216, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <8 x i128> @llvm.fptosi.sat.v8i128.v8f64(<8 x double> %f)
+ ret <8 x i128> %x
+}
+
+;
+; 16-bit float to signed integer
+;
+
+declare <32 x i1> @llvm.fptosi.sat.v32i1.v32f16(<32 x half>)
+declare <32 x i8> @llvm.fptosi.sat.v32i8.v32f16(<32 x half>)
+declare <32 x i16> @llvm.fptosi.sat.v32i16.v32f16(<32 x half>)
+declare <32 x i32> @llvm.fptosi.sat.v32i32.v32f16(<32 x half>)
+declare <32 x i64> @llvm.fptosi.sat.v32i64.v32f16(<32 x half>)
+declare <32 x i128> @llvm.fptosi.sat.v32i128.v32f16(<32 x half>)
+
+define <32 x i1> @test_signed_v32i1_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i1_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $2, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $3, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $4, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $5, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $6, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $7, %ecx, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $8, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $9, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $10, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $11, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $12, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $13, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $14, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $15, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $2, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $3, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $4, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $5, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $6, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $7, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $8, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $9, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $10, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $11, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $12, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $13, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm6, %xmm2, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $14, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; CHECK-NEXT: vminss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ecx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $15, %ecx, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <32 x i1> @llvm.fptosi.sat.v32i1.v32f16(<32 x half> %f)
+ ret <32 x i1> %x
+}
+
+define <32 x i8> @test_signed_v32i8_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i8_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-1.28E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.27E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $2, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $3, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $4, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $5, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $6, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $7, %ecx, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $8, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $9, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $10, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $11, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $12, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $13, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $14, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $15, %ecx, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $2, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $3, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $4, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $5, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $6, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $7, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $8, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $9, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $10, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $11, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $12, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $13, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $14, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; CHECK-NEXT: vminss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ecx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrb $15, %ecx, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <32 x i8> @llvm.fptosi.sat.v32i8.v32f16(<32 x half> %f)
+ ret <32 x i8> %x
+}
+
+define <32 x i16> @test_signed_v32i16_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i16_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-3.2768E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [3.2767E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $2, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $3, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $4, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $5, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $6, %ecx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vucomiss %xmm3, %xmm3
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $7, %ecx, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $2, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $3, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $4, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $5, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $6, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $7, %ecx, %xmm5, %xmm4
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $2, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $3, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $4, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $5, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $6, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $7, %ecx, %xmm5, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %ecx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %eax, %edx
+; CHECK-NEXT: vmovd %edx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $2, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $3, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $4, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $5, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vminss %xmm2, %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %ecx
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $6, %ecx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; CHECK-NEXT: vminss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %ecx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %eax, %ecx
+; CHECK-NEXT: vpinsrw $7, %ecx, %xmm5, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %x = call <32 x i16> @llvm.fptosi.sat.v32i16.v32f16(<32 x half> %f)
+ ret <32 x i16> %x
+}
+
+define <32 x i32> @test_signed_v32i32_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i32_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %esi
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [-2.14748365E+9,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vmovss {{.*#+}} xmm3 = [2.14748352E+9,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm4
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm2, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm2, %xmm2
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm2
+; CHECK-NEXT: vcvttss2si %xmm2, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm2, %xmm2
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm5, %xmm2
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm4
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm4, %zmm2
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm6
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm6, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm7
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm6, %xmm6
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm4, %xmm4
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm6, %xmm4
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm4, %ymm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm5, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %edi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpl %edx, %edi
+; CHECK-NEXT: vmovd %edi, %xmm6
+; CHECK-NEXT: vpinsrd $1, %esi, %xmm6, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm7
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $2, %esi, %xmm6, %xmm6
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpl %edx, %esi
+; CHECK-NEXT: vpinsrd $3, %esi, %xmm6, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm1
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %x = call <32 x i32> @llvm.fptosi.sat.v32i32.v32f16(<32 x half> %f)
+ ret <32 x i32> %x
+}
+
+define <32 x i64> @test_signed_v32i64_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i64_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovapd %zmm0, %zmm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %rsi
+; CHECK-NEXT: vmovss {{.*#+}} xmm3 = [-9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vmovss {{.*#+}} xmm4 = [9.22337149E+18,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm4, %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm0
+; CHECK-NEXT: vshufps {{.*#+}} xmm1 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm1
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm2[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm5[0],xmm1[0]
+; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT: vpsrlq $48, %xmm2, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm1
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm5[0],xmm1[0]
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm2, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm5, %ymm1
+; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm1
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm1[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vshufpd {{.*#+}} xmm7 = xmm1[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5
+; CHECK-NEXT: vpsrlq $48, %xmm1, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm1[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpsrld $16, %xmm1, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm1, %xmm1
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm1
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm7[0],xmm1[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm1, %ymm1
+; CHECK-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1
+; CHECK-NEXT: vextractf64x4 $1, %zmm2, %ymm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm2 = xmm5[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm2
+; CHECK-NEXT: vcvttss2si %xmm2, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm2
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm2, %xmm2
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm5[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm6[0],xmm2[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vshufpd {{.*#+}} xmm7 = xmm5[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2
+; CHECK-NEXT: vpsrlq $48, %xmm5, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm5[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpsrld $16, %xmm5, %xmm8
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2si %xmm8, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm8, %xmm8
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm6, %zmm2
+; CHECK-NEXT: vextractf128 $1, %ymm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm5[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm6, %xmm6
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm6
+; CHECK-NEXT: vshufps {{.*#+}} xmm7 = xmm5[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm7 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vshufpd {{.*#+}} xmm8 = xmm5[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2si %xmm8, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm8, %xmm8
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm8[0],xmm7[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6
+; CHECK-NEXT: vpsrlq $48, %xmm5, %xmm7
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm7, %xmm7
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm7
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm8 = xmm5[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2si %xmm8, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm8, %xmm8
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm8[0],xmm7[0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm8
+; CHECK-NEXT: vcvttss2si %xmm8, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm8, %xmm8
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm8
+; CHECK-NEXT: vpsrld $16, %xmm5, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rsi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rsi
+; CHECK-NEXT: vucomiss %xmm5, %xmm5
+; CHECK-NEXT: cmovpq %rdx, %rsi
+; CHECK-NEXT: vmovq %rsi, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm8[0],xmm3[0]
+; CHECK-NEXT: vinserti128 $1, %xmm7, %ymm3, %ymm3
+; CHECK-NEXT: vinserti64x4 $1, %ymm6, %zmm3, %zmm3
+; CHECK-NEXT: retq
+ %x = call <32 x i64> @llvm.fptosi.sat.v32i64.v32f16(<32 x half> %f)
+ ret <32 x i64> %x
+}
+
+define <32 x i128> @test_signed_v32i128_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_signed_v32i128_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $648, %rsp # imm = 0x288
+; CHECK-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: movabsq $-9223372036854775808, %rbp # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %r12 # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: movq $-1, %r13
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r12, %rdx
+; CHECK-NEXT: movq %r12, %r13
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: cmovbq %rbp, %r12
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r13, %r12
+; CHECK-NEXT: movq %r13, %r15
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovpq %r14, %r12
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovbq %r14, %r13
+; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rax, %rbp
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r15, %rbp
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r13
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %r14, %r13
+; CHECK-NEXT: cmovpq %r14, %rbp
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r14
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %r15
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %r15
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %r14
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rax, %r14
+; CHECK-NEXT: cmovpq %rax, %r15
+; CHECK-NEXT: vcvtph2ps (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixsfti at PLT
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movl $0, %esi
+; CHECK-NEXT: cmovbq %rsi, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rax
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovpq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 392(%rbx)
+; CHECK-NEXT: movq %rax, 384(%rbx)
+; CHECK-NEXT: movq %r15, 264(%rbx)
+; CHECK-NEXT: movq %r14, 256(%rbx)
+; CHECK-NEXT: movq %rbp, 136(%rbx)
+; CHECK-NEXT: movq %r13, 128(%rbx)
+; CHECK-NEXT: movq %r12, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 504(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 496(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 488(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 480(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 472(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 464(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 456(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 448(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 440(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 432(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 424(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 416(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 408(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 400(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 376(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 368(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 360(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 352(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 344(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 336(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 328(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 320(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 312(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 304(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 296(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 288(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 280(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 272(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 248(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 240(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 200(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 72(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $648, %rsp # imm = 0x288
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <32 x i128> @llvm.fptosi.sat.v32i128.v32f16(<32 x half> %f)
+ ret <32 x i128> %x
+}
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-vector-256.ll b/llvm/test/CodeGen/X86/fptoui-sat-vector-256.ll
new file mode 100644
index 0000000000000..a5f817b910cfb
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fptoui-sat-vector-256.ll
@@ -0,0 +1,2204 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s
+
+;
+; 32-bit float to unsigned integer
+;
+
+declare <8 x i1> @llvm.fptoui.sat.v8i1.v8f32(<8 x float>)
+declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f32(<8 x float>)
+declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f32(<8 x float>)
+declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float>)
+declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float>)
+declare <8 x i128> @llvm.fptoui.sat.v8i128.v8f32(<8 x float>)
+
+define <8 x i1> @test_unsigned_v8i1_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i1_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f32(<8 x float> %f)
+ ret <8 x i1> %x
+}
+
+define <8 x i1> @test_freeze_unsigned_v8i1_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_freeze_unsigned_v8i1_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f32(<8 x float> %f)
+ %y = freeze <8 x i1> %x
+ ret <8 x i1> %y
+}
+
+define <8 x i8> @test_unsigned_v8i8_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i8_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i8> @llvm.fptoui.sat.v8i8.v8f32(<8 x float> %f)
+ ret <8 x i8> %x
+}
+
+define <8 x i16> @test_unsigned_v8i16_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i16_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [6.5535E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f32(<8 x float> %f)
+ ret <8 x i16> %x
+}
+
+define <8 x i32> @test_unsigned_v8i32_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i32_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1
+; CHECK-NEXT: vpsrad $31, %ymm1, %ymm2
+; CHECK-NEXT: vbroadcastss {{.*#+}} ymm3 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; CHECK-NEXT: vsubps %ymm3, %ymm0, %ymm3
+; CHECK-NEXT: vcvttps2dq %ymm3, %ymm3
+; CHECK-NEXT: vpand %ymm2, %ymm3, %ymm2
+; CHECK-NEXT: vpor %ymm2, %ymm1, %ymm1
+; CHECK-NEXT: vbroadcastss {{.*#+}} ymm2 = [4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9,4.2949673E+9]
+; CHECK-NEXT: vcmpleps %ymm0, %ymm2, %ymm0
+; CHECK-NEXT: vorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float> %f)
+ ret <8 x i32> %x
+}
+
+define <8 x i64> @test_unsigned_v8i64_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i64_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vsubss %xmm1, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %rax
+; CHECK-NEXT: vcvttss2si %xmm2, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vmovss {{.*#+}} xmm4 = [1.8446743E+19,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm4, %xmm2
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vsubss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rdx
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm5[0],xmm2[0]
+; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %rdx
+; CHECK-NEXT: vcvttss2si %xmm0, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vsubss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rdx
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm5, %ymm2
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vsubss %xmm1, %xmm5, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rdx
+; CHECK-NEXT: vcvttss2si %xmm5, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm0[1,0]
+; CHECK-NEXT: vsubss %xmm1, %xmm6, %xmm7
+; CHECK-NEXT: vcvttss2si %xmm7, %rdx
+; CHECK-NEXT: vcvttss2si %xmm6, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0]
+; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %rdx
+; CHECK-NEXT: vcvttss2si %xmm0, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rdx
+; CHECK-NEXT: vcvttss2si %xmm0, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomiss %xmm4, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm6[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm1
+; CHECK-NEXT: vmovdqa %ymm2, %ymm0
+; CHECK-NEXT: retq
+ %x = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %f)
+ ret <8 x i64> %x
+}
+
+define <8 x i128> @test_unsigned_v8i128_v8f32(<8 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i128_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $168, %rsp
+; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %r13
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rbp
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rbp
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %r15
+; CHECK-NEXT: cmovbq %r12, %r14
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %r14
+; CHECK-NEXT: cmovaq %r13, %r15
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r12
+; CHECK-NEXT: cmovaq %rax, %r13
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 72(%rbx)
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq %r13, 8(%rbx)
+; CHECK-NEXT: movq %r12, (%rbx)
+; CHECK-NEXT: movq %r15, 120(%rbx)
+; CHECK-NEXT: movq %r14, 112(%rbx)
+; CHECK-NEXT: movq %rbp, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $168, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <8 x i128> @llvm.fptoui.sat.v8i128.v8f32(<8 x float> %f)
+ ret <8 x i128> %x
+}
+
+;
+; 64-bit float to unsigned integer
+;
+
+declare <4 x i1> @llvm.fptoui.sat.v4i1.v4f64(<4 x double>)
+declare <4 x i8> @llvm.fptoui.sat.v4i8.v4f64(<4 x double>)
+declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f64(<4 x double>)
+declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>)
+declare <4 x i64> @llvm.fptoui.sat.v4i64.v4f64(<4 x double>)
+declare <4 x i128> @llvm.fptoui.sat.v4i128.v4f64(<4 x double>)
+
+define <4 x i1> @test_unsigned_v4i1_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i1_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; CHECK-NEXT: vminpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f64(<4 x double> %f)
+ ret <4 x i1> %x
+}
+
+define <4 x i8> @test_unsigned_v4i8_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i8_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [2.55E+2,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i8> @llvm.fptoui.sat.v4i8.v4f64(<4 x double> %f)
+ ret <4 x i8> %x
+}
+
+define <4 x i16> @test_unsigned_v4i16_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i16_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [6.5535E+4,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f64(<4 x double> %f)
+ ret <4 x i16> %x
+}
+
+define <4 x i32> @test_unsigned_v4i32_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i32_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.294967296E+9,4.294967296E+9,4.294967296E+9,4.294967296E+9]
+; CHECK-NEXT: vcmplepd %ymm0, %ymm1, %ymm1
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
+; CHECK-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm2
+; CHECK-NEXT: vpsrad $31, %xmm2, %xmm3
+; CHECK-NEXT: vbroadcastsd {{.*#+}} ymm4 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
+; CHECK-NEXT: vsubpd %ymm4, %ymm0, %ymm0
+; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
+; CHECK-NEXT: vandpd %xmm3, %xmm0, %xmm0
+; CHECK-NEXT: vorpd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %f)
+ ret <4 x i32> %x
+}
+
+define <4 x i64> @test_unsigned_v4i64_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i64_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
+; CHECK-NEXT: vsubsd %xmm1, %xmm4, %xmm2
+; CHECK-NEXT: vcvttsd2si %xmm2, %rax
+; CHECK-NEXT: vcvttsd2si %xmm4, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [1.844674407370955E+19,0.0E+0]
+; CHECK-NEXT: vucomisd %xmm3, %xmm4
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vsubsd %xmm1, %xmm4, %xmm6
+; CHECK-NEXT: vcvttsd2si %xmm6, %rdx
+; CHECK-NEXT: vcvttsd2si %xmm4, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomisd %xmm3, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vsubsd %xmm1, %xmm0, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %rdx
+; CHECK-NEXT: vcvttsd2si %xmm0, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomisd %xmm3, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vsubsd %xmm1, %xmm0, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %rdx
+; CHECK-NEXT: vcvttsd2si %xmm0, %rsi
+; CHECK-NEXT: movq %rsi, %rdi
+; CHECK-NEXT: sarq $63, %rdi
+; CHECK-NEXT: andq %rdx, %rdi
+; CHECK-NEXT: orq %rsi, %rdi
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdi
+; CHECK-NEXT: vucomisd %xmm3, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdi
+; CHECK-NEXT: vmovq %rdi, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm5[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f64(<4 x double> %f)
+ ret <4 x i64> %x
+}
+
+define <4 x i128> @test_unsigned_v4i128_v4f64(<4 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v4i128_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $88, %rsp
+; CHECK-NEXT: vmovupd %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %r15
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rbp
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %r15
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %r13
+; CHECK-NEXT: cmovbq %r14, %r12
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %r12
+; CHECK-NEXT: cmovaq %rbp, %r13
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rax, %rbp
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomisd %xmm1, %xmm0
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r14
+; CHECK-NEXT: cmovbq %rax, %rbp
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %rbp
+; CHECK-NEXT: cmovaq %rax, %r14
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 40(%rbx)
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq %r14, 8(%rbx)
+; CHECK-NEXT: movq %rbp, (%rbx)
+; CHECK-NEXT: movq %r13, 56(%rbx)
+; CHECK-NEXT: movq %r12, 48(%rbx)
+; CHECK-NEXT: movq %r15, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $88, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <4 x i128> @llvm.fptoui.sat.v4i128.v4f64(<4 x double> %f)
+ ret <4 x i128> %x
+}
+
+;
+; 16-bit float to unsigned integer
+;
+
+declare <16 x i1> @llvm.fptoui.sat.v16i1.v16f16(<16 x half>)
+declare <16 x i8> @llvm.fptoui.sat.v16i8.v16f16(<16 x half>)
+declare <16 x i16> @llvm.fptoui.sat.v16i16.v16f16(<16 x half>)
+declare <16 x i32> @llvm.fptoui.sat.v16i32.v16f16(<16 x half>)
+declare <16 x i64> @llvm.fptoui.sat.v16i64.v16f16(<16 x half>)
+declare <16 x i128> @llvm.fptoui.sat.v16i128.v16f16(<16 x half>)
+
+define <16 x i1> @test_unsigned_v16i1_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i1_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $48, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ebx
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrb $1, %ebx, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; CHECK-NEXT: addq $48, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f16(<16 x half> %f)
+ ret <16 x i1> %x
+}
+
+define <16 x i8> @test_unsigned_v16i8_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i8_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $48, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ebx
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrb $1, %ebx, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; CHECK-NEXT: addq $48, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %x = call <16 x i8> @llvm.fptoui.sat.v16i8.v16f16(<16 x half> %f)
+ ret <16 x i8> %x
+}
+
+define <16 x i16> @test_unsigned_v16i16_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i16_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $64, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ebx
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrw $1, %ebx, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %ebx
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrw $1, %ebx, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: addq $64, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %x = call <16 x i16> @llvm.fptoui.sat.v16i16.v16f16(<16 x half> %f)
+ ret <16 x i16> %x
+}
+
+define <16 x i32> @test_unsigned_v16i32_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i32_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $96, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r14
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r14d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movl $-1, %ebp
+; CHECK-NEXT: cmoval %ebp, %r14d
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r14d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r14
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r14d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r14d
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r14d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r14
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r14d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r14d
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r14d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %r14
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %r14d
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %r14d
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpinsrd $1, %r14d, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vcvttss2si %xmm0, %rax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %ebx, %eax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmoval %ebp, %eax
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
+; CHECK-NEXT: vinserti128 $1, (%rsp), %ymm0, %ymm1 # 16-byte Folded Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: addq $96, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i32> @llvm.fptoui.sat.v16i32.v16f16(<16 x half> %f)
+ ret <16 x i32> %x
+}
+
+define <16 x i64> @test_unsigned_v16i64_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i64_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $168, %rsp
+; CHECK-NEXT: vmovdqu %ymm0, (%rsp) # 32-byte Spill
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: movq $-1, %r14
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqu (%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vcvttss2si %xmm1, %rax
+; CHECK-NEXT: vcvttss2si %xmm0, %rcx
+; CHECK-NEXT: movq %rcx, %rdx
+; CHECK-NEXT: sarq $63, %rdx
+; CHECK-NEXT: andq %rax, %rdx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rbx, %rdx
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmovaq %r14, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
+; CHECK-NEXT: vinserti128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm3 # 16-byte Folded Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload
+; CHECK-NEXT: addq $168, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: retq
+ %x = call <16 x i64> @llvm.fptoui.sat.v16i64.v16f16(<16 x half> %f)
+ ret <16 x i64> %x
+}
+
+define <16 x i128> @test_unsigned_v16i128_v16f16(<16 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i128_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $264, %rsp # imm = 0x108
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rbp
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, (%rsp) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, (%rsp) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss (%rsp), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %r14
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %r14
+; CHECK-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r15
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %r12
+; CHECK-NEXT: cmovbq %r13, %r15
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %r15
+; CHECK-NEXT: cmovaq %rbp, %r12
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %rbp
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r13
+; CHECK-NEXT: cmovaq %rax, %rbp
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: callq __extendhfsf2 at PLT
+; CHECK-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
+; CHECK-NEXT: # xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 136(%rbx)
+; CHECK-NEXT: movq %rax, 128(%rbx)
+; CHECK-NEXT: movq %rbp, 8(%rbx)
+; CHECK-NEXT: movq %r13, (%rbx)
+; CHECK-NEXT: movq %r12, 248(%rbx)
+; CHECK-NEXT: movq %r15, 240(%rbx)
+; CHECK-NEXT: movq %r14, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 200(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 72(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $264, %rsp # imm = 0x108
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i128> @llvm.fptoui.sat.v16i128.v16f16(<16 x half> %f)
+ ret <16 x i128> %x
+}
diff --git a/llvm/test/CodeGen/X86/fptoui-sat-vector-512.ll b/llvm/test/CodeGen/X86/fptoui-sat-vector-512.ll
new file mode 100644
index 0000000000000..c28959ac8e44e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fptoui-sat-vector-512.ll
@@ -0,0 +1,3094 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s
+
+;
+; 32-bit float to unsigned integer
+;
+
+declare <16 x i1> @llvm.fptoui.sat.v16i1.v16f32(<16 x float>)
+declare <16 x i8> @llvm.fptoui.sat.v16i8.v16f32(<16 x float>)
+declare <16 x i16> @llvm.fptoui.sat.v16i16.v16f32(<16 x float>)
+declare <16 x i32> @llvm.fptoui.sat.v16i32.v16f32(<16 x float>)
+declare <16 x i64> @llvm.fptoui.sat.v16i64.v16f32(<16 x float>)
+declare <16 x i128> @llvm.fptoui.sat.v16i128.v16f32(<16 x float>)
+
+define <16 x i1> @test_unsigned_v16i1_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i1_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f32(<16 x float> %f)
+ ret <16 x i1> %x
+}
+
+define <16 x i1> @test_freeze_unsigned_v16i1_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_freeze_unsigned_v16i1_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f32(<16 x float> %f)
+ %y = freeze <16 x i1> %x
+ ret <16 x i1> %y
+}
+
+define <16 x i8> @test_unsigned_v16i8_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i8_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm3
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm3
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <16 x i8> @llvm.fptoui.sat.v16i8.v16f32(<16 x float> %f)
+ ret <16 x i8> %x
+}
+
+define <16 x i16> @test_unsigned_v16i16_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i16_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm3[1,1,3,3]
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm2, %xmm1, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [6.5535E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vmaxss %xmm3, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm3, %xmm1, %xmm3
+; CHECK-NEXT: vminss %xmm3, %xmm2, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm4, %xmm3
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm4, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm4
+; CHECK-NEXT: vminss %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vmaxss %xmm5, %xmm1, %xmm5
+; CHECK-NEXT: vminss %xmm5, %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vminss %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <16 x i16> @llvm.fptoui.sat.v16i16.v16f32(<16 x float> %f)
+ ret <16 x i16> %x
+}
+
+define <16 x i32> @test_unsigned_v16i32_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i32_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxps %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vcmpgeps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
+; CHECK-NEXT: vcvttps2udq %zmm0, %zmm0
+; CHECK-NEXT: vpternlogd {{.*#+}} zmm1 = -1
+; CHECK-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
+; CHECK-NEXT: retq
+ %x = call <16 x i32> @llvm.fptoui.sat.v16i32.v16f32(<16 x float> %f)
+ ret <16 x i32> %x
+}
+
+define <16 x i64> @test_unsigned_v16i64_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i64_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm4, %rdx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vmovss {{.*#+}} xmm3 = [1.8446743E+19,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm2[1,0]
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vcvttss2usi %xmm2, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm2, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm5[0],xmm2[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vcvttss2usi %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm4, %zmm2
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0]
+; CHECK-NEXT: vcvttss2usi %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm4 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm4, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm6[0],xmm4[0]
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm4, %ymm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm0[1,0]
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0]
+; CHECK-NEXT: vcvttss2usi %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvttss2usi %xmm0, %rdx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm6[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm1
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %x = call <16 x i64> @llvm.fptoui.sat.v16i64.v16f32(<16 x float> %f)
+ ret <16 x i64> %x
+}
+
+define <16 x i128> @test_unsigned_v16i128_v16f32(<16 x float> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v16i128_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $360, %rsp # imm = 0x168
+; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: xorl %r13d, %r13d
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rbp
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %rdx
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rdx, %r14
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %r14
+; CHECK-NEXT: cmovbq %r13, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %rbp, %r14
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r15
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r13, %r12
+; CHECK-NEXT: cmovbq %r13, %r15
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %rbp, %r15
+; CHECK-NEXT: cmovaq %rbp, %r12
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %rbp
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r13
+; CHECK-NEXT: cmovaq %rax, %rbp
+; CHECK-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 200(%rbx)
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq %rbp, 136(%rbx)
+; CHECK-NEXT: movq %r13, 128(%rbx)
+; CHECK-NEXT: movq %r12, 72(%rbx)
+; CHECK-NEXT: movq %r15, 64(%rbx)
+; CHECK-NEXT: movq %r14, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 248(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 240(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $360, %rsp # imm = 0x168
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <16 x i128> @llvm.fptoui.sat.v16i128.v16f32(<16 x float> %f)
+ ret <16 x i128> %x
+}
+
+;
+; 64-bit float to unsigned integer
+;
+
+declare <8 x i1> @llvm.fptoui.sat.v8i1.v8f64(<8 x double>)
+declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double>)
+declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f64(<8 x double>)
+declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double>)
+declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double>)
+declare <8 x i128> @llvm.fptoui.sat.v8i128.v8f64(<8 x double>)
+
+define <8 x i1> @test_unsigned_v8i1_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i1_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [1.0E+0,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vpmovzxbq {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,xmm0[4],zero,zero,zero,zero,zero,zero,zero,xmm0[5],zero,zero,zero,zero,zero,zero,zero,xmm0[6],zero,zero,zero,zero,zero,zero,zero,xmm0[7],zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k0
+; CHECK-NEXT: vpmovm2w %k0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f64(<8 x double> %f)
+ ret <8 x i1> %x
+}
+
+define <8 x i8> @test_unsigned_v8i8_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i8_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [2.55E+2,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double> %f)
+ ret <8 x i8> %x
+}
+
+define <8 x i16> @test_unsigned_v8i16_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i16_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vmaxsd %xmm1, %xmm2, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = [6.5535E+4,0.0E+0]
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %eax
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vminsd %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vcvttsd2si %xmm1, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm1
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm5
+; CHECK-NEXT: vminsd %xmm5, %xmm3, %xmm5
+; CHECK-NEXT: vcvttsd2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vmaxsd %xmm4, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm4
+; CHECK-NEXT: vminsd %xmm4, %xmm3, %xmm4
+; CHECK-NEXT: vcvttsd2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; CHECK-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; CHECK-NEXT: vcvttsd2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm1, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %x = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f64(<8 x double> %f)
+ ret <8 x i16> %x
+}
+
+define <8 x i32> @test_unsigned_v8i32_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i32_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxpd %zmm1, %zmm0, %zmm1
+; CHECK-NEXT: vcvttpd2dq %zmm1, %ymm2
+; CHECK-NEXT: vpsrad $31, %ymm2, %ymm3
+; CHECK-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm0
+; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm0
+; CHECK-NEXT: vpternlogd {{.*#+}} ymm0 = (ymm0 & ymm3) | ymm2
+; CHECK-NEXT: vcmpgepd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %k1
+; CHECK-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; CHECK-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1}
+; CHECK-NEXT: retq
+ %x = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double> %f)
+ ret <8 x i32> %x
+}
+
+define <8 x i64> @test_unsigned_v8i64_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i64_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm3
+; CHECK-NEXT: vcvttsd2usi %xmm3, %rdx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = [1.844674407370955E+19,0.0E+0]
+; CHECK-NEXT: vucomisd %xmm2, %xmm3
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm3 = xmm3[1,0]
+; CHECK-NEXT: vcvttsd2usi %xmm3, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm3
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm3
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vcvttsd2usi %xmm4, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vcvttsd2usi %xmm4, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vcvttsd2usi %xmm4, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
+; CHECK-NEXT: vcvttsd2usi %xmm4, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm4
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm4
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm4
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
+; CHECK-NEXT: vcvttsd2usi %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vcvttsd2usi %xmm0, %rdx
+; CHECK-NEXT: vucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomisd %xmm2, %xmm0
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm5[0],xmm0[0]
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %x = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double> %f)
+ ret <8 x i64> %x
+}
+
+define <8 x i128> @test_unsigned_v8i128_v8f64(<8 x double> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v8i128_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $216, %rsp
+; CHECK-NEXT: vmovupd %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: xorl %r12d, %r12d
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %r13
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovupd %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT: vmovapd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rdx
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %rbp
+; CHECK-NEXT: cmovbq %r12, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r13, %rbp
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r12, %r15
+; CHECK-NEXT: cmovbq %r12, %r14
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r13, %r14
+; CHECK-NEXT: cmovaq %r13, %r15
+; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: movq %rax, %r12
+; CHECK-NEXT: movq %rdx, %r13
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r13
+; CHECK-NEXT: cmovbq %rax, %r12
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r12
+; CHECK-NEXT: cmovaq %rax, %r13
+; CHECK-NEXT: vmovapd (%rsp), %xmm0 # 16-byte Reload
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunsdfti at PLT
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomisd %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 104(%rbx)
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq %r13, 72(%rbx)
+; CHECK-NEXT: movq %r12, 64(%rbx)
+; CHECK-NEXT: movq %r15, 40(%rbx)
+; CHECK-NEXT: movq %r14, 32(%rbx)
+; CHECK-NEXT: movq %rbp, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $216, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <8 x i128> @llvm.fptoui.sat.v8i128.v8f64(<8 x double> %f)
+ ret <8 x i128> %x
+}
+
+;
+; 16-bit float to unsigned integer
+;
+
+declare <32 x i1> @llvm.fptoui.sat.v32i1.v32f16(<32 x half>)
+declare <32 x i8> @llvm.fptoui.sat.v32i8.v32f16(<32 x half>)
+declare <32 x i16> @llvm.fptoui.sat.v32i16.v32f16(<32 x half>)
+declare <32 x i32> @llvm.fptoui.sat.v32i32.v32f16(<32 x half>)
+declare <32 x i64> @llvm.fptoui.sat.v32i64.v32f16(<32 x half>)
+declare <32 x i128> @llvm.fptoui.sat.v32i128.v32f16(<32 x half>)
+
+define <32 x i1> @test_unsigned_v32i1_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i1_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm2
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm2, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm3
+; CHECK-NEXT: vminss %xmm2, %xmm3, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: vptestmb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k0
+; CHECK-NEXT: vpmovm2b %k0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <32 x i1> @llvm.fptoui.sat.v32i1.v32f16(<32 x half> %f)
+ ret <32 x i1> %x
+}
+
+define <32 x i8> @test_unsigned_v32i8_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i8_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm2
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm2, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm3
+; CHECK-NEXT: vminss %xmm2, %xmm3, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm3, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $8, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $9, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $10, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $11, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $12, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $13, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrb $14, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrb $15, %eax, %xmm4, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %x = call <32 x i8> @llvm.fptoui.sat.v32i8.v32f16(<32 x half> %f)
+ ret <32 x i8> %x
+}
+
+define <32 x i16> @test_unsigned_v32i16_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i16_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm3
+; CHECK-NEXT: vpsrld $16, %xmm3, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm2
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmaxss %xmm1, %xmm2, %xmm4
+; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [6.5535E+4,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm4
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrlq $48, %xmm3, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm3[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm3, %xmm3
+; CHECK-NEXT: vmaxss %xmm1, %xmm3, %xmm3
+; CHECK-NEXT: vminss %xmm2, %xmm3, %xmm3
+; CHECK-NEXT: vcvttss2si %xmm3, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm4, %xmm3
+; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm5, %xmm4
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vmaxss %xmm1, %xmm4, %xmm4
+; CHECK-NEXT: vminss %xmm2, %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2si %xmm4, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm5, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %eax
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vmaxss %xmm1, %xmm5, %xmm5
+; CHECK-NEXT: vminss %xmm2, %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2si %xmm5, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm5
+; CHECK-NEXT: vpinsrw $1, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $2, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $3, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufpd {{.*#+}} xmm6 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $4, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $5, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vmaxss %xmm1, %xmm6, %xmm6
+; CHECK-NEXT: vminss %xmm2, %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2si %xmm6, %eax
+; CHECK-NEXT: vpinsrw $6, %eax, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vminss %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2si %xmm0, %eax
+; CHECK-NEXT: vpinsrw $7, %eax, %xmm5, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %x = call <32 x i16> @llvm.fptoui.sat.v32i16.v32f16(<32 x half> %f)
+ ret <32 x i16> %x
+}
+
+define <32 x i32> @test_unsigned_v32i32_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i32_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm4
+; CHECK-NEXT: vcvttss2usi %xmm4, %edx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vmovss {{.*#+}} xmm3 = [4.29496704E+9,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: movl $-1, %ecx
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2usi %xmm4, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm4
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm2, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm2, %xmm2
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm2
+; CHECK-NEXT: vcvttss2usi %xmm2, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm5, %xmm2
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm4 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2usi %xmm4, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2usi %xmm4, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm4
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm4, %xmm4
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm6 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm4, %zmm2
+; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm4[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm4[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm4[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm4, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm6
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm6, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm4[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm7
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm6, %xmm6
+; CHECK-NEXT: vpsrlq $48, %xmm4, %xmm4
+; CHECK-NEXT: vcvtph2ps %xmm4, %xmm4
+; CHECK-NEXT: vcvttss2usi %xmm4, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm4
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm4
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm6, %xmm4
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm4, %ymm4
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm0[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm5
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm5
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm0[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm5, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %esi
+; CHECK-NEXT: vucomiss %xmm1, %xmm6
+; CHECK-NEXT: cmovbl %eax, %esi
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmoval %ecx, %esi
+; CHECK-NEXT: vmovd %esi, %xmm6
+; CHECK-NEXT: vpinsrd $1, %edx, %xmm6, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm0[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm7
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $2, %edx, %xmm6, %xmm6
+; CHECK-NEXT: vpsrlq $48, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2usi %xmm0, %edx
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: cmovbl %eax, %edx
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmoval %ecx, %edx
+; CHECK-NEXT: vpinsrd $3, %edx, %xmm6, %xmm0
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm1
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %x = call <32 x i32> @llvm.fptoui.sat.v32i32.v32f16(<32 x half> %f)
+ ret <32 x i32> %x
+}
+
+define <32 x i64> @test_unsigned_v32i64_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i64_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovapd %zmm0, %zmm2
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vcvttss2usi %xmm0, %rdx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; CHECK-NEXT: vucomiss %xmm3, %xmm0
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vmovss {{.*#+}} xmm4 = [1.8446743E+19,0.0E+0,0.0E+0,0.0E+0]
+; CHECK-NEXT: vucomiss %xmm4, %xmm0
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm0
+; CHECK-NEXT: vshufps {{.*#+}} xmm1 = xmm2[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2usi %xmm1, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm1
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm1 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2usi %xmm1, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm1
+; CHECK-NEXT: vshufpd {{.*#+}} xmm5 = xmm2[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm5[0],xmm1[0]
+; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT: vpsrlq $48, %xmm2, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2usi %xmm1, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm1
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm5[0],xmm1[0]
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vpsrld $16, %xmm2, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm5, %ymm1
+; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm1
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm5 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm5
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm1[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vshufpd {{.*#+}} xmm7 = xmm1[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5
+; CHECK-NEXT: vpsrlq $48, %xmm1, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm1[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpsrld $16, %xmm1, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm1
+; CHECK-NEXT: vcvttss2usi %xmm1, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm1
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm1
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm1
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm7[0],xmm1[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm1, %ymm1
+; CHECK-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1
+; CHECK-NEXT: vextractf64x4 $1, %zmm2, %ymm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm2 = xmm5[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm2, %xmm2
+; CHECK-NEXT: vcvttss2usi %xmm2, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm2
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm2
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm2
+; CHECK-NEXT: vshufps {{.*#+}} xmm6 = xmm5[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm6[0],xmm2[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vshufpd {{.*#+}} xmm7 = xmm5[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2
+; CHECK-NEXT: vpsrlq $48, %xmm5, %xmm6
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm7 = xmm5[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpsrld $16, %xmm5, %xmm8
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2usi %xmm8, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6
+; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm6, %zmm2
+; CHECK-NEXT: vextractf128 $1, %ymm5, %xmm5
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm6 = xmm5[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm6, %xmm6
+; CHECK-NEXT: vcvttss2usi %xmm6, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm6
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm6
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm6
+; CHECK-NEXT: vshufps {{.*#+}} xmm7 = xmm5[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
+; CHECK-NEXT: vpsrldq {{.*#+}} xmm7 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vshufpd {{.*#+}} xmm8 = xmm5[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2usi %xmm8, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm8[0],xmm7[0]
+; CHECK-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6
+; CHECK-NEXT: vpsrlq $48, %xmm5, %xmm7
+; CHECK-NEXT: vcvtph2ps %xmm7, %xmm7
+; CHECK-NEXT: vcvttss2usi %xmm7, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm7
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm7
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm7
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm8 = xmm5[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm8, %xmm8
+; CHECK-NEXT: vcvttss2usi %xmm8, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm8
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm8[0],xmm7[0]
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm8
+; CHECK-NEXT: vcvttss2usi %xmm8, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm8
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm8
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm8
+; CHECK-NEXT: vpsrld $16, %xmm5, %xmm5
+; CHECK-NEXT: vcvtph2ps %xmm5, %xmm5
+; CHECK-NEXT: vcvttss2usi %xmm5, %rdx
+; CHECK-NEXT: vucomiss %xmm3, %xmm5
+; CHECK-NEXT: cmovbq %rax, %rdx
+; CHECK-NEXT: vucomiss %xmm4, %xmm5
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: vmovq %rdx, %xmm3
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm8[0],xmm3[0]
+; CHECK-NEXT: vinserti128 $1, %xmm7, %ymm3, %ymm3
+; CHECK-NEXT: vinserti64x4 $1, %ymm6, %zmm3, %zmm3
+; CHECK-NEXT: retq
+ %x = call <32 x i64> @llvm.fptoui.sat.v32i64.v32f16(<32 x half> %f)
+ ret <32 x i64> %x
+}
+
+define <32 x i128> @test_unsigned_v32i128_v32f16(<32 x half> %f) nounwind {
+; CHECK-LABEL: test_unsigned_v32i128_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %r13
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: subq $648, %rsp # imm = 0x288
+; CHECK-NEXT: vmovdqu64 %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm1
+; CHECK-NEXT: vcvtph2ps %xmm1, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: xorl %r14d, %r14d
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %r15
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
+; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm0
+; CHECK-NEXT: vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrlq $48, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[1,0]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $10, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpermilps $255, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[3,3,3,3]
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vpsrldq $14, (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: # xmm0 = mem[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rdx
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %rdx
+; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rdx, %r12
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %r12
+; CHECK-NEXT: cmovbq %r14, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %rax
+; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; CHECK-NEXT: cmovaq %r15, %r12
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r13
+; CHECK-NEXT: movq %rdx, %rbp
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %r14, %rbp
+; CHECK-NEXT: cmovbq %r14, %r13
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cmovaq %r15, %r13
+; CHECK-NEXT: cmovaq %r15, %rbp
+; CHECK-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: movq %rax, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: cmovbq %rax, %r15
+; CHECK-NEXT: cmovbq %rax, %r14
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaq %rax, %r14
+; CHECK-NEXT: cmovaq %rax, %r15
+; CHECK-NEXT: vcvtph2ps (%rsp), %xmm0 # 16-byte Folded Reload
+; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT: callq __fixunssfti at PLT
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: movl $0, %ecx
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: cmovbq %rcx, %rax
+; CHECK-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovaq %rcx, %rax
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, 392(%rbx)
+; CHECK-NEXT: movq %rax, 384(%rbx)
+; CHECK-NEXT: movq %r15, 264(%rbx)
+; CHECK-NEXT: movq %r14, 256(%rbx)
+; CHECK-NEXT: movq %rbp, 136(%rbx)
+; CHECK-NEXT: movq %r13, 128(%rbx)
+; CHECK-NEXT: movq %r12, 8(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, (%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 504(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 496(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 488(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 480(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 472(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 464(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 456(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 448(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 440(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 432(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 424(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 416(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 408(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 400(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 376(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 368(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 360(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 352(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 344(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 336(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 328(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 320(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 312(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 304(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 296(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 288(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 280(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 272(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 248(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 240(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 232(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 224(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 216(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 208(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 200(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 192(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 184(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 176(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 168(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 160(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 152(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 144(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 120(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 112(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 104(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 96(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 88(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 80(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 72(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 64(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 56(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 48(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 40(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 32(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 24(%rbx)
+; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; CHECK-NEXT: movq %rax, 16(%rbx)
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: addq $648, %rsp # imm = 0x288
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: popq %r13
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ %x = call <32 x i128> @llvm.fptoui.sat.v32i128.v32f16(<32 x half> %f)
+ ret <32 x i128> %x
+}
>From d1fd838f820d1294b2ddab56ebb2e0cef1196e66 Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 14 Jun 2026 02:34:51 +0200
Subject: [PATCH 10/11] improvment test
---
llvm/test/CodeGen/X86/llc-accept-avx10-512.ll | 65 ++-----------------
1 file changed, 6 insertions(+), 59 deletions(-)
diff --git a/llvm/test/CodeGen/X86/llc-accept-avx10-512.ll b/llvm/test/CodeGen/X86/llc-accept-avx10-512.ll
index b5c9895fefd98..1ba6392ebe11f 100644
--- a/llvm/test/CodeGen/X86/llc-accept-avx10-512.ll
+++ b/llvm/test/CodeGen/X86/llc-accept-avx10-512.ll
@@ -26,65 +26,12 @@ define <32 x bfloat> @foo_avx10.1(<16 x float> %a, <16 x float> %b) {
define <8 x i32> @foo_avx10.2(<8 x double> %f) {
; CHECK-AVX10_1-LABEL: foo_avx10.2:
; CHECK-AVX10_1: # %bb.0:
-; CHECK-AVX10_1-NEXT: vextractf32x4 $2, %zmm0, %xmm1
-; CHECK-AVX10_1-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]
-; CHECK-AVX10_1-NEXT: vmovsd {{.*#+}} xmm3 = [-2.147483648E+9,0.0E+0]
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm2, %xmm4
-; CHECK-AVX10_1-NEXT: vmovsd {{.*#+}} xmm5 = [2.147483647E+9,0.0E+0]
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm4, %xmm4
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm4, %ecx
-; CHECK-AVX10_1-NEXT: xorl %eax, %eax
-; CHECK-AVX10_1-NEXT: vucomisd %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm1, %xmm2
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm2, %edx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm1, %xmm1
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %edx
-; CHECK-AVX10_1-NEXT: vmovd %edx, %xmm1
-; CHECK-AVX10_1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; CHECK-AVX10_1-NEXT: vextractf32x4 $3, %zmm0, %xmm2
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm2, %xmm4
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm4, %xmm4
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm4, %ecx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
-; CHECK-AVX10_1-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm2, %xmm4
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm4, %xmm4
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm4, %ecx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vpinsrd $3, %ecx, %xmm1, %xmm1
-; CHECK-AVX10_1-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm2, %xmm4
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm4, %xmm4
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm4, %ecx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm0, %xmm2
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm2, %edx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm0, %xmm0
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %edx
-; CHECK-AVX10_1-NEXT: vmovd %edx, %xmm2
-; CHECK-AVX10_1-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm0, %xmm4
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm4, %xmm4
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm4, %ecx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm0, %xmm0
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vpinsrd $2, %ecx, %xmm2, %xmm2
-; CHECK-AVX10_1-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; CHECK-AVX10_1-NEXT: vmaxsd %xmm3, %xmm0, %xmm3
-; CHECK-AVX10_1-NEXT: vminsd %xmm5, %xmm3, %xmm3
-; CHECK-AVX10_1-NEXT: vcvttsd2si %xmm3, %ecx
-; CHECK-AVX10_1-NEXT: vucomisd %xmm0, %xmm0
-; CHECK-AVX10_1-NEXT: cmovpl %eax, %ecx
-; CHECK-AVX10_1-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm0
-; CHECK-AVX10_1-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-AVX10_1-NEXT: vcmpgepd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
+; CHECK-AVX10_1-NEXT: vcvttpd2dq %zmm0, %ymm1
+; CHECK-AVX10_1-NEXT: vpbroadcastd {{.*#+}} ymm1 {%k1} = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; CHECK-AVX10_1-NEXT: vcmpunordpd %zmm0, %zmm0, %k0
+; CHECK-AVX10_1-NEXT: knotb %k0, %k1
+; CHECK-AVX10_1-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1} {z}
; CHECK-AVX10_1-NEXT: retq
;
; CHECK-AVX10_2-LABEL: foo_avx10.2:
>From 7eda4d6a7b069fdfbf008230911d65ded4dc2f2c Mon Sep 17 00:00:00 2001
From: Jordan Jazbor <jazborj at gmail.com>
Date: Sun, 14 Jun 2026 13:01:46 +0200
Subject: [PATCH 11/11] Improve comment
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d838031371a89..6ca6245f74f60 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -22883,10 +22883,10 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2IBS : X86ISD::CVTTP2IUBS,
dl, VecI16VT, Src);
return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
- }
+ }
if ((DstVT == MVT::v4i32 && Subtarget.hasSSE2()) ||
- (DstVT == MVT::v8i32 && Subtarget.hasAVX()) ||
- (DstVT == MVT::v16i32 && Subtarget.hasAVX512())) {
+ (DstVT == MVT::v8i32 && Subtarget.hasAVX()) ||
+ (DstVT == MVT::v16i32 && Subtarget.hasAVX512())) {
unsigned SatWidth = SatVT.getScalarSizeInBits();
assert(SatWidth <= 32 &&
"Expected saturation width no wider than result element");
@@ -22937,8 +22937,7 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
IsOvf = DAG.getNode(ISD::TRUNCATE, dl, SelCCVT, IsOvf);
// v16i32 (512-bit, AVX512): use X86ISD::CVTTP2UI (VCVTTPS2UDQZ).
// v4i32 (128-bit, SSE) and v8i32 (256-bit, AVX) are already covered
- // by CVTTPS2DQ/VCVTTPS2DQ via expandFP_TO_UINT_SSE — no AVX512VL
- // needed.
+ // by CVTTPS2DQ/VCVTTPS2DQ via expandFP_TO_UINT_SSE
SDValue Cvt;
if (DstVT == MVT::v16i32)
Cvt = DAG.getNode(X86ISD::CVTTP2UI, dl, DstVT, Clamped);
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