[llvm] [X86][APX] Remove prefer-ndd-imm tuning (PR #203758)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 14 03:02:08 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Phoebe Wang (phoebewang)
<details>
<summary>Changes</summary>
It turns out NDD's immediate variants perform as good as non-NDD's on real hardware. Verified both on CPU2017 and CPU2026, the geomean is around 0 w/ and w/o this change. A few items get up and down due to the side effect of register live range change caused by the NDD form. No evidence shows this change has improvements or degradations even on single items.
Assisted-by: Claude Sonnet 4.6
---
Patch is 150.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203758.diff
28 Files Affected:
- (modified) llvm/lib/Target/X86/X86.td (-4)
- (modified) llvm/lib/Target/X86/X86InstrArithmetic.td (+15-25)
- (modified) llvm/lib/Target/X86/X86InstrCompiler.td (+11-20)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+4-4)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (-2)
- (modified) llvm/test/CodeGen/X86/apx/adc.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/add.ll (+38-290)
- (modified) llvm/test/CodeGen/X86/apx/and.ll (+18-172)
- (modified) llvm/test/CodeGen/X86/apx/cmov.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/dec.ll (+10-52)
- (modified) llvm/test/CodeGen/X86/apx/imul.ll (-40)
- (modified) llvm/test/CodeGen/X86/apx/inc.ll (+19-75)
- (modified) llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/apx/mul-i1024.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/apx/neg.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/not.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/or.ll (+18-193)
- (modified) llvm/test/CodeGen/X86/apx/rol.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/ror.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/sar.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/sbb.ll (+1-117)
- (modified) llvm/test/CodeGen/X86/apx/shl.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/shld.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/shr.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/shrd.ll (-2)
- (modified) llvm/test/CodeGen/X86/apx/sub.ll (+37-277)
- (modified) llvm/test/CodeGen/X86/apx/xor.ll (+18-185)
- (modified) llvm/test/CodeGen/X86/cmp.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 8cce0589aae41..7551966cb8e15 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -789,10 +789,6 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
-def TuningNDDImm
- : SubtargetFeature<"prefer-ndd-imm", "HasNDDI",
- "true", "Prefer NDD immediate variant">;
-
def TuningNDDMem
: SubtargetFeature<"prefer-ndd-mem", "HasNDDM",
"true", "Prefer NDD memory addressing">;
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 3934d449f54e9..c91600525d1eb 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -433,7 +433,7 @@ let isConvertibleToThreeAddress = 1 in {
def DEC16r : DecOpR_RF<Xi16>, OpSize16;
def DEC32r : DecOpR_RF<Xi32>, OpSize32;
}
- let Predicates = [NoNDDI] in {
+ let Predicates = [NoNDD] in {
def INC64r : IncOpR_RF<Xi64>;
def DEC64r : DecOpR_RF<Xi64>;
}
@@ -445,7 +445,7 @@ let isConvertibleToThreeAddress = 1 in {
def DEC16r_ND : DecOpR_RF<Xi16, 1>, PD;
def DEC32r_ND : DecOpR_RF<Xi32, 1>;
}
- let Predicates = [HasNDDI, In64BitMode] in {
+ let Predicates = [HasNDD, In64BitMode] in {
def INC64r_ND : IncOpR_RF<Xi64, 1>;
def DEC64r_ND : DecOpR_RF<Xi64, 1>;
}
@@ -639,8 +639,7 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
string mnemonic, Format RegMRM, Format MemMRM,
SDNode opnodeflag, SDNode opnode,
bit CommutableRR, bit ConvertibleToThreeAddress,
- bit ConvertibleToThreeAddressRR,
- Predicate prd = HasNDD> {
+ bit ConvertibleToThreeAddressRR> {
let isCommutable = CommutableRR,
isConvertibleToThreeAddress = ConvertibleToThreeAddressRR in {
let Predicates = [NoNDD] in {
@@ -730,27 +729,23 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
def 16ri : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM>, OpSize16;
def 32ri : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM>, OpSize32;
- }
- let Predicates = [NoNDDI] in {
def 64ri8 : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>;
def 64ri32: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM>;
}
let Predicates = [HasNDD, In64BitMode] in {
def 16ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM, 1>, PD;
def 32ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM, 1>;
+ def 64ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM, 1>;
def 8ri_ND : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM, 1>;
def 16ri_ND : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM, 1>, PD;
def 32ri_ND : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM, 1>;
+ def 64ri32_ND: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM, 1>;
def 16ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD;
def 32ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM, 1>, EVEX_NF;
+ def 64ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM, 1>, EVEX_NF;
def 8ri_NF_ND : BinOpRI_R<0x80, mnemonic, Xi8, RegMRM, 1>, EVEX_NF;
def 16ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD;
def 32ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM, 1>, EVEX_NF;
- }
- let Predicates = [prd, In64BitMode] in {
- def 64ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM, 1>;
- def 64ri32_ND: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM, 1>;
- def 64ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM, 1>, EVEX_NF;
def 64ri32_NF_ND : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM, 1>, EVEX_NF;
}
let Predicates = [In64BitMode] in {
@@ -1103,10 +1098,10 @@ defm OR : ArithBinOp_RF<0x09, 0x0B, 0x0D, "or", MRM1r, MRM1m,
defm XOR : ArithBinOp_RF<0x31, 0x33, 0x35, "xor", MRM6r, MRM6m,
X86xor_flag, xor, 1, 0, 0>;
defm ADD : ArithBinOp_RF<0x01, 0x03, 0x05, "add", MRM0r, MRM0m,
- X86add_flag, add, 1, 1, 1, HasNDDI>;
+ X86add_flag, add, 1, 1, 1>;
let isCompare = 1 in {
defm SUB : ArithBinOp_RF<0x29, 0x2B, 0x2D, "sub", MRM5r, MRM5m,
- X86sub_flag, sub, 0, 1, 0, HasNDDI>;
+ X86sub_flag, sub, 0, 1, 0>;
}
// Version of XOR8rr_NOREX that use GR8_NOREX. This is used by the handling of
@@ -1166,8 +1161,7 @@ def : Pat<(store (X86adc_flag GR64:$src, (loadi64 addr:$dst), EFLAGS),
(ADC64mr addr:$dst, GR64:$src)>;
// Patterns for basic arithmetic ops with relocImm for the immediate field.
-multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode,
- Predicate prd=HasNDD> {
+multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode> {
let Predicates = [NoNDD] in {
def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
(!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
@@ -1175,6 +1169,8 @@ multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode,
(!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
(!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
+ def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
+ (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
def : Pat<(store (OpNode (load addr:$dst), relocImm8_su:$src), addr:$dst),
(!cast<Instruction>(NAME#"8mi") addr:$dst, relocImm8_su:$src)>;
@@ -1192,6 +1188,8 @@ multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode,
(!cast<Instruction>(NAME#"16ri_ND") GR16:$src1, relocImm16_su:$src2)>;
def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
(!cast<Instruction>(NAME#"32ri_ND") GR32:$src1, relocImm32_su:$src2)>;
+ def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
+ (!cast<Instruction>(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>;
def : Pat<(OpNode (load ndd_addr:$dst), relocImm8_su:$src),
(!cast<Instruction>(NAME#"8mi_ND") ndd_addr:$dst, relocImm8_su:$src)>;
@@ -1202,14 +1200,6 @@ multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode,
def : Pat<(OpNode (load ndd_addr:$dst), i64relocImmSExt32_su:$src),
(!cast<Instruction>(NAME#"64mi32_ND") ndd_addr:$dst, i64relocImmSExt32_su:$src)>;
}
-
- let Predicates = [NoNDDI] in
- def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
- (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
-
- let Predicates = [prd] in
- def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
- (!cast<Instruction>(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>;
}
multiclass ArithBinOp_RFF_relocImm_Pats<SDNode OpNodeFlag> {
@@ -1276,8 +1266,8 @@ multiclass ArithBinOp_F_relocImm_Pats<SDNode OpNodeFlag> {
defm AND : ArithBinOp_RF_relocImm_Pats<X86and_flag, and>;
defm OR : ArithBinOp_RF_relocImm_Pats<X86or_flag, or>;
defm XOR : ArithBinOp_RF_relocImm_Pats<X86xor_flag, xor>;
-defm ADD : ArithBinOp_RF_relocImm_Pats<X86add_flag, add, HasNDDI>;
-defm SUB : ArithBinOp_RF_relocImm_Pats<X86sub_flag, sub, HasNDDI>;
+defm ADD : ArithBinOp_RF_relocImm_Pats<X86add_flag, add>;
+defm SUB : ArithBinOp_RF_relocImm_Pats<X86sub_flag, sub>;
defm ADC : ArithBinOp_RFF_relocImm_Pats<X86adc_flag>;
defm SBB : ArithBinOp_RFF_relocImm_Pats<X86sbb_flag>;
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index c7ea2985d1353..35dfdf2d0067c 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1614,15 +1614,13 @@ let Predicates = [NoNDD] in {
(SUB16ri GR16:$src1, -128)>;
def : Pat<(add GR32:$src1, 128),
(SUB32ri GR32:$src1, -128)>;
+ def : Pat<(add GR64:$src1, 128),
+ (SUB64ri32 GR64:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR16:$src1, 128),
(SUB16ri GR16:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR32:$src1, 128),
(SUB32ri GR32:$src1, -128)>;
-}
-let Predicates = [NoNDDI] in {
- def : Pat<(add GR64:$src1, 128),
- (SUB64ri32 GR64:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR64:$src1, 128),
(SUB64ri32 GR64:$src1, -128)>;
}
@@ -1631,15 +1629,13 @@ let Predicates = [HasNDD] in {
(SUB16ri_ND GR16:$src1, -128)>;
def : Pat<(add GR32:$src1, 128),
(SUB32ri_ND GR32:$src1, -128)>;
+ def : Pat<(add GR64:$src1, 128),
+ (SUB64ri32_ND GR64:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR16:$src1, 128),
(SUB16ri_ND GR16:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR32:$src1, 128),
(SUB32ri_ND GR32:$src1, -128)>;
-}
-let Predicates = [HasNDDI] in {
- def : Pat<(add GR64:$src1, 128),
- (SUB64ri32_ND GR64:$src1, -128)>;
def : Pat<(X86add_flag_nocf GR64:$src1, 128),
(SUB64ri32_ND GR64:$src1, -128)>;
}
@@ -1666,7 +1662,7 @@ let Predicates = [NoNDD] in {
def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),
(SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
}
-let Predicates = [HasNDDI] in {
+let Predicates = [HasNDD] in {
def : Pat<(add GR64:$src1, 0x0000000080000000),
(SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>;
def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),
@@ -2107,7 +2103,7 @@ def : Pat<(X86btc GR64:$src1, GR64:$src2), (BTC64rr GR64:$src1, GR64:$src2)>;
// EFLAGS-defining Patterns
//===----------------------------------------------------------------------===//
-multiclass EFLAGSDefiningPats<string suffix, Predicate PredNDD, Predicate PredNDDI, bit ndd> {
+multiclass EFLAGSDefiningPats<string suffix, Predicate PredNDD, bit ndd> {
let Predicates = [PredNDD] in {
// add reg, reg
def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>;
@@ -2250,9 +2246,7 @@ multiclass EFLAGSDefiningPats<string suffix, Predicate PredNDD, Predicate PredND
(!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>;
def : Pat<(and GR64:$src1, i64immSExt32:$src2),
(!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
- }
- let Predicates = [PredNDDI] in {
def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
(!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
@@ -2264,28 +2258,25 @@ multiclass EFLAGSDefiningPats<string suffix, Predicate PredNDD, Predicate PredND
def : Pat<(add_like GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>;
def : Pat<(add_like GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>;
def : Pat<(add_like GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>;
+ def : Pat<(add_like GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;
def : Pat<(add GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>;
def : Pat<(add GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>;
def : Pat<(add GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>;
+ def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;
def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>;
def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>;
def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>;
+ def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;
def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>;
def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>;
def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>;
- }
-
- let Predicates = [UseIncDec, PredNDDI] in {
- def : Pat<(add_like GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;
- def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;
- def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;
def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;
}
}
-defm : EFLAGSDefiningPats<"", NoNDD, NoNDDI, 0>;
-defm : EFLAGSDefiningPats<"_ND", HasNDD, HasNDDI, 1>;
+defm : EFLAGSDefiningPats<"", NoNDD, 0>;
+defm : EFLAGSDefiningPats<"_ND", HasNDD, 1>;
let Predicates = [HasZU] in {
// zext (mul reg/mem, imm) -> imulzu
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 15d2e10aa0f08..d4162414b3b40 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5699,7 +5699,7 @@ static bool canConvert2Copy(unsigned Opc) {
/// Convert an ALUrr opcode to corresponding ALUri opcode. Such as
/// ADD32rr ==> ADD32ri
-static unsigned convertALUrr2ALUri(unsigned Opc, bool HasNDDI) {
+static unsigned convertALUrr2ALUri(unsigned Opc) {
switch (Opc) {
default:
return 0;
@@ -5750,9 +5750,9 @@ static unsigned convertALUrr2ALUri(unsigned Opc, bool HasNDDI) {
FROM_TO(CCMP32rr, CCMP32ri)
#undef FROM_TO
case X86::ADD64rr_ND:
- return HasNDDI ? X86::ADD64ri32_ND : 0;
+ return X86::ADD64ri32_ND;
case X86::SUB64rr_ND:
- return HasNDDI ? X86::SUB64ri32_ND : 0;
+ return X86::SUB64ri32_ND;
}
}
@@ -5839,7 +5839,7 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
else
return false;
} else
- NewOpc = convertALUrr2ALUri(Opc, Subtarget.hasNDDI());
+ NewOpc = convertALUrr2ALUri(Opc);
if (!NewOpc)
return false;
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 352de4141ce71..afca2e6eafd2c 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -50,8 +50,6 @@ def PreferLegacySetCC : Predicate<"!Subtarget->hasZU() || "
"Subtarget->preferLegacySetCC()">;
def PreferNoLegacySetCC : Predicate<"Subtarget->hasZU() && "
"!Subtarget->preferLegacySetCC()">;
-def HasNDDI : Predicate<"Subtarget->hasNDD() && Subtarget->hasNDDI()">;
-def NoNDDI : Predicate<"!Subtarget->hasNDD() || !Subtarget->hasNDDI()">;
def HasCF : Predicate<"Subtarget->hasCF()">;
def HasJMPABS : Predicate<"Subtarget->hasJMPABS()">;
def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll
index 863fe8b5a518a..f524ffce89f61 100644
--- a/llvm/test/CodeGen/X86/apx/adc.ll
+++ b/llvm/test/CodeGen/X86/apx/adc.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NDD
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-imm -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NDD
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-mem -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,MEM
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-imm,+prefer-ndd-mem -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,MEM
define i8 @adc8rr(i8 %a, i8 %b, i8 %x, i8 %y) nounwind {
; CHECK-LABEL: adc8rr:
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index 0cbbbdfbb8715..d7c5635b617c1 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NDD
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-imm -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,IMM,IMMONLY
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-mem -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,MEM,MEMONLY
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-imm,+prefer-ndd-mem -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,IMM,MEM,BOTH
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,+prefer-ndd-mem -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,MEM
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -x86-enable-apx-for-relocation=true -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
@@ -74,13 +72,6 @@ define i8 @add8rm(i8 noundef %a, ptr %ptr) {
; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
;
-; IMMONLY-LABEL: add8rm:
-; IMMONLY: # %bb.0: # %entry
-; IMMONLY-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; IMMONLY-NEXT: addb (%rsi), %al # encoding: [0x02,0x06]
-; IMMONLY-NEXT: # kill: def $al killed $al killed $eax
-; IMMONLY-NEXT: retq # encoding: [0xc3]
-;
; MEM-LABEL: add8rm:
; MEM: # %bb.0: # %entry
; MEM-NEXT: addb (%rsi), %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x02,0x3e]
@@ -106,13 +97,6 @@ define i16 @add16rm(i16 noundef %a, ptr %ptr) {
; NDD-NEXT: # kill: def $ax killed $ax killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
;
-; IMMONLY-LABEL: add16rm:
-; IMMONLY: # %bb.0: # %entry
-; IMMONLY-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; IMMONLY-NEXT: addw (%rsi), %ax # encoding: [0x66,0x03,0x06]
-; IMMONLY-NEXT: # kill: def $ax killed $ax killed $eax
-; IMMONLY-NEXT: retq # encoding: [0xc3]
-;
; MEM-LABEL: add16rm:
; MEM: # %bb.0: # %entry
; MEM-NEXT: addw (%rsi), %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x03,0x3e]
@@ -137,12 +121,6 @@ define i32 @add32rm(i32 noundef %a, ptr %ptr) {
; NDD-NEXT: addl (%rsi), %eax # encoding: [0x03,0x06]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; IMMONLY-LABEL: add32rm:
-; IMMONLY: # %bb.0: # %entry
-; IMMONLY-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; IMMONLY-NEXT: addl (%rsi), %eax # encoding: [0x03,0x06]
-; IMMONLY-NEXT: retq # encoding: [0xc3]
-;
; MEM-LABEL: add32rm:
; MEM: # %bb.0: # %entry
; MEM-NEXT: addl (%rsi), %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x03,0x3e]
@@ -166,12 +144,6 @@ define i64 @add64rm(i64 noundef %a, ptr %ptr) {
; NDD-NEXT: addq (%rsi), %rax # encoding: [0x48,0x03,0x06]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; IMMONLY-LABEL: add64rm:
-; IMMONLY: # %bb.0: # %entry
-; IMMONLY-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
-; IMMONLY-NEXT: addq (%rsi), %rax # encoding: [0x48,0x03,0x06]
-; IMMONLY-NEXT: retq # encoding: [0xc3]
-;
; MEM-LABEL: add64rm:
; MEM: # %bb.0: # %entry
; MEM-NEXT: addq (%rsi), %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x03,0x3e]
@@ -303,13 +275,6 @@ define i8 @add8mr(ptr %a, i8 noundef %b) {
; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq # encoding: [0xc3]
;
-; IMMONLY-LABEL: add8mr:
-; IMMONLY: # %bb.0: # %entry
-; IMMONLY-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
-; IMMONLY-NEXT: addb (%rdi), %al # encoding: [0x02,0x07]
-; IMMONLY-NEXT: # kill: def $al killed $al killed $eax
-; IMMONLY-NEXT: retq # encoding: [0xc3]
-;
; MEM-LABEL: add8mr:
; MEM: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203758
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