[llvm] [SLP][NFC]Add a test with miscompiled ordered reductions, NFC (PR #203738)
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 13 18:58:29 PDT 2026
https://github.com/alexey-bataev created https://github.com/llvm/llvm-project/pull/203738
None
>From 7d62238b4e0ada75316b6385be9d01fac35737a0 Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev at outlook.com>
Date: Sat, 13 Jun 2026 18:58:18 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
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Created using spr 1.3.7
---
.../X86/reduction-ordered-fadd.ll | 164 ++++++++++++++++++
1 file changed, 164 insertions(+)
create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
new file mode 100644
index 0000000000000..405efd15336d5
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-ordered-fadd.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux -mcpu=skylake-avx512 -slp-threshold=-100 | FileCheck %s
+
+define float @reduce_ordered_fadd_inorder(ptr %a, ptr %b) {
+; CHECK-LABEL: define float @reduce_ordered_fadd_inorder(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 0
+; CHECK-NEXT: [[B0:%.*]] = getelementptr inbounds float, ptr [[B]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[A0]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr [[B0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP2]])
+; CHECK-NEXT: ret float [[TMP8]]
+;
+entry:
+ %a0 = getelementptr inbounds float, ptr %a, i64 0
+ %va0 = load float, ptr %a0
+ %b0 = getelementptr inbounds float, ptr %b, i64 0
+ %vb0 = load float, ptr %b0
+ %m0 = fmul float %va0, %vb0
+ %a1 = getelementptr inbounds float, ptr %a, i64 1
+ %va1 = load float, ptr %a1
+ %b1 = getelementptr inbounds float, ptr %b, i64 1
+ %vb1 = load float, ptr %b1
+ %m1 = fmul float %va1, %vb1
+ %a2 = getelementptr inbounds float, ptr %a, i64 2
+ %va2 = load float, ptr %a2
+ %b2 = getelementptr inbounds float, ptr %b, i64 2
+ %vb2 = load float, ptr %b2
+ %m2 = fmul float %va2, %vb2
+ %a3 = getelementptr inbounds float, ptr %a, i64 3
+ %va3 = load float, ptr %a3
+ %b3 = getelementptr inbounds float, ptr %b, i64 3
+ %vb3 = load float, ptr %b3
+ %m3 = fmul float %va3, %vb3
+ %a4 = getelementptr inbounds float, ptr %a, i64 4
+ %va4 = load float, ptr %a4
+ %b4 = getelementptr inbounds float, ptr %b, i64 4
+ %vb4 = load float, ptr %b4
+ %m4 = fmul float %va4, %vb4
+ %a5 = getelementptr inbounds float, ptr %a, i64 5
+ %va5 = load float, ptr %a5
+ %b5 = getelementptr inbounds float, ptr %b, i64 5
+ %vb5 = load float, ptr %b5
+ %m5 = fmul float %va5, %vb5
+ %a6 = getelementptr inbounds float, ptr %a, i64 6
+ %va6 = load float, ptr %a6
+ %b6 = getelementptr inbounds float, ptr %b, i64 6
+ %vb6 = load float, ptr %b6
+ %m6 = fmul float %va6, %vb6
+ %a7 = getelementptr inbounds float, ptr %a, i64 7
+ %va7 = load float, ptr %a7
+ %b7 = getelementptr inbounds float, ptr %b, i64 7
+ %vb7 = load float, ptr %b7
+ %m7 = fmul float %va7, %vb7
+ %r0 = fadd float %m0, %m1
+ %r1 = fadd float %r0, %m2
+ %r2 = fadd float %r1, %m3
+ %r3 = fadd float %r2, %m4
+ %r4 = fadd float %r3, %m5
+ %r5 = fadd float %r4, %m6
+ %r6 = fadd float %r5, %m7
+ ret float %r6
+}
+
+define float @reduce_ordered_fadd_reversed(ptr %a, ptr %b) {
+; CHECK-LABEL: define float @reduce_ordered_fadd_reversed(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 0
+; CHECK-NEXT: [[B0:%.*]] = getelementptr inbounds float, ptr [[B]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[A0]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr [[B0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[R6:%.*]] = call float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP2]])
+; CHECK-NEXT: ret float [[R6]]
+;
+entry:
+ %a0 = getelementptr inbounds float, ptr %a, i64 0
+ %va0 = load float, ptr %a0
+ %b0 = getelementptr inbounds float, ptr %b, i64 0
+ %vb0 = load float, ptr %b0
+ %m0 = fmul float %va0, %vb0
+ %a1 = getelementptr inbounds float, ptr %a, i64 1
+ %va1 = load float, ptr %a1
+ %b1 = getelementptr inbounds float, ptr %b, i64 1
+ %vb1 = load float, ptr %b1
+ %m1 = fmul float %va1, %vb1
+ %a2 = getelementptr inbounds float, ptr %a, i64 2
+ %va2 = load float, ptr %a2
+ %b2 = getelementptr inbounds float, ptr %b, i64 2
+ %vb2 = load float, ptr %b2
+ %m2 = fmul float %va2, %vb2
+ %a3 = getelementptr inbounds float, ptr %a, i64 3
+ %va3 = load float, ptr %a3
+ %b3 = getelementptr inbounds float, ptr %b, i64 3
+ %vb3 = load float, ptr %b3
+ %m3 = fmul float %va3, %vb3
+ %a4 = getelementptr inbounds float, ptr %a, i64 4
+ %va4 = load float, ptr %a4
+ %b4 = getelementptr inbounds float, ptr %b, i64 4
+ %vb4 = load float, ptr %b4
+ %m4 = fmul float %va4, %vb4
+ %a5 = getelementptr inbounds float, ptr %a, i64 5
+ %va5 = load float, ptr %a5
+ %b5 = getelementptr inbounds float, ptr %b, i64 5
+ %vb5 = load float, ptr %b5
+ %m5 = fmul float %va5, %vb5
+ %a6 = getelementptr inbounds float, ptr %a, i64 6
+ %va6 = load float, ptr %a6
+ %b6 = getelementptr inbounds float, ptr %b, i64 6
+ %vb6 = load float, ptr %b6
+ %m6 = fmul float %va6, %vb6
+ %a7 = getelementptr inbounds float, ptr %a, i64 7
+ %va7 = load float, ptr %a7
+ %b7 = getelementptr inbounds float, ptr %b, i64 7
+ %vb7 = load float, ptr %b7
+ %m7 = fmul float %va7, %vb7
+ %r0 = fadd float %m7, %m6
+ %r1 = fadd float %r0, %m5
+ %r2 = fadd float %r1, %m4
+ %r3 = fadd float %r2, %m3
+ %r4 = fadd float %r3, %m2
+ %r5 = fadd float %r4, %m1
+ %r6 = fadd float %r5, %m0
+ ret float %r6
+}
+
+define float @reduce_ordered_fadd_reassoc_no_nsz(ptr %p) {
+; CHECK-LABEL: define float @reduce_ordered_fadd_reassoc_no_nsz(
+; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds float, ptr [[P]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[P0]], align 4
+; CHECK-NEXT: [[R6:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP0]])
+; CHECK-NEXT: ret float [[R6]]
+;
+entry:
+ %p0 = getelementptr inbounds float, ptr %p, i64 0
+ %l0 = load float, ptr %p0
+ %p1 = getelementptr inbounds float, ptr %p, i64 1
+ %l1 = load float, ptr %p1
+ %p2 = getelementptr inbounds float, ptr %p, i64 2
+ %l2 = load float, ptr %p2
+ %p3 = getelementptr inbounds float, ptr %p, i64 3
+ %l3 = load float, ptr %p3
+ %p4 = getelementptr inbounds float, ptr %p, i64 4
+ %l4 = load float, ptr %p4
+ %p5 = getelementptr inbounds float, ptr %p, i64 5
+ %l5 = load float, ptr %p5
+ %p6 = getelementptr inbounds float, ptr %p, i64 6
+ %l6 = load float, ptr %p6
+ %p7 = getelementptr inbounds float, ptr %p, i64 7
+ %l7 = load float, ptr %p7
+ %r0 = fadd reassoc float %l0, %l1
+ %r1 = fadd reassoc float %r0, %l2
+ %r2 = fadd reassoc float %r1, %l3
+ %r3 = fadd reassoc float %r2, %l4
+ %r4 = fadd reassoc float %r3, %l5
+ %r5 = fadd reassoc float %r4, %l6
+ %r6 = fadd reassoc float %r5, %l7
+ ret float %r6
+}
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