[llvm] [X86] Add post-RA redundant copy elimination for TEST/CMP branch paths (PR #203733)
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Sat Jun 13 17:22:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: mike-goutokuji (mike-goutokuji)
<details>
<summary>Changes</summary>
Like AArch64 and RISC-V.
---
Patch is 38.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203733.diff
15 Files Affected:
- (modified) llvm/lib/Target/X86/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/X86/X86.h (+14)
- (modified) llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp (+3)
- (modified) llvm/lib/Target/X86/X86PassRegistry.def (+1)
- (added) llvm/lib/Target/X86/X86RedundantCopyElimination.cpp (+395)
- (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+4)
- (modified) llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/coalescer-commute3.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/conditional-tailcall.ll (-1)
- (modified) llvm/test/CodeGen/X86/llc-pipeline-npm.ll (+2)
- (added) llvm/test/CodeGen/X86/machine-zero-copy-remove.mir (+277)
- (modified) llvm/test/CodeGen/X86/opt-pipeline.ll (+2)
- (modified) llvm/test/CodeGen/X86/pr38795.ll (-2)
- (modified) llvm/test/CodeGen/X86/switch.ll (+77-90)
- (modified) llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn (+1)
``````````diff
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index 62987bdbd1c2b..7e0918dad176b 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -54,6 +54,7 @@ set(sources
X86DynAllocaExpander.cpp
X86FixupSetCC.cpp
X86FlagsCopyLowering.cpp
+ X86RedundantCopyElimination.cpp
X86FloatingPoint.cpp
X86FrameLowering.cpp
X86ISelDAGToDAG.cpp
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 3ecc7a6ec498b..93ce34170818f 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -20,10 +20,13 @@
#include "llvm/IR/PassManager.h"
#include "llvm/PassInfo.h"
#include "llvm/Support/CodeGen.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
+extern cl::opt<bool> EnableRedundantCopyElimination;
+
class FunctionPass;
class InstructionSelector;
class PassRegistry;
@@ -224,6 +227,16 @@ class X86LowerTileCopyPass
FunctionPass *createX86LowerTileCopyLegacyPass();
+/// Remove redundant copies/moves based on dominating branch conditions.
+class X86RedundantCopyEliminationPass
+ : public OptionalPassInfoMixin<X86RedundantCopyEliminationPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createX86RedundantCopyEliminationLegacyPass();
+
/// Return a pass that inserts int3 at the end of the function if it ends with a
/// CALL instruction. The pass does the same for each funclet as well. This
/// ensures that the open interval of function start and end PCs contains all
@@ -498,6 +511,7 @@ void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &);
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &);
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &);
void initializeX86LowerTileCopyLegacyPass(PassRegistry &);
+void initializeX86RedundantCopyEliminationLegacyPass(PassRegistry &);
void initializeX86OptimizeLEAsLegacyPass(PassRegistry &);
void initializeX86PartialReductionLegacyPass(PassRegistry &);
void initializeX86PreTileConfigLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
index bb389b6756a52..f240e10698375 100644
--- a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
@@ -163,6 +163,9 @@ void X86CodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) const {
}
void X86CodeGenPassBuilder::addPostRegAlloc(PassManagerWrapper &PMW) const {
+ if (getOptLevel() != CodeGenOptLevel::None &&
+ EnableRedundantCopyElimination)
+ addMachineFunctionPass(X86RedundantCopyEliminationPass(), PMW);
addMachineFunctionPass(X86LowerTileCopyPass(), PMW);
addMachineFunctionPass(X86FPStackifierPass(), PMW);
// When -O0 is enabled, the Load Value Injection Hardening pass will fall back
diff --git a/llvm/lib/Target/X86/X86PassRegistry.def b/llvm/lib/Target/X86/X86PassRegistry.def
index 45e7d0ebdbf7b..55047bedad6bc 100644
--- a/llvm/lib/Target/X86/X86PassRegistry.def
+++ b/llvm/lib/Target/X86/X86PassRegistry.def
@@ -47,6 +47,7 @@ MACHINE_FUNCTION_PASS("x86-fixup-leas", X86FixupLEAsPass())
MACHINE_FUNCTION_PASS("x86-fixup-setcc", X86FixupSetCCPass())
MACHINE_FUNCTION_PASS("x86-fixup-vector-constants", X86FixupVectorConstantsPass())
MACHINE_FUNCTION_PASS("x86-flags-copy-lowering", X86FlagsCopyLoweringPass())
+MACHINE_FUNCTION_PASS("x86-copyelim", X86RedundantCopyEliminationPass())
MACHINE_FUNCTION_PASS("x86-fp-stackifier", X86FPStackifierPass())
MACHINE_FUNCTION_PASS("x86-global-base-reg", X86GlobalBaseRegPass())
MACHINE_FUNCTION_PASS("x86-indirect-branch-tracking", X86IndirectBranchTrackingPass())
diff --git a/llvm/lib/Target/X86/X86RedundantCopyElimination.cpp b/llvm/lib/Target/X86/X86RedundantCopyElimination.cpp
new file mode 100644
index 0000000000000..46bb7577dba72
--- /dev/null
+++ b/llvm/lib/Target/X86/X86RedundantCopyElimination.cpp
@@ -0,0 +1,395 @@
+
+//=- X86RedundantCopyElimination.cpp - Remove useless copy for X86 ----------=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "X86InstrInfo.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/iterator_range.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+
+#include "llvm/Pass.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "x86-copyelim"
+
+STATISTIC(NumCopiesRemoved, "Number of copies removed.");
+
+namespace llvm {
+cl::opt<bool> EnableRedundantCopyElimination(
+ "x86-enable-copyelim",
+ cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
+ cl::Hidden);
+} // namespace llvm
+
+namespace {
+
+struct KnownValue {
+ bool IsReg;
+ union {
+ MCPhysReg Reg;
+ int64_t Imm;
+ } U;
+
+ KnownValue() : IsReg(false) { U.Imm = 0; }
+ KnownValue(MCPhysReg R) : IsReg(true) { U.Reg = R; }
+ KnownValue(int64_t I) : IsReg(false) { U.Imm = I; }
+};
+
+static bool isRedundantZeroDefinition(const MachineInstr &MI) {
+ if (MI.getOpcode() == X86::MOV32r0)
+ return true;
+ if (MI.isMoveImmediate())
+ return MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0;
+ switch (MI.getOpcode()) {
+ case X86::XOR8rr:
+ case X86::XOR16rr:
+ case X86::XOR32rr:
+ case X86::XOR64rr:
+ return MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
+ default:
+ return false;
+ }
+}
+
+class X86RedundantCopyEliminationImpl {
+public:
+ X86RedundantCopyEliminationImpl() {}
+ bool run(MachineFunction &MF);
+
+private:
+
+ const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII;
+
+ bool optimizeBlock(MachineBasicBlock &MBB);
+};
+
+class X86RedundantCopyEliminationLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ X86RedundantCopyEliminationLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setNoVRegs();
+ }
+ StringRef getPassName() const override {
+ return "X86 Redundant Copy Elimination";
+ }
+};
+
+bool X86RedundantCopyEliminationImpl::optimizeBlock(MachineBasicBlock &MBB) {
+ if (MBB.pred_size() != 1)
+ return false;
+
+ MachineBasicBlock *BranchMBB = *MBB.pred_begin();
+ SmallVector<MachineBasicBlock *, 4> Path;
+
+ // Trace back along single-predecessor edges.
+ while (BranchMBB->succ_size() != 2) {
+ if (BranchMBB->pred_size() != 1)
+ return false;
+ Path.push_back(BranchMBB);
+ BranchMBB = *BranchMBB->pred_begin();
+ }
+
+ MachineBasicBlock *TBB = nullptr;
+ MachineBasicBlock *FBB = nullptr;
+ SmallVector<MachineOperand, 4> Cond;
+ if (TII->analyzeBranch(*BranchMBB, TBB, FBB, Cond, /*AllowModify=*/false) ||
+ Cond.size() != 1)
+ return false;
+
+ X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
+
+ MachineBasicBlock *NextOnPath = Path.empty() ? &MBB : Path.back();
+ bool IsTruePath = (NextOnPath == TBB);
+ if (!IsTruePath) {
+ if (FBB) {
+ if (NextOnPath != FBB)
+ return false;
+ } else if (NextOnPath != BranchMBB->getNextNode()) {
+ return false;
+ }
+ }
+
+ MachineInstr *CondBr = nullptr;
+ for (MachineInstr &Term : BranchMBB->terminators()) {
+ if (X86::isJCC(Term.getOpcode())) {
+ CondBr = &Term;
+ break;
+ }
+ }
+ if (!CondBr)
+ return false;
+
+ // Find the flag-setting instruction
+ MachineInstr *FlagSetter = nullptr;
+ MachineBasicBlock::reverse_iterator RIt = CondBr->getReverseIterator();
+ for (MachineInstr &PredI : make_range(std::next(RIt), BranchMBB->rend())) {
+ if (PredI.modifiesRegister(X86::EFLAGS, TRI)) {
+ FlagSetter = &PredI;
+ break;
+ }
+ }
+ if (!FlagSetter)
+ return false;
+
+ SmallVector<std::pair<MCPhysReg, KnownValue>, 4> KnownRegs;
+
+ // Helper: is the equality/zero path taken?
+ bool IsEqualPath = (CC == X86::COND_E && IsTruePath) ||
+ (CC == X86::COND_NE && !IsTruePath);
+
+ // Analyze the flag setter.
+ switch (FlagSetter->getOpcode()) {
+ default:
+ break;
+
+ // TEST is BinOpRR_F: (outs), (ins $src1, $src2) — no destination register.
+ // Operand 0 = $src1, Operand 1 = $src2.
+ case X86::TEST8rr: case X86::TEST16rr:
+ case X86::TEST32rr: case X86::TEST64rr:
+ if (FlagSetter->getOperand(0).getReg() ==
+ FlagSetter->getOperand(1).getReg()) {
+ if (IsEqualPath)
+ KnownRegs.push_back(
+ {FlagSetter->getOperand(0).getReg(), KnownValue((int64_t)0)});
+ }
+ break;
+
+ // AND/OR are BinOpRR_RF: (outs $dst), (ins $src1, $src2).
+ // Operand 0 = $dst (tied to $src1), Operand 1 = $src1, Operand 2 = $src2.
+ // Self-AND/OR (src1 == src2) sets ZF iff the value is zero.
+ case X86::AND8rr: case X86::AND16rr:
+ case X86::AND32rr: case X86::AND64rr:
+ case X86::OR8rr: case X86::OR16rr:
+ case X86::OR32rr: case X86::OR64rr:
+ if (FlagSetter->getOperand(1).getReg() ==
+ FlagSetter->getOperand(2).getReg()) {
+ if (IsEqualPath)
+ KnownRegs.push_back(
+ {FlagSetter->getOperand(0).getReg(), KnownValue((int64_t)0)});
+ }
+ break;
+
+ // CMP reg, reg is BinOpRR_F: (outs), (ins $src1, $src2).
+ // If equal, $src1 == $src2.
+ case X86::CMP8rr: case X86::CMP16rr:
+ case X86::CMP32rr: case X86::CMP64rr:
+ if (IsEqualPath) {
+ KnownRegs.push_back({FlagSetter->getOperand(0).getReg(),
+ KnownValue((MCPhysReg)FlagSetter->getOperand(1).getReg())});
+ KnownRegs.push_back({FlagSetter->getOperand(1).getReg(),
+ KnownValue((MCPhysReg)FlagSetter->getOperand(0).getReg())});
+ }
+ break;
+
+ // CMP reg, imm: (outs), (ins $src1, $imm).
+ // If equal, $src1 == $imm.
+ case X86::CMP8ri: case X86::CMP16ri: case X86::CMP16ri8:
+ case X86::CMP32ri: case X86::CMP32ri8:
+ case X86::CMP64ri8: case X86::CMP64ri32:
+ if (IsEqualPath && FlagSetter->getOperand(1).isImm()) {
+ int64_t Imm = FlagSetter->getOperand(1).getImm();
+ KnownRegs.push_back(
+ {FlagSetter->getOperand(0).getReg(), KnownValue(Imm)});
+ }
+ break;
+
+ // SUB reg, reg is BinOpRR_RF: (outs $dst), (ins $src1, $src2).
+ // If ZF set, $dst is zero. (Note: src1 and src2 were equal before the instruction,
+ // but $dst is tied to $src1, so $src1 is overwritten with zero and no longer equals $src2).
+ case X86::SUB8rr: case X86::SUB16rr:
+ case X86::SUB32rr: case X86::SUB64rr:
+ if (IsEqualPath) {
+ KnownRegs.push_back(
+ {FlagSetter->getOperand(0).getReg(), KnownValue((int64_t)0)});
+ }
+ break;
+ }
+
+ if (KnownRegs.empty())
+ return false;
+
+ // Check if any known register was clobbered in the path.
+ auto isClobbered = [&](MCPhysReg Reg) {
+ // Check BranchMBB from FlagSetter to end
+ for (MachineInstr &MI : make_range(std::next(MachineBasicBlock::iterator(FlagSetter)), BranchMBB->end())) {
+ if (MI.modifiesRegister(Reg, TRI)) return true;
+ }
+ // Check Path blocks
+ for (auto *PMBB : llvm::reverse(Path)) {
+ for (MachineInstr &MI : *PMBB) {
+ if (MI.modifiesRegister(Reg, TRI)) return true;
+ }
+ }
+ return false;
+ };
+
+ for (unsigned i = 0; i < KnownRegs.size();) {
+ if (isClobbered(KnownRegs[i].first) ||
+ (KnownRegs[i].second.IsReg && isClobbered(KnownRegs[i].second.U.Reg))) {
+ KnownRegs[i] = KnownRegs.back();
+ KnownRegs.pop_back();
+ } else {
+ ++i;
+ }
+ }
+
+ if (KnownRegs.empty())
+ return false;
+
+ bool Changed = false;
+ MachineBasicBlock::iterator LastChange = MBB.begin();
+
+ SmallVector<MCPhysReg, 4> OptimizedRegs;
+
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
+ MachineInstr *MI = &*I;
+ ++I;
+
+ // Optimization 1: Remove redundant immediate definitions.
+ // This covers zero-idioms (XOR reg, reg; MOV32r0; MOV reg, 0) as well as
+ // move-immediates matching a known constant from CMP reg, imm.
+ if (isRedundantZeroDefinition(*MI)) {
+ Register DefReg = MI->getOperand(0).getReg();
+ auto It = llvm::find_if(KnownRegs, [&](const std::pair<MCPhysReg, KnownValue> &K) {
+ return K.first == DefReg;
+ });
+ if (It != KnownRegs.end() && !It->second.IsReg && It->second.U.Imm == 0) {
+ LLVM_DEBUG(dbgs() << "Remove redundant zero definition: " << *MI);
+ MI->eraseFromParent();
+ Changed = true;
+ LastChange = I;
+ ++NumCopiesRemoved;
+ OptimizedRegs.push_back(DefReg);
+ continue;
+ }
+ } else if (MI->isMoveImmediate() && MI->getOperand(1).isImm()) {
+ Register DefReg = MI->getOperand(0).getReg();
+ int64_t MIImm = MI->getOperand(1).getImm();
+ auto It = llvm::find_if(KnownRegs, [&](const std::pair<MCPhysReg, KnownValue> &K) {
+ return K.first == DefReg;
+ });
+ if (It != KnownRegs.end() && !It->second.IsReg &&
+ It->second.U.Imm == MIImm) {
+ LLVM_DEBUG(dbgs() << "Remove redundant immediate definition: " << *MI);
+ MI->eraseFromParent();
+ Changed = true;
+ LastChange = I;
+ ++NumCopiesRemoved;
+ OptimizedRegs.push_back(DefReg);
+ continue;
+ }
+ }
+
+ // Optimization 2: Remove redundant register copies/moves.
+ if (MI->isCopy() || MI->isMoveReg()) {
+ Register DefReg = MI->getOperand(0).getReg();
+ Register SrcReg = MI->getOperand(1).getReg();
+ auto It = llvm::find_if(KnownRegs, [&](const std::pair<MCPhysReg, KnownValue> &K) {
+ return K.first == DefReg;
+ });
+ if (It != KnownRegs.end() && It->second.IsReg && It->second.U.Reg == SrcReg) {
+ LLVM_DEBUG(dbgs() << "Remove redundant register copy: " << *MI);
+ MI->eraseFromParent();
+ Changed = true;
+ LastChange = I;
+ ++NumCopiesRemoved;
+ OptimizedRegs.push_back(DefReg);
+ continue;
+ }
+ }
+
+ // Remove clobbered registers from KnownRegs.
+ for (unsigned i = 0; i < KnownRegs.size();) {
+ if (MI->modifiesRegister(KnownRegs[i].first, TRI) ||
+ (KnownRegs[i].second.IsReg && MI->modifiesRegister(KnownRegs[i].second.U.Reg, TRI))) {
+ KnownRegs[i] = KnownRegs.back();
+ KnownRegs.pop_back();
+ } else {
+ ++i;
+ }
+ }
+ if (KnownRegs.empty())
+ break;
+ }
+
+ if (!Changed)
+ return false;
+
+ // Liveness fixups: clear kill flags along the entire extended live range.
+ for (MCPhysReg Reg : OptimizedRegs) {
+ // Clear kills in BranchMBB from FlagSetter to end (covers CondBr too).
+ for (MachineInstr &MMI :
+ make_range(MachineBasicBlock::iterator(FlagSetter), BranchMBB->end()))
+ MMI.clearRegisterKills(Reg, TRI);
+
+ if (!MBB.isLiveIn(Reg))
+ MBB.addLiveIn(Reg);
+
+ // Clear kills on Path blocks and add live-ins.
+ for (auto *PMBB : Path) {
+ if (!PMBB->isLiveIn(Reg))
+ PMBB->addLiveIn(Reg);
+ for (MachineInstr &MMI : *PMBB)
+ MMI.clearRegisterKills(Reg, TRI);
+ }
+
+ // Clear kills in MBB up to the last change.
+ for (MachineInstr &MMI : make_range(MBB.begin(), LastChange))
+ MMI.clearRegisterKills(Reg, TRI);
+ }
+
+ return true;
+}
+
+bool X86RedundantCopyEliminationImpl::run(MachineFunction &MF) {
+ TII = MF.getSubtarget().getInstrInfo();
+ TRI = MF.getSubtarget().getRegisterInfo();
+
+ bool Changed = false;
+ for (MachineBasicBlock &MBB : MF)
+ Changed |= optimizeBlock(MBB);
+ return Changed;
+}
+
+bool X86RedundantCopyEliminationLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ return X86RedundantCopyEliminationImpl().run(MF);
+}
+
+} // end anonymous namespace
+
+char X86RedundantCopyEliminationLegacy::ID = 0;
+
+INITIALIZE_PASS(X86RedundantCopyEliminationLegacy, DEBUG_TYPE,
+ "X86 redundant copy elimination pass", false, false)
+
+PreservedAnalyses
+X86RedundantCopyEliminationPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ const bool Changed = X86RedundantCopyEliminationImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+FunctionPass *llvm::createX86RedundantCopyEliminationLegacyPass() {
+ return new X86RedundantCopyEliminationLegacy();
+}
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 932669b5cbac6..d12133358bc40 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -94,6 +94,7 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() {
initializeX86SpeculativeLoadHardeningLegacyPass(PR);
initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(PR);
initializeX86FlagsCopyLoweringLegacyPass(PR);
+ initializeX86RedundantCopyEliminationLegacyPass(PR);
initializeX86LoadValueInjectionLoadHardeningLegacyPass(PR);
initializeX86LoadValueInjectionRetHardeningLegacyPass(PR);
initializeX86OptimizeLEAsLegacyPass(PR);
@@ -539,6 +540,9 @@ void X86PassConfig::addMachineSSAOptimization() {
}
void X86PassConfig::addPostRegAlloc() {
+ if (getOptLevel() != CodeGenOptLevel::None &&
+ EnableRedundantCopyElimination)
+ addPass(createX86RedundantCopyEliminationLegacyPass());
addPass(createX86LowerTileCopyLegacyPass());
addPass(createX86FPStackifierLegacyPass());
// When -O0 is enabled, the Load Value Injection Hardening pass will fall back
diff --git a/llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll b/llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
index d1d23babd33b6..9204cf25d99cc 100644
--- a/llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
+++ b/llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
@@ -29,7 +29,7 @@ define fastcc i64 @foo(ptr %p0, ptr %p1, i64 %p2, i64 %p3, ptr %p4, ptr %p5, ptr
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_7: # %bb3
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: .LBB0_8: # %cleanup
+; CHECK-NEXT: .LBB0_8: # %bb19
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12
@@ -58,7 +58,7 @@ define fastcc i64 @foo(ptr %p0, ptr %p1, i64 %p2, i64 %p3, ptr %p4, ptr %p5, ptr
; CHECK-NEXT: # %bb.20: # %bb15
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: testl %eax, %eax
-; CHECK-NEXT: je .LBB0_7
+; CHECK-NEXT: je .LBB0_8
; CHECK-NEXT: # %bb.21: # %bb15
; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: je .LBB0_7
diff --git a/llvm/test/CodeGen/X86/coalescer-commute3.ll b/llvm/test/CodeGen/X86/coalescer-commute3.ll
index 023a302e51cd2..57506da66a7cd 100644
--- a/llvm/test/CodeGen/X86/coalescer-commute3.ll
+++ b/llvm/test/CodeGen/X86/coalescer-commute3.ll
@@ -13,7 +13,7 @@ define i32 @perimeter(ptr %tree, i32 %size) nounwind {
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.1: ## %entry
; CHECK-NEXT: cmpl $2, %eax
-; CHECK-NEXT: jne LBB0_3
+; CHECK-NEXT: jne LBB0_4
; CHECK-NEXT: ## %bb.2: ## %bb
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
@@ -23,10 +23,10 @@ define i32 @perimeter(ptr %tree, i32 %size) nounwind {
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll _perimeter
; CHECK-NEXT: addl %esi, %eax
-; CHECK-NEXT: jmp LBB0_4
-; CHECK-NEXT: LBB0_3: ## %UnifiedReturnBlock
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: jmp LBB0_3
; CHECK-NEXT: LBB0_4: ## %UnifiedReturnBlock
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: LBB0_3: ## %bb50
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/conditional-tailcall.ll b/llvm/test/CodeGen/X86/conditional-tailcall.ll
index 34f11af756ad0..6b38bf97779e8 100644
--- a/llvm/test/CodeGen/X86/conditional-tailcall.ll
+++ b/llvm/test/CodeGen/X86/conditional-tailcall.ll
@@ -504,7 +504,6 @@ define zeroext i1 @pr31257(ptr nocapture readonly dereferenceable(8) %s) minsize
; WIN64-NEXT:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203733
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