[llvm] [AArch64] Split misched-fusion.ll per feature(NFC) (PR #203576)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 13 12:31:19 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Tomer Shafir (tomershafir)
<details>
<summary>Changes</summary>
This patch splits misched-fusion.ll into 2 tests one for each feature: arith+bcc and arith+cbz. As part of the refactor, it increases coverage by introducing test cases for each possible pair as well as negative test cases for positive shift operands. The patch also introduces a new structured dual testing strategy - one .ll and one .mir test for each feature, to provide codegen and misched coverage for asserts-off and asserts-on builds.
Plus apple-m5 runlines.
---
Patch is 71.09 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203576.diff
5 Files Affected:
- (added) llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll (+243)
- (added) llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir (+665)
- (added) llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll (+689)
- (added) llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir (+1501)
- (removed) llvm/test/CodeGen/AArch64/misched-fusion.ll (-48)
``````````diff
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll
new file mode 100644
index 0000000000000..9f5a8ab344e4d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll
@@ -0,0 +1,243 @@
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=cortex-a57 -mattr=+arith-bcc-fusion | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=cyclone | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=apple-m5 | FileCheck %s
+
+target triple = "aarch64-unknown"
+
+declare void @fi32(i32, i32)
+declare void @fi64(i64, i64)
+
+; CHECK-LABEL: subswri:
+; CHECK: cmp {{w[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subswri(i32 %a) {
+entry:
+ %cond = icmp eq i32 %a, 13
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subswrr:
+; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subswrr(i32 %a, i32 %b) {
+entry:
+ %cond = icmp eq i32 %a, %b
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addswri:
+; CHECK: cmn {{w[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addswri(i32 %a) {
+entry:
+ %cond = icmp eq i32 %a, -13
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addswrr:
+; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addswrr(i32 %a, i32 %b) {
+entry:
+ %nb = sub i32 0, %b
+ %cond = icmp eq i32 %a, %nb
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andswri:
+; CHECK: ands {{w[0-9]+}}, {{w[0-9]+}}, #0x1000
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andswri(i32 %a) {
+entry:
+ %v0 = and i32 %a, 4096
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andswrr:
+; CHECK: ands {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andswrr(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicswrr:
+; CHECK: bics {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @bicswrr(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subsxri:
+; CHECK: cmp {{x[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subsxri(i64 %a) {
+entry:
+ %cond = icmp eq i64 %a, 13
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subsxrr:
+; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subsxrr(i64 %a, i64 %b) {
+entry:
+ %cond = icmp eq i64 %a, %b
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addsxri:
+; CHECK: cmn {{x[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addsxri(i64 %a) {
+entry:
+ %cond = icmp eq i64 %a, -13
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addsxrr:
+; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addsxrr(i64 %a, i64 %b) {
+entry:
+ %nb = sub i64 0, %b
+ %cond = icmp eq i64 %a, %nb
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andsxri:
+; CHECK: ands {{x[0-9]+}}, {{x[0-9]+}}, #0x2000
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andsxri(i64 %a) {
+entry:
+ %v0 = and i64 %a, 8192
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andsxrr:
+; CHECK: ands {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andsxrr(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicsxrr:
+; CHECK: bics {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @bicsxrr(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir
new file mode 100644
index 0000000000000..ffa2769469978
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir
@@ -0,0 +1,665 @@
+# REQUIRES: asserts
+
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mattr=+arith-bcc-fusion -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=cyclone -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWri $w0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWri $w0, 13, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_addswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWri $w0, 4096, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWri $w0, 4096, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_andswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWri $w0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWri $w0, 13, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_subswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_bicswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXri $x0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXri $x0, 13, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_addsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXri $x0, 8192, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXri $x0, 8192, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_andsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXri $x0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXri $x0, 13, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_subsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Suc...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203576
More information about the llvm-commits
mailing list