[llvm] Aarch64 add missing arith to cbz clustering (PR #203721)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 13 12:31:10 PDT 2026
https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/203721
None
>From b5dcf7073d23797183ebe09842c6b9fc6f9dd0ed Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Fri, 12 Jun 2026 14:39:27 +0300
Subject: [PATCH 1/2] [AArch64] Split misched-fusion.ll per feature(NFC)
This patch splits misched-fusion.ll into 2 tests one for each feature: arith+bcc and arith+cbz. As part of the refactor, it increases coverage by introducing test cases for each possible pair as well as negative test cases for positive shift operands. The patch also introduces a new structured dual testing strategy - one .ll and one .mir test for each feature, to provide codegen and misched coverage for asserts-off and asserts-on builds.
Plus apple-m5 runlines.
---
.../AArch64/misched-fusion-arith-bcc.ll | 243 +++
.../AArch64/misched-fusion-arith-bcc.mir | 665 ++++++++
.../AArch64/misched-fusion-arith-cbz.ll | 689 ++++++++
.../AArch64/misched-fusion-arith-cbz.mir | 1501 +++++++++++++++++
llvm/test/CodeGen/AArch64/misched-fusion.ll | 48 -
5 files changed, 3098 insertions(+), 48 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll
create mode 100644 llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir
create mode 100644 llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
create mode 100644 llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
delete mode 100644 llvm/test/CodeGen/AArch64/misched-fusion.ll
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll
new file mode 100644
index 0000000000000..9f5a8ab344e4d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.ll
@@ -0,0 +1,243 @@
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=cortex-a57 -mattr=+arith-bcc-fusion | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=cyclone | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -mcpu=apple-m5 | FileCheck %s
+
+target triple = "aarch64-unknown"
+
+declare void @fi32(i32, i32)
+declare void @fi64(i64, i64)
+
+; CHECK-LABEL: subswri:
+; CHECK: cmp {{w[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subswri(i32 %a) {
+entry:
+ %cond = icmp eq i32 %a, 13
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subswrr:
+; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subswrr(i32 %a, i32 %b) {
+entry:
+ %cond = icmp eq i32 %a, %b
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addswri:
+; CHECK: cmn {{w[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addswri(i32 %a) {
+entry:
+ %cond = icmp eq i32 %a, -13
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addswrr:
+; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addswrr(i32 %a, i32 %b) {
+entry:
+ %nb = sub i32 0, %b
+ %cond = icmp eq i32 %a, %nb
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %a)
+ br label %exit
+exit:
+ call void @fi32(i32 %a, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andswri:
+; CHECK: ands {{w[0-9]+}}, {{w[0-9]+}}, #0x1000
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andswri(i32 %a) {
+entry:
+ %v0 = and i32 %a, 4096
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andswrr:
+; CHECK: ands {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andswrr(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicswrr:
+; CHECK: bics {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @bicswrr(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %cond = icmp slt i32 %v0, 0
+ %v1 = add i32 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subsxri:
+; CHECK: cmp {{x[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subsxri(i64 %a) {
+entry:
+ %cond = icmp eq i64 %a, 13
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subsxrr:
+; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @subsxrr(i64 %a, i64 %b) {
+entry:
+ %cond = icmp eq i64 %a, %b
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addsxri:
+; CHECK: cmn {{x[0-9]+}}, #13
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addsxri(i64 %a) {
+entry:
+ %cond = icmp eq i64 %a, -13
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addsxrr:
+; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @addsxrr(i64 %a, i64 %b) {
+entry:
+ %nb = sub i64 0, %b
+ %cond = icmp eq i64 %a, %nb
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %a)
+ br label %exit
+exit:
+ call void @fi64(i64 %a, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andsxri:
+; CHECK: ands {{x[0-9]+}}, {{x[0-9]+}}, #0x2000
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andsxri(i64 %a) {
+entry:
+ %v0 = and i64 %a, 8192
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andsxrr:
+; CHECK: ands {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @andsxrr(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicsxrr:
+; CHECK: bics {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: b.{{[a-z][a-z]}}
+define void @bicsxrr(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %cond = icmp slt i64 %v0, 0
+ %v1 = add i64 %a, 7
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir
new file mode 100644
index 0000000000000..ffa2769469978
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-bcc.mir
@@ -0,0 +1,665 @@
+# REQUIRES: asserts
+
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mattr=+arith-bcc-fusion -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=cyclone -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWri $w0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWri $w0, 13, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_addswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWri $w0, 4096, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWri $w0, 4096, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_andswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWri $w0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWri $w0, 13, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_subswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrr $w0, $w1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicswrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrr $w0, $w1, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrs $w0, $w1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrs $w0, $w1, 0, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICSWrs $w0, $w1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_bicswrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICSWrs $w0, $w1, 12, implicit-def $nzcv
+ $w3 = ORRWri $w2, 4096
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXri $x0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXri $x0, 13, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: addsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_addsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXri $x0, 8192, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXri $x0, 8192, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: andsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_andsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXri $x0, 13, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxri
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXri $x0, 13, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: subsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_subsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICSXrr $x0, $x1, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicsxrr
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICSXrr $x0, $x1, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICSXrs $x0, $x1, 0, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: bicsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICSXrs $x0, $x1, 0, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICSXrs $x0, $x1, 12, implicit-def $nzcv
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: Bcc
+---
+name: no_fuse_positive_shift_bicsxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICSXrs $x0, $x1, 12, implicit-def $nzcv
+ $x3 = ORRXri $x2, 8192
+ Bcc 0, %bb.2, implicit $nzcv
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
new file mode 100644
index 0000000000000..0355de12d448c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
@@ -0,0 +1,689 @@
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cortex-a57 -mattr=+arith-cbz-fusion | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cyclone | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=apple-m5 | FileCheck %s
+
+target triple = "aarch64-unknown"
+
+declare void @fi32(i32, i32)
+declare void @fi64(i64, i64)
+
+; CHECK-LABEL: addwri_cbz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @addwri_cbz(i32 %a) {
+entry:
+ %v0 = add i32 %a, 13
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addwri_cbnz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @addwri_cbnz(i32 %a) {
+entry:
+ %v0 = add i32 %a, 13
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addwrr_cbz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @addwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %v0 = add i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addwrr_cbnz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @addwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = add i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andwri_cbz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @andwri_cbz(i32 %a) {
+entry:
+ %v0 = and i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andwri_cbnz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @andwri_cbnz(i32 %a) {
+entry:
+ %v0 = and i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andwrr_cbz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @andwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andwrr_cbnz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @andwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwri_cbz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @eorwri_cbz(i32 %a) {
+entry:
+ %v0 = xor i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwri_cbnz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @eorwri_cbnz(i32 %a) {
+entry:
+ %v0 = xor i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwrr_cbz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @eorwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %v0 = xor i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwrr_cbnz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @eorwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = xor i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwri_cbz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @orrwri_cbz(i32 %a) {
+entry:
+ %v0 = or i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwri_cbnz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @orrwri_cbnz(i32 %a) {
+entry:
+ %v0 = or i32 %a, 255
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwrr_cbz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @orrwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %v0 = or i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwrr_cbnz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @orrwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = or i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwri_cbz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @subwri_cbz(i32 %a) {
+entry:
+ %v0 = sub i32 %a, 13
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwri_cbnz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @subwri_cbnz(i32 %a) {
+entry:
+ %v0 = sub i32 %a, 13
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwrr_cbz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @subwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %v0 = sub i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwrr_cbnz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @subwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = sub i32 %a, %b
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxri_cbz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @addxri_cbz(i64 %a) {
+entry:
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxri_cbnz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @addxri_cbnz(i64 %a) {
+entry:
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxrr_cbz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @addxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = add i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxrr_cbnz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @addxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = add i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andxri_cbz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @andxri_cbz(i64 %a) {
+entry:
+ %v0 = and i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andxri_cbnz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @andxri_cbnz(i64 %a) {
+entry:
+ %v0 = and i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andxrr_cbz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @andxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andxrr_cbnz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @andxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxri_cbz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @eorxri_cbz(i64 %a) {
+entry:
+ %v0 = xor i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxri_cbnz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @eorxri_cbnz(i64 %a) {
+entry:
+ %v0 = xor i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxrr_cbz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @eorxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = xor i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxrr_cbnz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @eorxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = xor i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxri_cbz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @orrxri_cbz(i64 %a) {
+entry:
+ %v0 = or i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxri_cbnz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @orrxri_cbnz(i64 %a) {
+entry:
+ %v0 = or i64 %a, 255
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxrr_cbz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @orrxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = or i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxrr_cbnz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @orrxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = or i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxri_cbz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @subxri_cbz(i64 %a) {
+entry:
+ %v0 = sub i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxri_cbnz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @subxri_cbnz(i64 %a) {
+entry:
+ %v0 = sub i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxrr_cbz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @subxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = sub i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxrr_cbnz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @subxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = sub i64 %a, %b
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
new file mode 100644
index 0000000000000..4eb2980431cd3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
@@ -0,0 +1,1501 @@
+# REQUIRES: asserts
+
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mattr=+arith-cbz-fusion -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=cyclone -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+# RUN: llc -o /dev/null %s -mtriple=aarch64-unknown -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags 2>&1 | FileCheck %s
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: addwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: addwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: addwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: addwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: addwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: addwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_addwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ADDWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: andwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: andwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: andwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: andwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: andwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: andwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_andwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ANDWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: eorwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: eorwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: eorwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: eorwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_eorwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: orrwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: orrwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: orrwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: orrwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_orrwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: subwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: subwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: subwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: subwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: subwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: subwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_subwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: bicwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: bicwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_bicwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: addxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: addxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: addxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: addxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: addxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: addxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_addxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: andxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: andxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: andxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: andxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: andxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: andxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_andxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: eorxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: eorxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: eorxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: eorxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_eorxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: orrxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: orrxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: orrxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: orrxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_orrxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: subxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: subxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: subxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: subxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: subxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: subxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_subxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = SUBXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: bicxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: bicxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_bicxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion.ll b/llvm/test/CodeGen/AArch64/misched-fusion.ll
deleted file mode 100644
index 75fbfac7bcd50..0000000000000
--- a/llvm/test/CodeGen/AArch64/misched-fusion.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cortex-a57 -mattr=+arith-bcc-fusion | FileCheck %s --check-prefix=FUSEBCC
-; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cortex-a57 -mattr=+arith-cbz-fusion | FileCheck %s --check-prefix=FUSECBZ
-; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cyclone | FileCheck %s --check-prefix=FUSEBCC --check-prefix=FUSECBZ
-
-target triple = "aarch64-unknown"
-
-declare void @foobar(i32 %v0, i32 %v1)
-
-; Make sure cmp is scheduled in front of bcc
-; FUSEBCC-LABEL: test_cmp_bcc:
-; FUSEBCC: cmp {{w[0-9]+}}, #13
-; FUSEBCC-NEXT: b.ne {{.?LBB[0-9_]+}}
-define void @test_cmp_bcc(i32 %a0, i32 %a1) {
-entry:
- %cond = icmp eq i32 %a0, 13
- %v1 = add i32 %a1, 7
- br i1 %cond, label %if, label %exit
-
-if:
- call void @foobar(i32 %v1, i32 %a0)
- br label %exit
-
-exit:
- call void @foobar(i32 %a0, i32 %v1)
- ret void
-}
-
-; Make sure sub is scheduled in front of cbnz
-; FUSECBZ-LABEL: test_sub_cbz:
-; FUSECBZ: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
-; FUSECBZ-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
-define void @test_sub_cbz(i32 %a0, i32 %a1) {
-entry:
- ; except for the fusion opportunity the sub/add should be equal so the
- ; scheduler would leave them in source order if it weren't for the scheduling
- %v0 = sub i32 %a0, 13
- %cond = icmp eq i32 %v0, 0
- %v1 = add i32 %a1, 7
- br i1 %cond, label %if, label %exit
-
-if:
- call void @foobar(i32 %v1, i32 %v0)
- br label %exit
-
-exit:
- call void @foobar(i32 %v0, i32 %v1)
- ret void
-}
>From 59e37a182ff34c108cdcd0c089d8bf5c06f95ba2 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Sat, 13 Jun 2026 10:47:53 +0300
Subject: [PATCH 2/2] [AArch64] Add missing arithmetic to arith+cb(n)z
clustering
This patch adds a few missing opcodes for arithmetic+CB(N)Z clustering. Most of them complement an already existing rr/rs variant for pre/post-RA coverage. The only one which is completely new is ORN which I think can be reasonably expectedd to behave similarly on AArch64 targets.
---
.../lib/Target/AArch64/AArch64MacroFusion.cpp | 10 +
.../AArch64/misched-fusion-arith-cbz.ll | 144 +++++
.../AArch64/misched-fusion-arith-cbz.mir | 492 +++++++++++++++++-
3 files changed, 642 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
index bd4ef12a94b35..e00bbdd3db0a0 100644
--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -97,15 +97,25 @@ static bool isArithmeticCbzPair(const MachineInstr *FirstMI,
case AArch64::ORRWrr:
case AArch64::ORRXri:
case AArch64::ORRXrr:
+ case AArch64::ORNWrr:
+ case AArch64::ORNXrr:
case AArch64::SUBWri:
case AArch64::SUBWrr:
case AArch64::SUBXri:
case AArch64::SUBXrr:
+ case AArch64::BICWrr:
+ case AArch64::BICXrr:
return true;
case AArch64::ADDWrs:
case AArch64::ADDXrs:
case AArch64::ANDWrs:
case AArch64::ANDXrs:
+ case AArch64::EORWrs:
+ case AArch64::EORXrs:
+ case AArch64::ORNWrs:
+ case AArch64::ORNXrs:
+ case AArch64::ORRWrs:
+ case AArch64::ORRXrs:
case AArch64::SUBWrs:
case AArch64::SUBXrs:
case AArch64::BICWrs:
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
index 0355de12d448c..a82fa5017a6b7 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
@@ -279,6 +279,78 @@ exit:
ret void
}
+; CHECK-LABEL: ornwrr_cbz:
+; CHECK: orn [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @ornwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = or i32 %a, %n
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: ornwrr_cbnz:
+; CHECK: orn [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @ornwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = or i32 %a, %n
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicwrr_cbz:
+; CHECK: bic [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @bicwrr_cbz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %v1 = add i32 %a, 7
+ %cond = icmp ne i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicwrr_cbnz:
+; CHECK: bic [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @bicwrr_cbnz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %v1 = add i32 %a, 7
+ %cond = icmp eq i32 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: subwri_cbz:
; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -619,6 +691,78 @@ exit:
ret void
}
+; CHECK-LABEL: ornxrr_cbz:
+; CHECK: orn [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @ornxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = or i64 %a, %n
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: ornxrr_cbnz:
+; CHECK: orn [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @ornxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = or i64 %a, %n
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicxrr_cbz:
+; CHECK: bic [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @bicxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicxrr_cbnz:
+; CHECK: bic [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @bicxrr_cbnz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: subxri_cbz:
; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
index 4eb2980431cd3..fe007e8252dab 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
@@ -402,6 +402,50 @@ body: |
# CHECK-LABEL: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: eorwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = EORWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: eorwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = EORWrs $w0, $w1, 12
+# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK-LABEL: ExitSU: CBNZW
---
@@ -413,7 +457,117 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrs $w0, $w1, 0
+ $w0 = EORWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORNWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: ornwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORNWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: ornwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORNWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: ornwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORNWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: ornwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORNWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_ornwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 12
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -512,6 +666,50 @@ body: |
# CHECK-LABEL: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: orrwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: orrwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $w0 = ORRWrs $w0, $w1, 12
+# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK-LABEL: ExitSU: CBNZW
---
@@ -523,7 +721,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrs $w0, $w1, 0
+ $w0 = ORRWrs $w0, $w1, 12
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -686,6 +884,50 @@ body: |
RET undef $lr
...
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZW
+---
+name: bicwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZW
+---
+name: bicwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
# CHECK-LABEL: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
@@ -1150,6 +1392,50 @@ body: |
# CHECK-LABEL: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: eorxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = EORXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: eorxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = EORXrs $x0, $x1, 12
+# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK-LABEL: ExitSU: CBNZX
---
@@ -1161,7 +1447,117 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrs $x0, $x1, 0
+ $x0 = EORXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORNXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: ornxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORNXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORNXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: ornxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORNXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORNXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: ornxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORNXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORNXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: ornxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORNXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORNXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_ornxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORNXrs $x0, $x1, 12
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1260,6 +1656,50 @@ body: |
# CHECK-LABEL: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: orrxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORRXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: orrxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ORRXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU(0): $x0 = ORRXrs $x0, $x1, 12
+# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK-LABEL: ExitSU: CBNZX
---
@@ -1271,7 +1711,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrs $x0, $x1, 0
+ $x0 = ORRXrs $x0, $x1, 12
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1434,6 +1874,50 @@ body: |
RET undef $lr
...
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBZX
+---
+name: bicxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-LABEL: ExitSU: CBNZX
+---
+name: bicxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = BICXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
# CHECK-LABEL: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
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