[llvm] [ARM] Port Redundant Copy Elimination to ARM (PR #203706)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/ARM/ARMRedundantCopyElimination.cpp llvm/lib/Target/ARM/ARM.h llvm/lib/Target/ARM/ARMTargetMachine.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMRedundantCopyElimination.cpp b/llvm/lib/Target/ARM/ARMRedundantCopyElimination.cpp
index f3f0a69e2..75bcd8757 100644
--- a/llvm/lib/Target/ARM/ARMRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/ARM/ARMRedundantCopyElimination.cpp
@@ -172,7 +172,8 @@ static bool isRedundantZeroAssign(const MachineInstr &MI, MCPhysReg DefReg,
     if (KnownReg.Reg != DefReg)
       continue;
     int64_t ImmVal;
-    if (MI.isMoveImmediate() && getMoveImmediateValue(MI, ImmVal) && ImmVal == 0)
+    if (MI.isMoveImmediate() && getMoveImmediateValue(MI, ImmVal) &&
+        ImmVal == 0)
       return true;
     if (MI.isCopy() && isKnownZeroSource(MI, KnownRegs))
       return true;
@@ -208,16 +209,16 @@ static bool isRedundantEqualRegAssign(const MachineInstr &MI,
 static bool shouldStopPredScan(ArrayRef<RegImm> KnownRegs,
                                ArrayRef<RegEqual> KnownEqualRegs,
                                const LiveRegUnits &Clobbered) {
-  bool AnyKnownReg = any_of(KnownRegs, [&](const RegImm &K) {
-    return Clobbered.available(K.Reg);
-  });
+  bool AnyKnownReg = any_of(
+      KnownRegs, [&](const RegImm &K) { return Clobbered.available(K.Reg); });
   bool AnyKnownEqual = any_of(KnownEqualRegs, [&](const RegEqual &Eq) {
     return Clobbered.available(Eq.Reg1) && Clobbered.available(Eq.Reg2);
   });
   return !AnyKnownReg && !AnyKnownEqual;
 }
 
-static void propagateEqualRegThroughCopy(MCPhysReg CopyDstReg, MCPhysReg CopySrcReg,
+static void propagateEqualRegThroughCopy(MCPhysReg CopyDstReg,
+                                         MCPhysReg CopySrcReg,
                                          ArrayRef<RegEqual> KnownEqualRegs,
                                          SmallVectorImpl<RegEqual> &Out) {
   Out.push_back(RegEqual(CopyDstReg, CopySrcReg));
@@ -235,8 +236,7 @@ static void propagateEqualRegThroughCopy(MCPhysReg CopyDstReg, MCPhysReg CopySrc
 
 bool ARMRedundantCopyEliminationImpl::getCBZKnownRegs(
     MachineInstr &CondBr, MachineBasicBlock *MBB,
-    SmallVectorImpl<RegImm> &KnownRegs,
-    MachineBasicBlock::iterator &FirstUse) {
+    SmallVectorImpl<RegImm> &KnownRegs, MachineBasicBlock::iterator &FirstUse) {
   unsigned Opc = CondBr.getOpcode();
   if (Opc != ARM::tCBZ && Opc != ARM::tCBNZ)
     return false;

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https://github.com/llvm/llvm-project/pull/203706